JPH1083388A - Orthogonal transformer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a two-dimensional discrete cosine transformer realizing optional weighting of a converting result without using any multiplier. SOLUTION: The two-dimensional discrete cosine transfonrmer (two-dimensional DCT device) consists of two one-dimensional DCT circuits 11 and 13 and an inverted memory 12 interposed between them. Each of the two circuits 11 and 13 incorporates a butterfly arithmetic circuit and a distribution arithmetic circuit at its postage and previously stores the partial sum of vector inner products based on a constant matrix, which is obtained by multiplying the weight of frequency dependency corresponding to human visibility to each element of the discrete cosine matrix, in ROM in the distribution arithmetic circuit to obtain the result of one-dimensional DCT weighted by using the stored contents of this ROM. For example, in a picture compression-encoding system, compression efficiency is improved compared with a case without weighting.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an orthogonal transformation device suitably used for image information processing, audio information processing, and the like.

[0002]

2. Description of the Related Art For example, in a compression coding method of an image,
There is a need for a small-scale orthogonal transform device for converting a signal in the spatial domain into a signal in the frequency domain. In the encoder, a forward orthogonal transform, for example, a discrete cosine transform (Discrete C
sine transform (DCT), discrete sine transform (Discre
te Sine Transform: DST) is adopted. In the decoder, an orthogonal transform in the reverse direction, for example, an inverse discrete cosine transform (IDCT),
Inverse Discrete Sine Transform
: IDST) and the like.

US Pat. No. 4,791,598 discloses a two-dimensional DCT device comprising two one-dimensional DCT circuits and a transposition memory interposed therebetween. Each of the two one-dimensional DCT circuits employs a so-called high-speed algorithm and a distributed operation (Distributed Arithmetic: DA) method, and includes a butterfly operation circuit composed of a plurality of adders and subtractors. And a distribution operation circuit for obtaining a vector inner product using a ROM (Read Only Memory) without using a multiplier at a subsequent stage. The distribution operation circuit includes a plurality of ROM / accumulators (ROM
and Accumulator (RAC). Each RAC
Is a ROM storing a partial sum of a vector dot product based on a discrete cosine matrix in the form of a look-up table,
An accumulator for performing digit-alignment addition of partial sums indexed sequentially from the OM using the bit slice word as an address to obtain a vector inner product corresponding to the input vector. In the one-dimensional IDCT circuit, a butterfly operation circuit is arranged at a stage subsequent to a plurality of RACs constituting the distribution operation circuit.

[0004] In general, human visibility is lower for high frequency components than for low frequency components. Therefore, a technique of multiplying the low-frequency component of the one-dimensional DCT result by a large weight and multiplying the high-frequency component by a small weight before performing the encoding is employed in a DVC (Digital Video Cassette) or the like to improve the compression efficiency. Have been. However, if a one-dimensional DCT result is obtained and multiplication for weighting the frequency dependence is performed on the result, an extra multiplier is required. U.S. Pat. No. 5,117,381 proposes an 8-point one-dimensional DCT circuit that can achieve limited weighting. In this circuit, a multiplier for performing multiplication of input data and elements of a discrete cosine matrix is also used for weighting.

[0005]

The above U.S. Pat.
The one-dimensional DCT circuit proposed in US Pat. No. 7,381 has a problem that its application range is limited to 8-point DCT and cannot realize arbitrary weighting, and is disclosed in the above-mentioned US Pat. No. 4,791,598. There is also a problem that a circuit scale and power consumption are large in using a multiplier as compared with a one-dimensional DCT circuit.

The two-dimensional DCT device disclosed in the above-mentioned US Pat. No. 4,791,598 has two one-dimensional DTs when handling an input data matrix composed of N × N elements.
Each of the CT circuits performed N-point one-dimensional DCT. In this case, each of the two one-dimensional DCT circuits includes N RACs. That is, US Pat.
The two-dimensional DCT apparatus disclosed in No. 791,598 needs to have a total of 2N RACs, and has a problem that a circuit scale and power consumption are large.

An object of the present invention is to provide an orthogonal transform apparatus which can realize arbitrary weighting on a transform result without using any multiplier.

Another object of the present invention is to reduce the number of RACs in a two-dimensional DCT device.

[0009]

In order to achieve the above object, in the case of orthogonal transformation, the present invention provides a vector inner product based on a constant matrix obtained by multiplying each element of an orthogonal transformation matrix by a frequency-dependent weight. In the case of the inverse orthogonal transform, the partial sum of the vector inner product based on the constant matrix obtained by dividing each element of the inverse orthogonal transform matrix by the frequency-dependent weight in the case of the inverse orthogonal transform is looked up in the distribution arithmetic circuit This is stored in a table, and weighted conversion is realized using the stored contents of the lookup table. According to the present invention, the original orthogonal transform and the weighting are simultaneously executed, and the original inverse orthogonal transform and the deweighting are simultaneously executed. That is, adoption of the DA method not only eliminates the need for a multiplier for performing multiplication of input data and elements of an orthogonal transformation matrix or an inverse orthogonal transformation matrix, but also provides a multiplier for weighting and a function for canceling weighting. Also eliminates the need for a divider. Moreover, any weight can be applied to the conversion result without being restricted by the type of conversion or the number of points.

Further, the present invention realizes an 8 × 8 element two-dimensional DCT by using three one-dimensional DCT circuits for executing, for example, four-point one-dimensional DCT. More specifically, in an apparatus for performing two-dimensional DCT of an input data matrix composed of N × N elements, N / N of N input vectors each composed of N elements are used.
By sequentially executing two-point one-dimensional DCT, N
By sequentially executing a first circuit for generating each half of the first N-point transform results and N / 2-point one-dimensional DCTs relating to N transposed vectors each including N elements. A second circuit for generating each half of the N second N-point transform results, and the other N / 2-point one-dimensional DCTs for the N input vectors are sequentially executed. Generate the other half of each of the N first N-point transform results and sequentially perform the other N / 2-point one-dimensional DCTs on the N transposed vectors by using the N second N-point transform results. A third circuit for generating the other half of each of the N-point conversion results of
And the N first N-point transform results generated by the third circuit and store the N transposed vectors in the second
And a transposition memory for supplying to the third circuit.
The N second N-point conversion results generated by the second and third circuits are converted to a two-dimensional DC of the input data matrix.
Output as a T result. According to the invention,
A first dimension N-point DCT is performed by the first and third circuits, and a second dimension N-point DCT is performed by the second and third circuits. The first, second, and third circuits each include N / 2 RACs. That is, according to the present invention, the number of RACs of the two-dimensional DCT apparatus is 2N to 3
N / 2. Note that the two-dimensional IDCT device is similarly configured.

The first and second circuits have a one-stage butterfly operation circuit, and the third circuit has a two-stage butterfly operation circuit. N / 2 lookup tables are provided in each of the distribution operation circuits of the first, second, and third circuits, and a partial sum in units of 2 bits is obtained from each of the lookup tables of the first and second circuits. Assuming that partial sums in 4-bit units are respectively indexed from the lookup tables of the third circuit, the processing speed of the third circuit is twice as fast as the processing speed of the first and second circuits. Therefore, the time sharing operation of the third circuit becomes possible.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific examples of an orthogonal transform device and an inverse orthogonal transform device according to the present invention will be described with reference to the drawings.

FIG. 1 shows an example of the configuration of a two-dimensional DCT device according to the present invention. The two-dimensional DCT device of FIG.
, A transposing memory 12, and a second one-dimensional DCT circuit 13. As shown in FIG. 2, the first one-dimensional DCT circuit 11 includes a butterfly operation circuit 14 and a distribution operation circuit 15 at the subsequent stage, and each element of an 8 × 8 discrete cosine matrix has frequency dependence. Are stored in eight ROMs in the distribution calculation circuit 15, and an input vector is formed using the stored contents of the eight ROMs. 8 elements Xi (i = 0, 1,...,
7) is a circuit configured to obtain eight elements Yi ′ constituting a part of the one-dimensional DCT result subjected to the first-dimensional weighting from 7). These weighted elements Yi '
It is stored in the transposition memory 12 as a row vector. Then, when the storage of the eight row vectors in the transposition memory 12 is completed, reading of the column vectors from the transposition memory 12 starts, and the read column vectors are stored in the second one-dimensional D
Eight elements Uj constituting an input vector in the CT circuit 13
(J = 0, 1,..., 7). Similarly to the first one-dimensional DCT circuit 11, the second one-dimensional DCT circuit 13 forms a part of a two-dimensional weighted two-dimensional DCT result from the supplied eight elements Uj. This is a circuit configured to determine the number of elements Vj '. These weighted elements Vj 'are output from the two-dimensional DCT apparatus of FIG. 1 as eight elements indicating the column vectors of the two-dimensional weighted DCT result. Two-dimensional weighted D
The entire CT result is composed of eight column vectors. Note that the handling of the row vector and the column vector may be reversed.

FIG. 3 is an explanatory diagram of a basic discrete cosine matrix. According to FIG. 3, an unweighted one-dimensional DCT is obtained by multiplying an 8 × 8 discrete cosine matrix 21 by an input vector including eight elements Xi (i = 0, 1,..., 7). Eight elements Yi that form part of the result are obtained. Here, each element of the discrete cosine matrix 21 complies with the definition of Ci = cos (iπ / 16) i = 1, 2,.

FIG. 4 is an explanatory diagram of a discrete cosine matrix when a butterfly operation is employed. According to FIG. 4, an input vector composed of eight elements Xi (i = 0, 1,..., 7) is converted into eight elements A by a butterfly operation expression 22.
It is converted to an intermediate vector composed of i. And 8
A discrete cosine matrix 23 of 8 rows and 8 elements Ai (i
= 0, 1,..., 7), eight elements Yi constituting a part of the unweighted one-dimensional DCT result are obtained. This multiplication is executed by the distribution operation circuit without using a multiplier. Moreover, since half of all the elements of the discrete cosine matrix 23 in FIG. 4 are 0, the amount of calculation is reduced as compared with the case of FIG.

FIG. 5 is an explanatory diagram of a weighted constant matrix used in the first one-dimensional DCT circuit 11 in FIG. Here, the eight frequency-dependent weights Wi (i = 0,
1, 7) are introduced. For example, W0 = 1.00, W
1 = 0.98, W2 = 0.95, W3 = 0.90, W4
= 0.85, W5 = 0.80, W6 = 0.75, W7 =
0.70. The relationship between the eight weighted elements Yi ′ and the eight unweighted elements Yi according to the one-dimensional DCT result is as follows: Yi ′ = WiYi i = 0, 1,. Therefore, as shown in FIG. 5, a constant matrix 24 obtained by multiplying each element of the discrete cosine matrix 23 in FIG. 4 by a corresponding weight, and eight elements Ai (i = 0,
,..., 7), the eight elements Y constituting a part of the one-dimensional weighted DCT result by multiplication with an intermediate vector (determined by the butterfly operation circuit 14).
i 'is obtained. This multiplication is executed by the distribution operation circuit 15 without using a multiplier. Moreover, since half of all elements of the weighted constant matrix 24 in FIG. 5 are 0,
A small-capacity ROM can be employed in the distribution calculation circuit 15. Note that the second one-dimensional DCT circuit 13 in FIG.
A matrix similar to the weighted constant matrix 24 in FIG. 5 is used.

FIG. 6 shows a configuration example of a two-dimensional IDCT apparatus according to the present invention. The two-dimensional IDCT device in FIG.
A first one-dimensional IDCT circuit 31, a transposition memory 32,
A second one-dimensional IDCT circuit 33 is provided. As shown in FIG. 7, the first one-dimensional IDCT circuit 31 includes a distribution operation circuit 34 and a butterfly operation circuit 35 at a subsequent stage.
And a partial sum of a vector inner product based on a constant matrix obtained by dividing each element of an 8-row, 8-column inverse discrete cosine matrix by a frequency-dependent weight.
OM, and the eight weighted elements Vi 'constituting the input vector using the storage contents of the eight ROMs.
This is a circuit configured to obtain eight elements Ui that form a part of the one-dimensional IDCT result from which the first-dimensional weight has been released from (i = 0, 1,..., 7). The elements Ui for which the first-dimensional weighting has been released are stored in the transposition memory 32 as row vectors. When the storage of the eight row vectors in the transposition memory 32 is completed,
The reading of the column vector from the transposition memory 32 starts, and the read column vector is used by the eight one-dimensional IDCT circuit 33 to form eight weighted elements Y constituting an input vector.
j ′ (j = 0, 1,..., 7). Similarly to the first one-dimensional IDCT circuit 31, the second one-dimensional IDCT circuit 33 is a part of the two-dimensional IDCT result in which the two-dimensional weighting is removed from the supplied eight weighted elements Yj '. Is a circuit configured to obtain eight elements Xj that constitute. These two-dimensional weighted elements Xj are output from the two-dimensional IDCT device in FIG. 6 as eight elements indicating column vectors of the two-dimensional weighted IDCT results. The entirety of the two-dimensional IDCT result completely de-weighted is composed of eight column vectors. Note that the handling of the row vector and the column vector may be reversed.

FIG. 8 is an explanatory diagram of a basic inverse discrete cosine matrix. According to FIG. 8, an 8 × 8 inverse discrete cosine matrix 41 and eight unweighted elements Vi (i = 0, 1, 1)
.., 7) by multiplication with the input vector
Eight elements Ui constituting a part of the dimension IDCT result are obtained.

FIG. 9 is an explanatory diagram of an inverse discrete cosine matrix when a butterfly operation is employed. According to FIG.
Eight elements constituting an intermediate vector are obtained by multiplying an inverse discrete cosine matrix 42 having eight rows and an input vector composed of eight elements Vi (i = 0, 1,..., 7) without weights Bi is obtained. This multiplication is executed by the distribution operation circuit without using a multiplier. And eight elements Bi
An intermediate vector composed of (i = 0, 1,..., 7) is
The butterfly operation expression 43 converts the vector into a desired vector forming a part of the one-dimensional IDCT result composed of eight elements Ui. Moreover, the inverse discrete cosine matrix 42 in FIG.
Is 0, so that the amount of calculation is reduced as compared with the case of FIG. 8, so that a small-capacity ROM can be employed in the distribution operation circuit.

FIG. 10 shows the first one-dimensional IDCT in FIG.
FIG. 4 is an explanatory diagram of a weighted constant matrix used in the circuit 31. The eight frequency-dependent weights W used here
i (i = 0, 1,..., 7) is the same as in DCT. The relationship between the eight unweighted elements Vi and the eight weighted elements Vi ′ relating to the input of the one-dimensional IDCT is as follows: Vi = Vi ′ / Wi i = 0, 1,... Therefore, as shown in FIG. 10, a constant matrix 44 obtained by dividing each element of the inverse discrete cosine matrix 42 in FIG. 9 by the corresponding weight, and eight weighted elements V
By multiplication with an input vector composed of i ′ (i = 0, 1,..., 7), eight elements Bi constituting an intermediate vector whose first-dimensional weight has been released are obtained. This multiplication is executed by the distribution operation circuit 34 without using a multiplier. Then, eight elements Bi (i = 0, 1,..., 7)
The intermediate vector constituted by
, The eight elements U
It is converted into a desired vector that forms part of the one-dimensional IDCT result composed of i. Moreover, since half of all the elements of the weighted constant matrix 44 in FIG. 10 are 0, a small-capacity ROM can be employed in the distribution calculation circuit 34. Note that the second one-dimensional IDCT circuit 33 in FIG.
A matrix similar to the weighted constant matrix 44 in 0 is used.

The above example is an 8-point DCT and I-point.
Although the DCT is an example, the scope of the present invention is not limited by the type of transformation or the number of points.
That is, the invention described with reference to FIGS. 1 to 10 can be widely applied to an N-point orthogonal transform apparatus and an inverse orthogonal transform apparatus. For example, N points DST, IDS
It is also applicable to T and the like.

FIG. 11 shows another configuration example of the two-dimensional DCT apparatus according to the present invention. The two-dimensional DCT device of FIG. 11 includes first, second, and third one-dimensional DCT circuits 51, 52, and 53 for executing four-point one-dimensional DCT.
And a transposition memory 54 of 8 × 8 words, and a third one-dimensional D
A multiplexer 55 for switching the input of the CT circuit 53 and a control circuit 56 for receiving the start pulse and the clock and controlling the operation of each section. The first and third one-dimensional DCT circuits 51 and 53 are:
Eight elements Xi (i = 0, 1, 1) constituting the input vector
, 7) constitute a part of the first-dimensional DCT result 8
This is a circuit configured to determine the number of elements Yi. These elements Yi are stored in the transposition memory 54 as row vectors. When the storage of the eight row vectors in the transposition memory 54 is completed, the reading of the column vectors from the transposition memory 54 starts, and the read column vectors (transposition vectors) are stored in the second and third 1s. Eight elements Uj constituting an input vector in the two-dimensional DCT circuits 52 and 53
(J = 0, 1,..., 7). The second and third one-dimensional DCT circuits 52 and 53 form a part of a second-dimensional DCT result from the supplied eight elements Uj.
Elements Vj are obtained. These elements Vj are output from the two-dimensional DCT apparatus in FIG. 11 as eight elements indicating column vectors of the two-dimensional DCT result. 2D
The entire CT result is composed of eight column vectors. Note that the handling of the row vector and the column vector may be reversed.

FIG. 12 shows the internal configuration and operation of each of the first and third one-dimensional DCT circuits 51 and 53. The first one-dimensional DCT circuit 51 includes a one-stage butterfly operation circuit 61 and a subsequent-stage distribution operation circuit 62 having four RACs. Third one-dimensional DCT
The circuit 53 includes two-stage butterfly operation circuits 63 and 64,
A distribution operation circuit 65 having four RACs at the subsequent stage is incorporated. Note that the second one-dimensional DCT circuit 52
It has the same internal configuration as the first one-dimensional DCT circuit 51.

FIG. 13 is an explanatory diagram of a discrete cosine matrix when another butterfly operation is performed after the butterfly operation 22 in FIG. According to FIG. 13, eight elements Ai
The partial vector composed of four elements Ai (i = 0, 1, 2, 3) of the intermediate vector composed of (i = 0, 1,..., 7) Is converted into a partial vector composed of the elements Pi (i = 0, 1, 2, 3). Then, an 8 × 8 discrete cosine matrix 72
And the eight elements P0, P1, P2, P3, A4, A5
By multiplication with the intermediate vector composed of A6 and A7,
Eight elements Yi constituting a part of the one-dimensional DCT result are obtained. This multiplication is executed by the distribution operation circuits 62 and 65 without using a multiplier. Moreover, since 40 elements in the discrete cosine matrix 72 in FIG. 13 are 0, FIG.
4 and the amount of calculation is reduced as compared with the case of FIG.

According to FIGS. 4 and 13, the first in FIG.
The one-dimensional DCT circuit 51 has four elements A4, A5, A
6, the subtraction of four of the butterfly operation formulas 22 for obtaining A7, and the four vector inner product operations for obtaining the four elements Y1, Y3, Y5, and Y7 are executed. That is, as shown in FIG. 12, the first one-dimensional DCT circuit 51 includes a one-stage butterfly operation circuit 61 and a four-stage butterfly operation circuit
And a distribution operation circuit 62 having a plurality of RACs. Each RAC includes a ROM storing, in the form of a look-up table, a partial sum of vector inner products based on four rows of four non-zero elements in the right half of the discrete cosine matrix 72, and a bit slice word from the ROM. And an accumulator for obtaining a vector inner product corresponding to a partial vector composed of four elements A4, A5, A6, and A7 by digit-aligning and adding a partial sum in 2-bit units sequentially indexed using .

On the other hand, a third one-dimensional DCT circuit 53 shown in FIG. 11 adds four of the butterfly operation expressions 22 for obtaining four elements A0, A1, A2, and A3, and A second butterfly operation formula 71 for obtaining elements P0, P1, P2, and P3, and four elements Y0, Y2, Y4,
And a four vector inner product operation for obtaining Y6. That is, as shown in FIG. 12, the third one-dimensional DCT circuit 53 includes two-stage butterfly operation circuits 63 and 64.
And a distribution operation circuit 65 having four RACs at the subsequent stage
And built-in. Each RAC consists of 4 non-zero elements, each of the left half of the discrete cosine matrix 72.
A ROM storing a partial sum of a vector inner product based on a row in the form of a look-up table, and a 4-bit unit partial index sequentially indexed from the ROM using a bit slice word as an address by digit-aligning and adding four elements P0, P
And an accumulator for obtaining a vector inner product corresponding to a partial vector consisting of P1, P2, and P3.

Each ROM of the first one-dimensional DCT circuit 51 indexes a 2-bit partial sum, and each ROM of the third one-dimensional DCT circuit 53 indexes a 4-bit partial sum. Therefore, the third one-dimensional DCT circuit 53
Means that the first one-dimensional DCT circuit 51 has four elements Y1, Y
The other four elements Y0, Y2, Y4, and Y6 can be obtained in half the time required to obtain 3, Y5, and Y7. Then, the eight elements Yi (i = 0, i) obtained by the first and third one-dimensional DCT circuits 51 and 53 are obtained.
,..., 7) are stored in the transposition memory 54 as row vectors. When the storage of the eight row vectors in the transposition memory 54 is completed, the reading of the column vectors from the transposition memory 54 starts, and the read column vectors are stored in the second and third one-dimensional DCT circuits 52 and 53. Are provided as eight elements Uj (j = 0, 1,..., 7) constituting a transposed vector. These eight elements Uj are converted into first and third ones by the second and third one-dimensional DCT circuits 52 and 53.
In a manner similar to the case of the dimensional DCT circuits 51 and 53, they are converted into eight elements Vj. Second one-dimensional DCT circuit 52
As in the case of the first one-dimensional DCT circuit 51, a one-stage butterfly operation circuit and a subsequent-stage distribution operation circuit having four RACs are incorporated. And the second one
A partial sum in 2-bit units is indexed from each ROM of the dimensional DCT circuit 52, and a partial sum in 4-bit units is indexed from each ROM of the third one-dimensional DCT circuit 53. Therefore, the third one-dimensional DCT circuit 53 generates the second one-dimensional DCT.
The time required for the T circuit 52 to determine the four elements V1, V3, V5, and V7 is half the time required for the other four elements V1,
0, V2, V4, and V6 can be obtained. That is,
The third one-dimensional DCT circuit 53 can perform a time sharing operation on the first and second one-dimensional DCT circuits 51 and 52.

FIG. 14 shows another configuration example of the two-dimensional IDCT apparatus according to the present invention. Two-dimensional IDCT of FIG.
The apparatus comprises first, second and third one-dimensional IDCT circuits 81, 8 for performing one-dimensional IDCT of four points each.
2, 83, an 8 × 8 word transposition memory 84, a multiplexer 85 for switching the input of the third one-dimensional IDCT circuit 83, and a control for receiving the start pulse and the clock to control the operation of each section. And a control circuit 86. First and third one-dimensional IDCT circuits 8
1, 83 are eight elements Vi constituting an input vector.
(I = 0, 1,..., 7) is a circuit configured to obtain eight elements Ui forming a part of the first-dimensional IDCT result. These elements Ui are stored in the transposition memory 84 as row vectors. When the storage of the eight row vectors in the transposition memory 84 is completed, the reading of the column vectors from the transposition memory 84 starts, and the read column vectors (transposition vectors) are stored in the second and third 1s. The dimensional IDCT circuits 82 and 83 are supplied as eight elements Yj (j = 0, 1,..., 7) constituting the input vector. Second and third one-dimensional IDCT circuits 82 and 83
Is a two-dimensional IDCT from the supplied eight elements Yj.
Eight elements Xj constituting a part of the result are obtained. These elements Xj are output from the two-dimensional IDCT apparatus in FIG. 14 as eight elements indicating column vectors of the two-dimensional IDCT result. The entire two-dimensional IDCT result is composed of eight column vectors. Note that the handling of the row vector and the column vector may be reversed.

As shown in FIG. 14, the first one-dimensional ID
The CT circuit 81 is a distribution operation circuit 9 having four RACs.
1 and a one-stage butterfly operation circuit 92 arranged at the subsequent stage. Second one-dimensional IDCT circuit 82
Is composed of a distribution operation circuit 93 having four RACs, and a one-stage butterfly operation circuit 94 arranged at the subsequent stage. The third one-dimensional IDCT circuit 83 includes four RAs
C and a two-stage butterfly operation circuit 96, 92 (or 96, 9)
4). The first and third one-dimensional IDCT circuits 81 and 83 share a butterfly operation circuit 92, and the second and third one-dimensional IDCT circuits 82 and 83 share a butterfly operation circuit 94.

FIG. 15 is an explanatory diagram of an inverse discrete cosine matrix when another butterfly operation is executed before the butterfly operation 43 in FIG. According to FIG. 15, an 8 × 8 inverse discrete cosine matrix 101 and eight elements Vi (i = 0,
, 7), the eight elements Q0, Q1, Q2, Q3, B4, B5
An intermediate vector composed of B6 and B7 is obtained. This multiplication is performed by the distribution operation circuits 91 and 95 without using a multiplier. A partial vector composed of four elements Qi (i = 0, 1, 2, 3) in the obtained intermediate vector is converted into four elements Bi (i = 0, 1, 2,
3) is converted into a partial vector. An intermediate vector composed of eight elements Bi (i = 0, 1,..., 7) is converted into a one-dimensional IDCT composed of eight elements Ui by a butterfly computation expression 43 in a butterfly computation circuit 92. It is converted to the desired vector that forms part of the result. Here, since 40 elements in the inverse discrete cosine matrix 101 in FIG. 15 are 0, the amount of calculation is reduced as compared with the case of FIGS. 8 and 9.

FIG. 16 shows the first and third IDCT circuits 8.
1 and 83 are shown. According to FIGS. 9 and 15, the first one-dimensional IDCT circuit 81 has four elements B
4, B5, B6, and B7 are calculated, and a four-vector inner product operation and a butterfly operation expression 43 are executed. That is, the first one-dimensional IDCT circuit 81 includes a distribution operation circuit 91 having four RACs, and a one-stage butterfly operation circuit 92 disposed at a subsequent stage. on the other hand,
The third one-dimensional IDCT circuit 83 has four elements Q0, Q
, Q2, and Q3, four vector inner product operations, a second butterfly operation expression 102 for obtaining four elements B0, B1, B2, and B3, and a butterfly operation expression 4
3). That is, the third one-dimensional IDCT circuit 8
Reference numeral 3 denotes a distribution operation circuit 95 having four RACs, and two-stage butterfly operation circuits 96 and 92 arranged at the subsequent stage.
It is composed of The first and third one-dimensional IDCT circuits 81 and 83 share a butterfly operation circuit 92.

Each ROM of the first one-dimensional IDCT circuit 81
From the two-bit unit partial sum of the third one-dimensional IDCT
From each ROM of the circuit 83, a partial sum in 4-bit units is respectively indexed. Therefore, the third one-dimensional IDCT circuit 83 takes half the time required for the first one-dimensional IDCT circuit 81 to obtain the four elements B4, B5, B6, and B7, and uses the other four elements. B0, B1, B2, and B3 can be obtained. And the first and third one-dimensional IDs
Eight elements Ui obtained by CT circuits 81 and 83
(I = 0, 1,..., 7) are stored in the transposition memory 84 as row vectors. When the storage of the eight row vectors in the transposition memory 84 is completed, the reading of the column vectors from the transposition memory 84 starts, and the read column vectors are stored in the second and third one-dimensional IDCT circuits 82 and 83. To the eight elements Yj (j = 0, 1,
, 7). These eight elements Yj are
By the second and third one-dimensional IDCT circuits 82 and 83,
As in the case of the first and third one-dimensional IDCT circuits 81 and 83, they are converted into eight elements Xj. The second one-dimensional IDCT circuit 82 includes a first one-dimensional IDCT circuit 81.
Similarly, a distribution operation circuit 93 having four RACs,
It is composed of a one-stage butterfly operation circuit 94 arranged at the subsequent stage. In addition, a partial sum in 2-bit units is indexed from each ROM of the second one-dimensional IDCT circuit 82, and a partial sum in 4-bit units is indexed from each ROM of the third one-dimensional IDCT circuit 83. Therefore, the third one
The two-dimensional IDCT circuit 83 includes a second one-dimensional IDCT circuit 8.
2 is half the time required to obtain the four elements X4, X5, X6, and X7, and the other four elements X0, X1,
X2 and X3 can be obtained. That is, the third one-dimensional IDCT circuit 83 can perform a time sharing operation with respect to the first and second one-dimensional IDCT circuits 81 and 82.

The above example is an 8-point DCT.
And IDCT, the application range of the present invention is not limited by the number of conversion points. That is, the invention described with reference to FIGS. 11 to 16 can be widely applied to an N-point DCT device and an IDCT device. Further, a random logic circuit having a look-up table function may be employed instead of the ROM in each RAC.

[0034]

As described above, according to the present invention, in the case of orthogonal transformation, the partial sum of the vector inner product based on a constant matrix obtained by multiplying each element of the orthogonal transformation matrix by a frequency-dependent weight. And, in the case of the inverse orthogonal transform, a partial sum of a vector inner product based on a constant matrix obtained by dividing each element of the inverse orthogonal transform matrix by a frequency-dependent weight, and use the stored content. As a result, the weighted transform is realized, so that a weighted orthogonal transform device and a weighted inverse orthogonal transform device that do not require any multiplier or divider can be obtained.

Further, according to the present invention, the first-dimensional N-point DCT is executed by half by the first and third circuits, and the second-dimensional N-point DCT is reduced by half by the second and third circuits. , And a two-dimensional D that handles an input data matrix consisting of N × N elements
The number of RACs in the CT apparatus is reduced, and the two-dimensional DC
The circuit scale and power consumption of the T device are reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a two-dimensional DCT device according to the present invention.

FIG. 2 is a block diagram showing an example of an internal configuration of a one-dimensional DCT circuit in FIG.

FIG. 3 is an explanatory diagram of a basic discrete cosine matrix.

FIG. 4 is an explanatory diagram of a discrete cosine matrix when a butterfly operation is employed.

FIG. 5 is an explanatory diagram of a weighted constant matrix used in the one-dimensional DCT circuit in FIG. 1;

FIG. 6 is a block diagram illustrating a configuration example of a two-dimensional IDCT apparatus according to the present invention.

FIG. 7 is a block diagram showing an example of an internal configuration of a one-dimensional IDCT circuit in FIG. 6;

FIG. 8 is an explanatory diagram of a basic inverse discrete cosine matrix.

FIG. 9 is an explanatory diagram of an inverse discrete cosine matrix when a butterfly operation is employed.

FIG. 10 is an explanatory diagram of a weighted constant matrix used in the one-dimensional IDCT circuit in FIG. 6;

FIG. 11 is a block diagram showing another configuration example of the two-dimensional DCT device according to the present invention.

FIG. 12 is a block diagram showing an internal configuration of each of two one-dimensional DCT circuits in FIG. 11;

FIG. 13 is an explanatory diagram of a discrete cosine matrix when a two-stage butterfly operation is employed.

FIG. 14 is a block diagram showing another configuration example of the two-dimensional IDCT apparatus according to the present invention.

FIG. 15 is an explanatory diagram of an inverse discrete cosine matrix when a two-stage butterfly operation is employed.

16 is a diagram illustrating an operation of each of two one-dimensional IDCT circuits in FIG. 14;

[Explanation of symbols]

11, 13 One-dimensional DCT circuit 12 Transpose memory 14 Butterfly operation circuit 15 Distribution operation circuit 21 Basic discrete cosine matrix 22 Butterfly operation expression 23 Discrete cosine matrix when butterfly operation is adopted 24 Weighted constant matrix for DCT 31 , 33 One-dimensional IDCT circuit 32 Transpose memory 34 Distribution operation circuit 35 Butterfly operation circuit 41 Basic inverse discrete cosine matrix 42 Inverse discrete cosine matrix when butterfly operation is adopted 43 Butterfly operation expression 44 Weighted constant matrix for IDCT 51, 52, 53 One-dimensional DCT circuit 54 Transpose memory 55 Multiplexer 56 Control circuit 61, 63, 64 Butterfly operation circuit 62, 65 Distribution operation circuit 71 Butterfly operation expression 72 Discrete cosine row when two-stage butterfly operation is adopted 81, 82, 83 One-dimensional IDCT circuit 84 Transpose memory 85 Multiplexer 86 Control circuit 91, 93, 95 Distribution operation circuit 92, 94, 96 Butterfly operation circuit 101 Inverse discrete cosine matrix 102 when two-stage butterfly operation is adopted 102 Butterfly Arithmetic expression

Claims (12)

[Claims] 1. A partial sum of a vector inner product based on a constant matrix obtained by multiplying each element of an orthogonal transformation matrix by a frequency-dependent weight is stored, and weighted orthogonality is calculated using the stored contents. An orthogonal transformation device characterized in that a transformation result is obtained. 2. A partial sum of a vector inner product based on a constant matrix obtained by multiplying each element of the orthogonal transformation matrix by a frequency-dependent weight, and weighting is performed using the stored contents. A two-dimensional orthogonal transform apparatus comprising: two one-dimensional orthogonal transform circuits configured to obtain an orthogonal transform result; and a transposition memory interposed between the two one-dimensional orthogonal transform circuits. . 3. The two-dimensional orthogonal transformation device according to claim 2, wherein each of the two one-dimensional orthogonal transformation circuits includes a butterfly operation circuit and a distribution operation circuit.
Dimensional orthogonal transformation device. 4. A partial sum of a vector inner product based on a constant matrix obtained by dividing each element of an inverse orthogonal transformation matrix by a frequency-dependent weight is stored, and weighting is released using the stored contents. An inverse orthogonal transform apparatus, wherein a result of the inverse orthogonal transform is obtained. 5. A partial sum of a vector inner product based on a constant matrix obtained by dividing each element of the inverse orthogonal transform matrix by a frequency-dependent weight, and weighting is performed using each of the stored contents. Two one-dimensional inverse orthogonal transform circuits configured to obtain the canceled inverse orthogonal transform result; and a transposition memory interposed between the two one-dimensional inverse orthogonal transform circuits. Two-dimensional inverse orthogonal transform device. 6. The two-dimensional inverse orthogonal transform apparatus according to claim 5, wherein each of the two one-dimensional inverse orthogonal transform circuits includes a distribution operation circuit and a butterfly operation circuit. Dimensional inverse orthogonal transform device. 7. An apparatus for performing a two-dimensional discrete cosine transform of an input data matrix composed of N × N elements, comprising: N / 2-point one-dimensional discrete elements related to N input vectors each composed of N elements. A first circuit for generating half of each of the N first N-point transform results by sequentially performing a cosine transform; and N / 2-points of N transposed vectors each consisting of N elements. A second circuit for generating one half of each of the N second N-point transform results by sequentially performing a one-dimensional discrete cosine transform; and another N / 2 point associated with the N input vectors. Of 1
By sequentially performing a dimensional discrete cosine transform, the N
Generating the other half of each of the first N-point transform results and sequentially performing another N / 2-point one-dimensional discrete cosine transform on the N transposed vectors. A third circuit for generating the other half of each of the second N-point conversion results; and storing N first N-point conversion results generated by the first and third circuits; And a transposition memory for supplying the N transposed vectors to the second and third circuits, wherein the N second N-point conversion results generated by the second and third circuits are 2 of the input data matrix
A discrete cosine transform device output as a result of a dimensional discrete cosine transform. 8. The discrete cosine transform apparatus according to claim 7, wherein the first and second circuits each include a one-stage butterfly operation circuit, and the third circuit includes a two-stage butterfly operation circuit. A discrete cosine transform device characterized by the above. 9. The discrete cosine transform apparatus according to claim 7, wherein the first, second, and third circuits each include N / 2 lookup tables, and each of the first and second circuits A discrete cosine transform apparatus characterized in that a partial sum in 2-bit units is indexed from a look-up table, and a partial sum in 4-bit units is indexed from each look-up table of the third circuit. 10. An apparatus for performing a two-dimensional inverse discrete cosine transform of an input data matrix composed of N × N elements, wherein one-dimensional N / 2 points relating to N input vectors each composed of N elements. A first circuit for generating each half of the N first N-point transform results by sequentially performing an inverse discrete cosine transform; and N / 2 associated with the N transposed vectors each having N elements. A second circuit for generating half of each of the N second N-point transform results by sequentially performing a one-dimensional inverse discrete cosine transform of the points, and another N associated with the N input vectors. / 1 of 2 points
The other half of each of the N first N-point transform results is generated by sequentially performing a dimensional inverse discrete cosine transform, and the other N / 2-point one-dimensional ones associated with the N transposed vectors. A third circuit for generating the other half of each of the N second N-point transform results by sequentially performing an inverse discrete cosine transform; and a third circuit generated by the first and third circuits. A transposition memory for storing N first N-point transformation results and for supplying the N transposition vectors to the second and third circuits, wherein the second and third circuits The generated N second N-point conversion results are the 2nd of the input data matrix.
An inverse discrete cosine transform device, which is output as a result of a dimensional inverse discrete cosine transform. 11. The inverse discrete cosine transform device according to claim 10, wherein the first and second circuits each include a one-stage butterfly operation circuit, and the third circuit includes a two-stage butterfly operation circuit. An inverse discrete cosine transform device, characterized in that: 12. The inverse discrete cosine transform apparatus according to claim 10, wherein each of the first, second, and third circuits includes N / 2 look-up tables. An inverse discrete cosine transform apparatus characterized in that a partial sum in 2-bit units is indexed from each look-up table, and a partial sum in 4-bit units is indexed from each look-up table of the third circuit.