JPH07200290A - Address generation circuit extending address - Google Patents

Abstract

PURPOSE:To provide an address generation circuit which can extend bit width that can be address-designated and which can cope with a large system. CONSTITUTION:A control memory element 4 inputs address output 18 and outputs an address control signal 15 and a clock control signal 17, which are arbitrarily set, in accordance with address output 18. The address generation circuit 3 inputs a clock 11 and outputs an address 12 corresponding to the address control signal 15 synchronizing with the clock 11. A clock generation circuit 6 outputs a clock signal 16 synchronizing with the clock 11 with the clock control signal 17 as the first input. A counting unit 1 counts the clock signal 16 as input and outputs an address 13. An adder 5 inputs the address 12 and the address 13, adds them and outputs it as the address 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address generation circuit for expanding generated addresses.

[0002]

2. Description of the Related Art The structure of an address generating circuit according to the prior art is shown in FIG. 3 in FIG. 3 is an address generator, and 4 is a control memory element. In FIG. 3, the address generator 3
Receives the address generation clock 11 and outputs an address output 18 in synchronization with the clock 11 according to the address control signal 15 output from the control memory element 4.

[0003]

In the configuration of FIG. 3, the bit width of the address output 18 generated by the address generator 3 is determined in advance according to the number of address bits of the memory or the like to be addressed. For example, when addressing a 256 W memory, the bit width generated by the address generator 3 is 256 = 2 ⁸ , which is 8 bits, 64 bits.
When addressing a KW (65536W) memory, 65536 = 2 ¹⁶ , which is 16 bits. As described above, in the conventional address generation circuit, the address area to be generated is determined in advance in accordance with the memory to be addressed and the like, and programs and data are stored and accessed in this area.

On the other hand, in recent years, software has tended to be bloated as microprocessors have become faster and more sophisticated. Therefore, to operate the software smoothly, increase the capacity of the internal storage device (memory) of the computer,
It is necessary to increase the memory space.

However, in the conventional address generation circuit, even if the memory area is increased, it is not possible to specify an address larger than the bit width generated by the address generator 3, and it is not possible to specify the increased memory area. Therefore, there are problems that the expandability of the system is significantly limited, the amount of data increases, and the system that requires a large capacity memory space cannot operate.

An object of the present invention is to provide an address generation circuit which can expand the bit width which can be addressed in the address generation circuit and can be applied to a large system.

[0007]

In order to achieve this object, the present invention uses an address output 18 as an input and arbitrarily sets an address control signal 15 and a clock control signal 1.
7, a control memory element 4 which outputs 7 in response to an address output 18, an address generator 3 which inputs a clock 11 and outputs an address 12 corresponding to an address control signal 15 in synchronization with the clock 11, and a clock control. The signal 17 is used as the first input, and the clock signal 1 is synchronized with the clock 11.
Clock generation circuit 6 for outputting 6 and clock signal 16
Is provided as an input, and a counter 1 that outputs an address 13 and an adder 5 that receives the addresses 12 and 13 as inputs and adds and outputs as an address 18 are generated, and the address 13 is generated by the address generator 3. Address 12
Add to.

[0008]

The structure of the address generator according to the present invention is shown in FIG. In FIG. 1, 1 is a counter, 2 is a storage element, 3 is an address generator, 4 is a control memory element, 5 is an adder, 6
Is a clock generation circuit. The configuration of FIG. 1 is obtained by adding a counter 1, a storage element 2, an adder 5, and a clock generation circuit 6 to the configuration of FIG. The storage element 2 gives an offset to the address output 18, and may be omitted if it is not necessary to give an offset.

In FIG. 1, the control memory element 4 receives an address output 18 as an input, outputs an address control signal 15, and outputs a clock control signal 17. The address generator 3 receives the address control signal 15 of the control memory element 4.
Address control signal 1 in synchronization with clock 11.
The address 12 corresponding to 5 is output.

The clock generation circuit 6 receives the clock control signal 17 and receives the clock signal 1 in synchronization with the clock 11.
6 is output. The address control signal 15 can be set arbitrarily and is a signal for controlling the address generated next by the address generator 3. The clock control signal 17 can be set to any address, and the clock generation circuit 6 counts up the counter 1. Is a control signal for performing. The counter 1 inputs the clock signal 16 which is the output of the clock generation circuit 6,
The counter 1 is incremented by 1. The storage element 2 is for storing an address value in advance. The adder 5 receives the address 12 of the address generator 3, the address 14 of the storage element 2, and the incremented address 13 of the counter 1 as input, adds them, and outputs an address output 18.

In FIG. 1, when the address 13 of the counter 1 and the address 14 of the storage element 2 are both 0, the address 18 output from the adder 5 is the same as the address 12 output from the address generator 3. is there. However, the address range that can be continuously generated by the clock 11 depends on the address bit width of the address generator 3, that is, the maximum value a of the address output. For example, when the bit width of the address generator 3 is 8 bits, The address range that can be continuously generated is 256 addresses.

If the counter 1 is not provided, the maximum value of the address output 14 of the storage element 2 is set to C, and the address generator 3
The address output 18 of the adder 5 can generate 0 to a when C is 0 and C to (C + a) when C is maximum, that is, 0 ( C +
Addresses can be generated in the range up to a).

The address 14 of the storage element 2 is fixed,
When the address output 14 of the memory circuit 2 is C1, the address output 18 of the adder 5 is from C1 to (C1 + a). That is, when there is no output from the counter 1, the storage element 2
The address output from the adder 5 is an address generated by the address generator 3 with an offset depending on the address value of the address.

Here, the counter 1 is used in order to extend the address range that can be continuously generated. The counter 1 receives the clock signal 16 output by the clock generation circuit 6 according to the clock control signal 17 from the control memory element 4, and increments the counter 1 by 1 to change the address output 13. Next, a transition state diagram of the address range of the address output 18 of FIG. 1 is shown in FIG. The address generator 3 in FIG.
When the address output 12 is generated in the range of up to a and the address written in the storage element 2 is D and the increment of the address output when the counter 1 is incremented by 1 is b1, the clock generation circuit 6 outputs the clock signal 16 Each time is output, the range accessed by the address output 18 of the adder 1 is moved by b1 and continuous addresses of which the address bits generated by the address generator 3 are equal to or larger than the address bits can be generated.

In FIG. 4A, the output address 18 of the adder 5 is generated in the range of D to D + a. This range is referred to as A1 range. That is, when the address generator 3 generates an address in the range of 0 to a, the range of A1 in FIG. 4 is accessed.

The clock control circuit 17 of the control memory device 4 of FIG.
Is generated, the counter 1 is incremented by 1. Since the increment of the output address 18 of the adder 5 when the counter is incremented by 1 is b1, the accessible range as shown in FIG.
The range is from (D + b1) to (D + b1 + a). This range is designated as A2.

When the clock generation circuit 6 outputs the clock signal 16 while accessing the range A2, the counter 1 is also incremented by 1 and the accessible range of the output address 18 is (D + 2 × b1) to (D + 2). Xb1 + a)
It becomes the range of A3 up to. Thus, every time the clock generation circuit 6 outputs the clock signal 16, the access range of the output address 18 changes from A1 → A2 → A3.

Incidentally, for example, the least significant bit of the memory element 2 may correspond to a certain bit of the address generator 3, or the least significant bit of the counter 1 may correspond to a certain bit of the memory element 2. The bit widths of the input addresses 12, 13, and 14 input to the adder 5 do not have to be equal, and the least significant bits need not correspond to each other.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, FIG. 2 shows the structure of an embodiment according to the present invention. In FIG. 2, the adder 5 is divided into 5A and 5B,
The adder 5A outputs the upper address, and the adder 5B outputs the lower address. The address output 13 of the counter 1 and the upper address 20 of the storage element 2 are input to the adder 5A, and the output address 1 of the address generator 3 is input to the adder 5B.
2 and the lower address 14 of the storage element 2 are input. The carry signal 19 is sent from the adder 5B to the adder 5A.
Are connected.

The storage element 2 gives an offset to the address outputs 18A and 18B of the adders 5A and 5B, and is composed of, for example, a flip-flop. In FIG. 2, it is assumed that the address C1 is stored in the storage element 2 as an example. The clock generation circuit 6 receives the control signal 17 from the control memory element 4, and receives the clock 11 and AN.
By outputting D, the clock signal 16 is output, but when the timing of the control signal 17 does not match the clock 11, the delay is delayed by a delay element or the like.

Next, in FIG. 2, the address generator 3 generates addresses 0 to a, the initial value of the address by the storage element 2 is C1, and the count up of the counter 1 increases the access range of the address outputs 18A and 18B. An example of the operation in the case of changing by (a + 1) will be described with reference to the timing chart of FIG. 6A shows the waveform of the clock 11.
6A shows the output address 12 of the address generator 3. The address is shown in FIG.
A0, a1, by the control signal 15 of the control memory element of
It shows a state in which a2 and a3 occur in this order.

FIG. 6C shows the waveform of the control signal 17, which is output at the address a1 in FIG. 6D shows the sum of the output addresses of the counter 1 and the storage element 2. 6E shows the address outputs 18A and 18B. The address a1 is a specific address which is written and set in the control memory element 4 in advance. When this address is input to the control memory element 4, the control signal 17 is output.

In FIG. 6A, when the output address of the address generator 3 is a1, the control memory element 4 of FIG. 2 inputs the control signal 17 of FIG. 6C to the clock generation circuit 6 and the count of FIG. 6 is incremented by 1 and the address C1 output from the adder 5 changes to "C1 + a + 1" in synchronization with the clock of FIG.

In FIG. 6E, the address obtained by adding (a + 1) to the output address of FIG. 6A is output in accordance with the change of the address in FIG. 6D. In this way, the address output 18A-1
8B shifts (a + 1) every time the control signal 17 is output.

Next, the transition of the address outputs 18A and 18B according to the embodiment of FIG. 2 will be described with reference to FIG. Figure 2
Then, the initial value of the sum of the addresses of the counter 1 and the storage element 2 is C
When set to 1, the address outputs 18A and 18B are C1 to (C
Addresses are generated in the range of 1 + a).

Here, the control memory element 4 outputs the control signal 17 when the maximum address a of the address generator 3 is output.
When the specific address a1 is set to a so as to output, the control memory element 4 outputs the control signal 17, and the next clock 11 and the control signal 17 input to the clock generation circuit 6 are ANDed and counted. The unit 1 is incremented by 1, and the address outputs 18A and 18B are changed by (a + 1) to (C
Addresses are output in the range of 1 + a + 1) to (C1 + 2 × (a + 1)).

In this state, when the specific address a1 is generated again and the control memory element 4 outputs the control signal 17, the counter 1 is also incremented by 1 and the address output 18A.
The range of 18B is (C1 + 2 × (a + 1)) to (C1 + 3).
Up to x (a + 1)).

In this way, if the transition due to the addition of the counter 1 is (a + 1) and the specific address a1 is a, the control memory element 4 outputs the control signal 17 when the address generator 3 has the maximum address a. The output is performed, and the maximum address of the address generator 3 is incremented by 1 to generate the minimum address (= 0), and the counter 1 shifts the range by (a + 1).

Therefore, the range A1 and the range A2 in FIG. 5 are continuous without overlapping and the memory map can be divided from the address C1 in units of (a + 1) address. If this is made to correspond as a page, the address 18A ・ 18
Each time B accesses a specific address, the range for accessing the next page moves, such as page 1 to page 2, page 2 to page 3.

The counter 1 is required to have a function of setting the address output 13 to 0. Further, if there is a function of freely setting the initial value, the upper address 20 of the storage element 2 can be deleted by inputting the upper address of the storage element 2 into the counter 1 as the initial value.

[0031]

According to the present invention, an address is generated by inputting a clock control signal from a control memory element to a counter, adding an address output from the counter with an address of an address generator and outputting the result. It is possible to specify the address exceeding the maximum address range generated by the device 3, and to expand the generated address. As a result, the upper limit of the memory that can generate addresses is expanded, so that a part of the software can be loaded into the memory that is built in or added to the computer to make effective use of the memory, and the execution speed of the software can be increased. .

[Brief description of drawings]

FIG. 1 is a configuration diagram of an address generation circuit according to the present invention.

FIG. 2 is a configuration diagram of the embodiment of FIG.

FIG. 3 is a configuration diagram of an address generating circuit according to a conventional technique.

4 is an explanatory diagram of an address generation state by the operation of FIG.

FIG. 5 is an explanatory diagram of an address generation state by the operation of FIG.

FIG. 6 is a timing chart of the operation of FIG.

[Explanation of symbols]

 1 Counter 2 Storage Element 3 Address Generator 4 Control Memory Element 5A / 5B Adder 6 Clock Generation Circuit

Claims (1)

[Claims] 1. An address control signal (15) and a clock control signal (17) which are arbitrarily set with an address output (18) as an input.
Control memory device (4) that outputs the address corresponding to the address output (18) and the clock (11) as input, and the address (12) corresponding to the address control signal (15) is synchronized with the clock (11). Address generator (3) that outputs the clock and the clock control signal (17) as the first input
The clock generation circuit (6) that outputs the clock signal (16) in synchronization with the
It is equipped with a counter (1) that outputs 3) and an adder (5) that inputs the address (12) and address (13) and adds and outputs as address (18). Address generated by generator (3)
An address generation circuit for expanding an address characterized by adding to (12).