JPH02100750A - Controller for microprocessor - Google Patents

Abstract

PURPOSE:To slow down the data read timing of the microprocessor to access a storage device and a peripheral device which are slow in access by slowing down a system clock upon occasion when the microprocessor accesses the storage device and peripheral device. CONSTITUTION:An equipment selecting device 4 decides a device which has a slow access time and outputs an equipment selection signal 8 to a voltage generating device 5 to vary a frequency variable voltage 11, thereby slowing down the system clock 9 outputted from a system clock varying device at need. Consequently, the data read timing of the microprocessor is slowed down to enable access to the storage device and peripheral device which are long in access time.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a bus cycle control device for a microprocessor used in office automation equipment such as word processors and personal computers.

Conventionally, this type of microprocessor control device has been equipped with a storage device, a peripheral device, a system bus cycle control device, a DMA control device, etc., and by controlling the system bus cycle control device, the number of cycles of the system bus can be controlled. By increasing the storage device with slow access time,
It is configured to allow access by peripheral devices, DMA control devices, and the like.

FIG. 3 shows the configuration of a conventional microprocessor control device.

In FIG. 3, 21 is a microprocessor, 22 is a storage device, 23 is a peripheral device, 24 is a DMA control device, 26
is a bus cycle control device. 26 is a system bus created by this microprocessor 21, and the storage device 22, peripheral device 23, DMA control device 24, and bus cycle control device 26 are directly connected to the system bus 2θ. The bus cycle control device 26 is connected to each device 22 to 24.
A signal 27 is outputted to the microprocessor by selectively determining whether one of them has been accessed, thereby increasing the number of bus cycles.

Next, the operation of the above conventional example will be explained.

In FIG. 3, the microprocessor 21 operates in synchronization with a system clock as shown in FIG. When the microprocessor 21 accesses the storage device 22, it outputs a storage device read signal 28 to the storage device 22. The storage device 22 starts operating according to the signal 28,
After the access time tacc has elapsed, the data is output to the system bus.

The microprocessor 21 is connected to the storage device 2 at time D in FIG.
The output data from 2 is read, but a general microprocessor needs to ensure a cent up time Ts from point D. When a storage device with a slow access time tacc is used, it becomes difficult to secure the setup time Ts, so the bus cycle control device 26 determines which device is being accessed and adjusts the bus cycle as necessary. In order to increase the number of bus cycles, the bus cycle control device 26 outputs a signal 27 to the microprocessor 21 at timing E as shown in FIG. 4, thereby increasing the number of bus cycles. As a result, the data reading point of the microprocessor 21 moves to F, and the access time ta
This means that cc has become isometrically faster, and the microprocessor 21 can read the data with a margin.

In this way, even with the conventional microprocessor bus cycle control device described above, by controlling the output 27 by the bus cycle control device, reading from a storage device with a slow access time can be performed.

Problems to be Solved by the Invention However, with the conventional microprocessor bus cycle control device described above, the number of bus cycles increases even if the access time is slightly short, resulting in a significant drop in system processing speed. There was a problem.

The present invention solves these conventional problems,
The object of the present invention is to provide an excellent microprocessor bus cycle control device that enables data to be read from devices with slow access times without increasing bus cycles, and does not slow down system processing speed. .

Means for Solving the Problems In order to solve the above objects, the present invention provides a storage device and a peripheral device connected to a system bus signal of a microprocessor, and a system clock variable device for varying the system clock of the microprocessor. , when the access time of the storage device and peripheral device is slower than the access time required by the microprocessor, the system clock variable device delays the system clock to secure the access time of the storage device and peripheral device. Therefore, according to the present invention, when a microprocessor accesses a storage device and a peripheral device, the system clock variable device delays the system clock as necessary to adjust the data reading timing of the microprocessor. This has the effect of making it possible to access storage devices and peripheral devices with slow access times.

Example FIG. 1 shows the configuration of an embodiment of the present invention.

In FIG. 1, 1 is a microprocessor, and a storage device 2, a peripheral device 3, and a device selection device 4 are connected to a system bus created by the microprocessor 1. The device selection device 4 uses the microprocessor 1 to determine which device has been selected, and notifies the corresponding device by outputting a selection signal. The device that receives the select signal starts operating.

Reference numeral 6 denotes a voltage generator, which changes a frequency variable voltage 11 based on a device selection signal 8. 6 is a system clock variable device, which generates the system clock 9 and at the same time,
A system clock 9 is varied and outputted to the microprocessor 1 using a variable frequency voltage 11 outputted from the voltage generator 5 .

Next, the operation of the above embodiment will be explained.

In the above embodiment, when the microprocessor 1 accesses the storage device 2, the device selection device 4 determines that the storage device has been selected, and selects the storage device from the storage device 2 at the timing shown in FIG. A select signal 10 is output. The storage device 2 starts a read operation by the signal 10. However, in a device with a slow access time tacc, it may not be possible to secure the setup time Ts as it is.

On the other hand, the device selection device 4 has previously set the address of the device for which the access time is insufficient, and outputs the device selection signal 8 to the voltage generator 6 when the access time of the storage device 2 is insufficient. do.

The voltage generator 6 outputs a frequency variable voltage 11 corresponding to the device selection signal 8 to the system clock variable device 6, lowers the system clock 9 as necessary, and outputs it to the microprocessor 1.

That is, while the device selection signal 8 is being output, the system clock 9 has a pulse width of TI (T2=T3=T4) to compensate for the lack of access time to the storage device 2. When the voltage generation device 5 has finished, the output from the device selection signal 8 is canceled and the frequency variable voltage 11 is restored to the old voltage.
The system clock 9, which had been lowered, is returned to its original frequency and the next device access cycle begins.

When it comes time.

TI = T2 = T3 = T4 The relationship is

In this way, according to the above embodiment, the device selection device 4 determines the device with slow access time and outputs the device selection signal 8 to the voltage generator 6, thereby increasing the frequency variable voltage 11.
By changing the system clock 9 and delaying the system clock 9 output from the system clock variable device as necessary, the data read timing of the microprocessor is delayed, and access to storage devices and peripheral devices with slow access times is made possible. It has the advantage of being able to

Further, according to the embodiment described above, access can be made without increasing the number of bus cycles of the microprocessor, so it has the effect of minimizing a decrease in processing speed.

Note that it is clear that the object of the present invention can be achieved even if the means for changing the system clock is not a voltage.

Effects of the Invention As is clear from the above embodiments, the present invention has the following effects.

(1) Since the system clock of the microprocessor is made variable, there is no increase in bus cycles and no reduction in processing speed when accessing devices with slow access times.

(2) Even in a system that combines a high-speed microprocessor and a low-speed storage device, it is possible to construct a system that does not reduce the processing speed of the microprocessor.

(3) By improving the resolution of the voltage applied to the system clock variable device, it is possible to maximize the performance of connected devices regardless of whether they are high speed or low speed, and the overall system performance can be improved.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a microprocessor system device according to an embodiment of the present invention, FIG. 2 is a timing diagram showing access to the storage device of the same device, and FIG. 3 is a conventional microprocessor system device. A schematic block diagram of
FIG. 4 is a timing diagram showing access to a storage device in a conventional device.0 1...microprocessor, 2...storage device, 3...
...Peripheral device, 4...Device selection device, 6...Voltage generator, 6...System clock variable device R17...
System hash, 8... Equipment selection signal, 9... System clock, 1o... Storage device selection signal, 11.
... Frequency variable voltage, 21... Microprocessor,
22...Storage device,...Peripheral device, 24...I)M pre-control device, 26...S cycle control device, 2e...System bus, 27...Bus cycle increase signal, 28 ...Storage device read signal O Fig.

Claims (1)

[Claims] A microprocessor, a storage device and a peripheral device connected to a system bus signal of the microprocessor, a system clock variable device for varying the system clock of the microprocessor, and a device for selecting a device whose system clock should be varied. and a device selection device, and when the access time of the storage device and peripheral device is slower than the access time required by the microprocessor, the device selection device outputs a variable signal corresponding to the system clock to the system clock variable device. A control device for a microprocessor, characterized in that the system clock output from the system clock variable device is varied to ensure access time for the storage device and peripheral devices.