JPH07200106A - Power source control circuit - Google Patents

Abstract

PURPOSE:To suppress the power consumption by employing a circuit constitution which performs supply and stop control over a power source for a peripheral device corresponding to various operation modes of a processor. CONSTITUTION:A decoder 3 once receiving an enable signal 10 from the processor 1 activates a device select signal 12 to the power which of a peripheral device Dev(r)6 and inactivates selects signals 11 to 13 to the power switches 8 of Dev(1)5-Dev(n)7. Consequently, to the Dev(r)6 and the bus driver 4 which is connected thereto electric power is supplied. The enable signal 10 is inactivated at the end of a CPU write cycle and the select signal 12 to the power switch 8 of the Dev(r)6 is inactivated to stop the power supply. Only to the peripheral device that the processor accesses, the electric power is supplied, so unnecessary consumption of the power source is reducible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply control circuit for controlling power supply to peripheral devices under processor control.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram of a power supply control circuit in a conventional example. In the figure, 1 is a processor, 2 is a system bus of the processor, 4 is a driver of the system bus of the processor, 5 to 7 are peripheral devices Dev [1] to Dev [r] to De connected to the system bus of the processor.
v [n] (1 ≦ r ≦ n: n is a positive integer), and 9 is a power supply.

Next, the operation will be described. In FIG. 6, the processor 1 directly connects the command required for device selection to the bus driver 4 via the system bus 2 based on the read / write cycle in order to access the device designated by the instruction from the program. By sending to the peripheral devices 5 to 7, the access operation to the device designated by the program is executed.

During the operation of the processor, the power supply 9 constantly supplies peripheral devices Dev [1] to Dev [r] to irrespective of data access to the peripheral devices of the processor.
The power supply current was continuously supplied to Dev [n].

[0005]

Since the conventional power supply control circuit is constructed as described above, a large amount of power is consumed because the power supply is continuously supplied to the peripheral devices regardless of the various operation modes of the processor. There was a problem that was done.

The present invention has been made to solve the above problems, and wasteful power consumption is achieved by controlling the supply and stop of power supply to peripheral devices corresponding to various operation modes of a processor. An object is to provide a suppressed and efficient power supply control circuit.

[0007]

A power supply control circuit according to the present invention includes a selection signal generating means for generating a selection signal of a peripheral device to be accessed based on command data issued from a processor, and a selection signal generating means for generating the selection signal. It is provided with power switch means for inputting the resulting selection signal and for turning on or off the power supplied from the power supply to the designated peripheral device according to the state of the selection signal. The power supply control circuit according to the present invention includes a selection signal generating means for generating a selection signal for a peripheral device to be accessed based on command data issued from a processor, and an on / off timing signal for supplying power to the peripheral device. A power supply timing generating means for generating a power supply timing generating means, a power supply control circuit means for generating an on / off control signal for supplying power to a designated device by inputting the selection signal and the power supply timing signal for designating a peripheral device, A power supply switch circuit is provided for inputting an output signal of the power supply control circuit means and for turning on or off the power supply supplied from the power supply to the designated peripheral device according to the state of the output signal. . Further, the power supply control circuit according to the present invention includes at least one pattern generator generating means for receiving command data issued from the processor and selectively outputting a pattern designating a power supply group for peripheral devices, and the pattern generator generating means. Designated pattern synthesizing circuit means for generating power supply on / off control signals for the designated device group with the output signal as an input, and the output signal of the designated pattern synthesizing circuit means for inputting from the power source according to the state of the output signal. Turn on or off the power supplied to the specified peripheral device
The power switch means for controlling f is provided.

[0008]

Since the power supply control circuit according to the present invention operates so as to control ON / OFF of the power supply switch for supplying power to the peripheral device based on the command data from the processor, the peripheral device targeted by the processor is accessed. Only the power can be supplied. In addition, an arbitrary peripheral device to be accessed is selected by command data from the processor, and independently of this, timing control of power-on / off of the specified peripheral device is performed by an instruction from the processor. Further, the peripheral device can be arbitrarily designated by the combined output result of a plurality of pattern generators.

[0009]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a processor, 2 is a system bus of the processor, 3 is a decoder that decodes an address from the system bus and activates only a peripheral device selection signal being accessed, 4 is a driver of the processor system bus, 5 7 are peripheral devices Dev [1] to Dev [r] connected to the system bus of the processor.
Dev [n] (1 ≦ r ≦ n: n is a positive integer), 8 is a power switch, 9 is a power supply, 10 is an enable signal from the processor, and 11 to 13 are selection signals for supplying power to peripheral devices. .

Next, the operation will be described. Here, a case where the processor selects the peripheral device 6 will be described. First, the processor 1 sends via the system bus 2 and the bus driver 4 the command data necessary for designating the peripheral device to be accessed in the peripheral device groups 5 to 7. Then the decoder 3 is the processor 1
When the enable signal 10 is received, the peripheral device power supply selection signal is activated (turned on) at the start of the CPU write cycle after the processor initialization. That is, in this case, the peripheral device Dev
The peripheral device selection signal 12 for the power switch 8 of [r] 6 is activated, and the peripheral device Dev
Selection signals 11 to 13 for the power switches 8 of the peripheral devices Dev [1] 5 to Dev [n] 7 excluding [r] 6
To the inactive state. As a result, the peripheral device selection signal 12 turns on the power switch 8, so that the peripheral device Dev [r] 6 and this device Dev
Power is supplied to the bus driver 4 connected to [r] 6. On the other hand, the peripheral device selection signals 11 to 13 other than the peripheral device selection signal 12 turn off the power switches 8 of the peripheral devices Dev [1] 5 to Dev [n] 7 other than Dev [r] 6. Power supply to the peripheral devices Dev [1] 5 to Dev [n] 7 excluding r] 6 and the bus drivers connected to these devices is stopped. In this way the device De
When the access to v [r] 6 is completed, the decoder 3 sets the enable signal 10 of the processor 1 to the non-active (off) state at the end of the CPU write cycle according to the instruction of the processor 1, and the device Dev [ r] 6 sets the peripheral device selection signal 12 to the power switch 8 to the non-active (off) state. As a result, the peripheral device selection signal 12 turns off the power switch 8 and the peripheral devices Dev [r] 6 and D
The power supply to the bus driver 4 connected to ev [r] 6 is stopped. The enable signal 10 is read by the CPU /
In the write cycle, the signal is output as a CPU access signal synchronized with the output of the address / data signal on the system bus 2. The decoder 3 address-decodes the address output signal on the system bus 2 during the period when the enable signal is in the active (on) state, and brings the selection signals (11 to 13) of the corresponding peripheral device into the active (on) state.

Embodiment 2. In the above embodiment, the power supply control circuit using the dedicated decoder by the input of the system bus 2 of the processor 1 is shown to generate the peripheral device selection signal. However, as shown in FIG. Selector circuit 15 for directly inputting selection signal
A similar operation can be expected by a power supply control circuit equipped with. Here, the selector circuit 15 has a port output signal 14 that corresponds to the selection signals (11 to 13) of each peripheral device output from the processor 1 on a one-to-one basis and an enable that determines enable / disable of each port output signal 14. The result of the logical product using the signal 10 as a gate input is finally output as a selection signal (11 to 13) for each peripheral device.

Embodiment 3. A third embodiment of the present invention will be described with reference to FIG. In FIG. 3, the peripheral device instruction signal 22 from the processor 1 and the processor 1
Is supplied to the peripheral device selection circuit 17 at an arbitrary timing required by the.
That is, the peripheral device instruction signal 22 corresponding to the peripheral devices 5 to 7 is valid while the enable signal 10 is in the active (on) state, and the peripheral device selection circuit 17 causes the peripheral device 5 to 5 of the processor.
The power supply instruction signal 20 for selecting only the peripheral device instructed by the processor 1 is output regardless of the access to 7. On the other hand, from processor 1 to any CPU
With the circuit configuration in which the port output signal 16 output at timing is supplied to the initial reset circuit 18, the initial reset circuit is in an active (on) / non-active (off) state regardless of the enable signal 10. A set / reset signal 21 of the selection device for determining Next, the power supply instruction signal 20 and the selection device set / reset signal 21 are supplied to the selector circuit 19, where the power supply selection signals 11 to 13 for final ON / OFF control of the designated device are generated. To be done. With this, when the access procedure to the peripheral device is predetermined, the power supply to the peripheral device can be freely turned on / off at an arbitrary request timing of the processor 1. For example, when the processor 1 controls the power supply to the device Dev [r] 6, the device Dev is activated by the peripheral device instruction signal 22 while the enable signal 10 is in the active (on) state.
A power supply instruction signal 20 that activates [r] 6 is input to the selector circuit 19. On the other hand, at the CPU timing based on a sequence determined in advance by the processor 1, the port output signal 16 is input to the initial circuit 18 and the selection device set / reset signal 21 that appropriately takes an active (on) / non-active (off) state is selected. It is input to 19. As a result, the selector circuit 19 responds to the peripheral device designated by the power supply instruction signal 20 while the selection device set / reset signal 21 is in the non-active (off) state.
The power switch 8 of the peripheral device Dev [r] 6 is turned on by setting the selection signal 12 of v [r] 6 to the active (on) state, and the power is supplied to the Dev [r] 6.

Embodiment 4. A fourth embodiment of the invention will be described with reference to FIG. When the ON / OFF setting patterns of the power supply of the peripheral device can be set in advance, as shown in FIG. 4, by adding dedicated pattern generators 24 and 25, the pattern instruction signal 23 from the processor 1 By generating a constant power supply pattern selection signal for peripheral devices with a minimum number of interface control signals from the processor and generating power supply selection signals 11-13 for peripheral devices via the pattern selection circuit 26 Power supply control can be realized by the circuit configuration. For example, when the pattern generator 24 outputs a pattern signal so as to supply power to the peripheral device Dev [r] 6, first, the processor 1 causes the pattern instruction signal 23 to activate the pattern generator 24. Is output. Upon receiving the pattern instruction signal 23, the pattern generator 24 outputs a pattern signal for generating a power supply group including the peripheral device Dev [r] 6. Next, the pattern selection circuit 26 determines the result of the logical operation between the pattern signal output from the pattern generator 24 and the pattern signal of the other pattern generator 25 as the final power supply peripheral device selection signal (11 to 13).
Output as. As a result, peripheral device selection signal 1
Only 2 becomes the active (on) state, and power is supplied only to the peripheral device Dev “r” 6.

Example 5. A fifth embodiment of the present invention will be described based on FIG. As shown in FIG. 5, the same operation can be expected in the power supply control circuit including the pattern generator 27 having the command register corresponding to the combination pattern of the power supply selection signals 11 to 13 for the peripheral devices. For example, the pattern generator 27 may add the peripheral device Dev to the system bus 2 of the processor 1.
If an output command that activates only [r] 6 is output to the pattern generator 27 via the system bus 2, the pattern generator 27 receives this output command and activates only the peripheral device selection signal 12 ( ON) state, resulting in peripheral device D
Only the power supply selection signal 12 of ev [r] 6 becomes active (on), and power is supplied only to the peripheral device Dev [r] 6. On the other hand, if the processor 1 outputs an output command to put only the peripheral device Dev [r] 6 into the non-active (off) state to the pattern generator 27 via the system bus 2, the pattern generator 27 receives this output command. Only the peripheral device selection signal 12 is set to the non-active (off) state, and as a result, the power supply selection signal 1 of the peripheral device Dev [r] 6
2 becomes a non-active (off) state, and the power supply to the peripheral device Dev [r] 6 is stopped.

[0015]

As described above, according to the present invention, the processor supplies power only to peripheral devices to be accessed, and to other peripheral devices not to be accessed and devices for which access operation has been completed. Since the power supply control circuit is configured to stop the power supply, the wasteful consumption of the power supply can be reduced. Further, according to the present invention, only the peripheral device to be accessed is kept in the selected state at all times, and the active / non-active timing control for the peripheral device is performed by the command data independent of the peripheral device. There is an effect that power on / off control can be realized. Further, according to the present invention, the target peripheral device is finally selected by combining a plurality of pattern generator circuits, so that a plurality of peripheral device groups to be turned on can be selected according to the control contents of the program. It is possible to classify them into arbitrary groups and divide them into hierarchical structures.

[Brief description of drawings]

FIG. 1 is a block diagram of a processor peripheral power supply control circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a processor peripheral power supply control circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a processor peripheral power supply control circuit according to a third embodiment of the present invention.

FIG. 4 is a block diagram of a processor peripheral power supply control circuit according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram of a processor peripheral power supply control circuit according to a fifth embodiment of the present invention.

FIG. 6 is a block diagram of a conventional processor peripheral power supply control circuit.

[Explanation of symbols]

 1 Processor 2 System Bus 3 Decoder Circuit 4 Bus Driver 5-7 Peripheral Device Group 8 Power Switch 9 Power Supply 9 Processor Enable Signal 11-13 Peripheral Device Power Supply Selection Signal 14 Processor Port Output Signal 15 Selector Circuit 16 Processor Port Output signal 17 Peripheral device selection circuit 18 Initial reset circuit 19 Selector circuit 20 Peripheral device power supply selection signal 21 Selection device set / reset signal 22 Peripheral device instruction signal 23 Pattern instruction signal 24, 25, 27 Pattern generator 26 Pattern selection circuit

Claims (3)

[Claims] 1. A power supply control circuit for supplying power to a peripheral device connected to a processor, wherein the power supply control circuit generates a selection signal of a peripheral device to be accessed based on command data issued from the processor. A signal generation means and a selection signal obtained as a result of the selection signal generation are input,
A power supply control circuit, comprising: a power supply switch means for controlling on / off of power supplied from the power supply to the designated peripheral device in accordance with the state of the selection signal. 2. A power supply control circuit for supplying power to a peripheral device connected to a processor, wherein the power supply control circuit generates a selection signal for a peripheral device to be accessed based on command data issued from the processor. A signal generation means, a power supply timing generation means for generating an on / off timing signal for supplying power to the peripheral device, and the selection signal for designating the peripheral device and the power supply timing signal as inputs to the designated device. Power supply control circuit means for generating an on / off control signal for power supply, and power supplied from the supply power supply to the designated peripheral device in response to the state of the output control signal, the power supply control circuit means being an input. And a power switch means for controlling ON or OFF of the power supply. 3. A power supply control circuit for supplying power to a peripheral device connected to a processor, wherein the power supply control circuit receives a command data issued from the processor and specifies a pattern for designating a power supply group for the peripheral device. At least one pattern generator generating means for selectively outputting, designated pattern synthesizing circuit means for generating power supply on / off control signals for the designated device group by using the output signal of the pattern generator generating means as input, and the designated pattern A power supply switch means for inputting an output control signal of the synthesizing circuit means and for turning on or off the power supplied from the power supply to the designated peripheral device in accordance with the state of the output control signal. Characteristic power supply control circuit.