JPH0719474B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly to improvement of a sense amplifier thereof.

The sense amplifier that amplifies the signal of the common data line pair CDL, ▲ ▼ in the static random access memory (RAM) and transmits it to the data output buffer circuit is
An asymmetric differential amplifier circuit composed of a differential MISFET and a current mirror circuit (active load) as its load has been used. Therefore, as an output signal, the differential MISFET
This sense amplifier can be relatively sensitive because a difference in drain current is obtained. However, since the amplification factor is as small as 5, the common data line CDL,
If the input level difference from ▲ ▼ does not become large,
The specified output voltage cannot be obtained.

Further, this sense amplifier has a drawback that an offset voltage generated due to variations in the characteristics of elements forming the sense amplifier is directly transmitted to the next stage. Further, since this sense amplifier is an asymmetric type that receives a pair of input signal level differences as input signals and forms an output signal having a potential corresponding to the input signal level difference with respect to the ground potential of the circuit, the next stage Influenced by the logic threshold voltage of, the noise margin becomes smaller. From the above, when the above sense amplifier is used, the level difference between the common data line pair CDL, ▲ ▼ is about 0.
It needs to be increased to 5 volts, which is a major obstacle in achieving high-speed operation. On the other hand, common data line pair CD
Each of L and ▲ ▼ has a larger parasitic capacitance as the memory has a larger capacity, and limits the changing speed of the data read from the selected memory cell.

An object of the present invention is to provide a semiconductor memory device which has a high speed operation.

Another object of the present invention is to provide a semiconductor memory device equipped with a high-sensitivity sense amplifier in which variations in element characteristics and the influence of noise are reduced.

According to the present invention, the first and second asymmetric differential amplifier circuits in parallel form which receive the signals of the common data line pair CDL, and form output signals of mutually opposite phases are used as sense amplifiers. The common data line pair is divided into a plurality of common data line pairs, and each of the divided common data line pairs is provided with the above sense amplifier. The outputs of the plurality of sense amplifiers are commonly connected and selectively driven.

Hereinafter, the present invention will be described in detail together with examples.

[Structure and Operation of Static Memory System] The structure of the static memory system will be described with reference to FIG. First, the block diagram surrounded by a dotted line shows a static memory system, and this system is an S-RAM IC ARRAY (hereinafter referred to as S-RAM).
In addition, it is composed of an interface circuit between a central processing unit (hereinafter referred to as CPU, not shown) of the computer and the S-RAM. E is a power supply circuit that represents the backup function in principle. Normally, the power supply E _O is working, but when the power supply E _O is turned off or it fails, the auxiliary power supply E _B works. It is configured to retain the stored contents of the memory chip. Power supply Vcc and Vss are all memory
It is common to ICs.

Next, input / output signals between the static memory system and the CPU will be described. First, the address signals Ao to Ak are signals for selecting the addresses of 2k memory cells in the S-RAM surrounded by the solid line. The address signals Ao to Ai are assigned as common address signals to each memory IC.
The address signals of _{1 + 1 to} Ak are assigned as selection signals for the m-row IC array and used as chip select signals ▲ ▼ common to the ICs in each row. ▲ ▼ is a write enable signal, which is a data read / write command signal in the S-RAM and is supplied to the WE terminals of all the memory ICs. MS is a memory activation signal that starts the memory operation of the S-RAM. D _{1 to} D ₈ are input / output data on the data bus connecting the CPU and the S-RAM.

Next, the static memory system will be described separately for the S-RAM and the interface circuit. First, S-RAM has n
A k-bit integrated circuit (hereinafter referred to as nk, 1 k-bit indicates 2 ¹⁰ = 1024 bits) is arranged in m columns and B rows, and (n × m) words × B bits are arranged. It consists of IC arrays connected in a matrix. In addition, in line B
Data input terminal Din of memory IC in each row of IC array
And the data output terminal Dout are commonly connected.

Next, the interface circuit will be described. The ADR is an address receiver that receives the address signals Ao to Ak sent from the CPU and converts the address signals into timing address signals that match the operation of the S-RAM.

The DCR is a decoder for transmitting a chip selection control signal (hereinafter referred to as CS _{1 to} CSm, m = 2k ^-1 ) for selecting an S-RAM chip.

DBD is a data bus driver in which data input / output between the CPU and S-RAM is switched by a gate control signal GC.
The gate control signal GC is a light enable signal ▲
It is made by the logical combination of ▼ and the memory activation signal MS.

The data output D _{O1 to} D _OB of the IC array is the IC (B
Read output signal from the data output terminal)
Array data inputs D _{I1 to} D _IB are selected column ICs (B
Write data to the data input terminal Din.

Next, the function of the address signal in the static memory system will be described.

The address signals Ao to Ak from the CPU are divided into two systems, that is, the address signals Ao to Ai are used as the address signals of the memory matrix in each chip of the S-RAM, and the address signals Ai _{+1 to} Ak are S. -When seen from the RAM chip, it becomes a chip selection signal indicating whether or not the entire chip is selected.

[16k words x 1 bit S-RAM circuit configuration] Figure 2A shows an S-RAM with a storage capacity of 16k bits and an output of 1 bit.
-Indicates the internal configuration of a RAM integrated circuit (hereinafter referred to as an IC).

A 16k-bit memory cell has four matrices (memory arrays M-ARY1 to M-ARY4) each having a storage capacity of 128 columns (rows) x 32 rows (columns) = 4096 bits (4k bits).
And each matrix is divided into two rows on the left and right sides of the row decoder R-DCR.

Row-related address selection lines (word lines WL1 to WL128, WR1 to WR
128), the row decoder R-DCR outputs 2 ⁸ = 256 different decode output signals obtained based on the address signals A _{0 to} A ₅ and A _{12 to} A ₁₃ .

In this way, the memory M-CEL of each matrix is word line W
One of L1 to WL128 and WR1 to WR128 is connected to one of complementary data line pairs D11, 11 to D132, 132 described later.

The address signals A ₅ and A ₆ are used to select only one of the four memory matrices. Address signals A _{7 to} A ₁₁ are used to select one column in one selected memory matrix.

The memory matrix selection signal GS is the above address signals A ₅ , A ₆
Decode into four combinations based on.

The column decoders C-DCR1 to C-DCR4 provide 2 ⁵ = 32 column selection decode output signals based on the address signals A _{7 to} A ₁₁ , respectively.

When reading, common data line pair CDL, ▲ ▼ are common data line dividing transistors Is divided into four for each memory array, and the common data line pair CDL, ▲ ▼ is commonly connected at the time of writing.

The sense amplifiers SA1, SA2, SA3, SA4 are provided corresponding to the above-mentioned divided common data line pairs CDL, ▲ ▼, respectively.

In this way, the common data line pair CDL, ▲ ▼ is divided and the sense amplifiers SA1, SA2, SA3, SA4 are provided for each purpose.The purpose is to divide the parasitic capacitance of the common data line pair CDL, ▲ ▼ to read the memory cell information. The purpose is to speed up the operation.

The address buffer ADB creates 14 pairs of complementary address signals a ₀ to a ₁₂ from 14 external address signals A _{0 to} A ₁₂ , respectively,
It is sent to the decoder circuit (R-DCR, C-DCR, GS).

Internal control signal generation circuit COM-GE has two external control signals ▲
In response to ▼ (chip select signal) and ▲ ▼ (write enable signal), CS1 (row decoder control signal),
SAC (sense amplifier control signal), we (write control signal), DOC (data output buffer control signal), DIC (data input buffer control signal), etc. are transmitted.

[16k Word × 1 Bit S-RAM Circuit Operation] The circuit operation of the S-RAM IC shown in FIG. 2A will be described with reference to the timing chart of FIG. 2B.

All operations in this IC, that is, address setting operation, read operation, and write operation, are controlled by one external control signal.
Only when the ▼ is low level. At this time, if the other external control signal {circle over ()} is high level, a read operation is performed, and if it is low level, a write operation is performed.

First, the address setting operation and the read operation will be described.

The address setting operation is always performed on the basis of the address signal applied during this period when the external control signal () is at the low level. On the contrary, by setting the external control signal ▲ ▼ to the high level, the address setting operation and the read operation based on the uncertain address signal can be prevented.

When the external control signal () becomes low level, the row decoder R-DCR receives the high level internal control signal CS1 synchronized with this signal and starts its operation. The row decoder (and word driver) R-DCR selects the eight complementary pairs address signal _{a 0 ~ a 5, a 12} ~ a 13 decodes by one word line, for driving the high level.

On the other hand, one of the four memory arrays M-ARY1 to M-ARY is selected by the memory array selection signals m1 to m4, and one selected memory array (for example, M-ARY) is selected.
One complementary data line pair (for example, D11,11) in 1) is selected by the column decoder (for example, C-DCR1).

In this way, one memory cell is selected (address setting)
To be done.

The information of the memory cell selected by the address setting operation is sent to one of the divided common data line pairs and amplified by the sense amplifier (for example, SA1).

In this case, one of the four sense amplifiers SA1, SA2, SA3, SA4 is selected by the memory array selection signals m1 to m4, and only the selected one sense amplifier receives the high level internal control signal SAC. It operates for the period of time.

As described above, the power consumption can be reduced by deactivating three sense amplifiers SA1, SA2, SA3, and SA4 that are not required to be used. The outputs of the three sense amplifiers in the non-operating state are in a high impedance (floating) state.

The output signal of the sense amplifier is amplified by the data output buffer DOB and sent as output data Dout to the outside of the IC.

The above data output buffer DOB is a high level control signal DOC
Operates while receiving

Next, the write operation will be described.

When the external control signal ▲ ▼ becomes low level, the high level control signal we synchronized with it becomes the common data line dividing transistor. And the common data lines CDL, ▲ ▼ are commonly coupled.

On the other hand, the data input buffer DIB receives the input data signal D from the outside of the IC while receiving the low level control signal DIC.
a common data line pair CDL that amplifies in and is commonly connected
Send to ▲ ▼.

The input data signal on the common data line pair CDL, ▲ ▼ is written in the memory cell M-CEL determined by the address setting operation.

[2k Word x 8-bit S-RAM Circuit Configuration] FIG. 3A shows an internal configuration of an S-RAM integrated circuit (hereinafter referred to as IC) having a storage capacity of 16k bits and an output of 8 bits as a reference example. .

The 16k-bit memory cell has eight matrices (memory arrays M-ARY1 to M-ARY8) each having a storage capacity of 128 columns (rows) x 16 rows (columns) = 2048 bits (2k bits).
And each matrix is divided into four rows on the left and right sides of the row decoder R-DCR.

Row-related address selection lines (word lines WL1 to WL128, WR1 to WR
128) is obtained based on the address signals A _{0 to} A ₆ 2 ⁷
= 128 different decode output signals are sent from the row decoder R-DCR.

In this way, the memory M-CEL of each matrix is word line W
One of L1 to WL128 and WR1 to WR128 is connected to one of complementary data line pairs D11, 11 to D132, 132 described later.

The word line intermediate buffers MB1 and MB2 have an amplifying action to minimize the delay time at the ends of the word lines WL1 to WL128 and WR1 to WR128, respectively.
It is located between Y3 and M-ARY6 and M-ARY7.

Address signal A ₇ to A ₁₀ is used to select one each of the column from the eight matrices.

The column decoder C-DCR provides 2 ⁴ = 16 different column select decode output signals based on the address signals A _{7 to} A ₁₀ .

The address buffer ADB generates 11 pairs of complementary address signals a ₀ to a ₁₀ from 11 external address signals A _{0 to} A ₁₀ , respectively,
It is sent to the decoder circuit (R-DCR, C-DCR).

Internal control signal generation circuit COM-GE has three external control signals ▲
In response to ▼ (chip select signal), ▲ ▼ (write enable) signal, ▲ ▼ (output enable signal), CS1 (row decoder control signal), CS12 (sense amplifier and data input buffer control signal), w ・ c
(Write control signal), · c · o (data output buffer control signal), etc. are transmitted.

[2k word × 8 bit S-RAM circuit operation] The circuit operation of the S-RAM IC shown in FIG. 3A will be described with reference to the timing chart of FIG.

All the operations in this IC, that is, the address setting operation, the reading operation, and the writing operation are performed only while the external control signal ▲ ▼ is at the low level. At this time, if the other external control signal ▲ ▼ is high level, read operation is performed,
If it is low level, write operation is performed.

The external control signal () is used to control the output timing when sending an 8-bit output signal to the outside of the IC.

First, the address setting operation and the read operation will be described.

The address setting operation is always performed based on the signal applied during this period when the external control signal ▲ ▼ is low level. On the contrary, by setting the external control signal ▲ ▼ to the high level, the address setting operation and the read operation based on the uncertain address signal can be prevented.

When the external control signal () becomes low level, the row decoder R-DCR receives the high level internal control signal CS1 synchronized with this signal and starts its operation. The row decoder (and word driver) R-DCR decodes seven types of complementary pair address signals a ₀ to a ₆ and selects a pair of left and right word lines,
This is driven to high level.

On the other hand, the column decoder C-DCR has eight memory arrays M.
Select one column each from -ARY1 to M-ARY8.

In this way, one for each memory array, or a total of 8
Two memory cells are selected (address setting).

Information of the memory cell selected by the address setting operation is sent to the common data line pair CDL, ▲ ▼ of each memory array and amplified by each sense amplifier SA.

The sense amplifier SA operates while receiving the high-level control signal CS12 synchronized with the external control signal ▲ ▼.

The output signal of the sense amplifier SA is amplified by the data output buffer DOB and sent as output data Dout1 to Dout8 to the outside of the IC.

The data output buffer DOB operates while receiving the high-level control signal .co.o.

Next, the write operation will be described.

When both the external control signals ▲ ▼ and ▲ ▼ become low level, the high level control signals w and c synchronized with this are applied to the write control transistors (Q ₁ , ₁ ; ... Q ₄ , ₄ ) and each common data The line pair CDL, ▲ ▼ and each data input buffer DIB are coupled.

On the other hand, the data input buffer DIB provided corresponding to each memory array has eight input data signals Di applied from the outside of the IC during the period of receiving the low level control signal CS12.
Each of n1 to Din8 is amplified and sent to the common data line pair CDL, ▲ ▼ provided corresponding to each memory array.

Each input data signal on the common data line pair has eight memory cells M-CE defined by the address setting operation.
Written to L respectively.

[Memory cell circuit]

FIG. 4 shows the circuit of the 1-bit memory cell M-CEL in the memory array of FIGS. 2A and 3A. This memory cell has load resistors R ₁ and R ₂ and a driving MISFET connected in series.
(Insulated Gate Field Effect Transistor) A pair of inverter circuits composed of Q ₁ and Q ₂ with cross-coupled input and output of a flip-flop and a pair of transmission gate MISF
It is composed of ETQ ₃ and Q ₄ . The flip-flop is used as a storage means of information, and the transmission gate is connected to the flip-flop and the complementary data line pair D, (D ₁₁ ,
₁₁ ...... D _{132, 132} are used as an address means for controlling the transfer of information between, the behavior is the row decoder R-DCR connected to the word line W (WL1, ...... WL128, WR
1, ... WR128) controlled by the address signal applied.

[Peripheral circuit]

FIG. 5 shows a peripheral circuit, for example, the data output buffer DOB shown in FIGS. 2A and 3A. This data output buffer DOB outputs Vou when the control signal Cont is logic "1" (+ Vcc).
When t becomes a logical value according to the input In, a very low output impedance is obtained, and when Cont is “0”, Vout becomes an undefined level that is not related to the input In, that is, a very high output impedance is obtained. To be Thus, a buffer with both high and low output impedance allows Wired-OR of multiple buffer outputs.

The final stage, so that it can drive a heavy load at high speed, the driving capability larger bipolar transistor Q ₁₀₅ is used,
The Q ₁₀₅ forms a push-pull circuit together with the N-channel MISFET Q _106, which has a larger driving capacity than the P-channel MISFET.

FIG. 6 is a circuit diagram showing an embodiment of the sense amplifier SA used in the static RAM described above.

In this embodiment, a first asymmetrical differential amplifier circuit P ₁ composed of differential MISFETs Q ₂₀₁ , Q ₂₀₂ and active load MISFETs Q ₂₀₃ , Q ₂₀₄ constituting current mirror circuits provided at the respective drains, and The second asymmetric differential amplifier circuit P ₂ having the same structure as the asymmetric differential amplifier circuit P ₁ composed of the MISFETs Q _{205 to} Q ₂₀₈ has a common data line pair CDL, ▲.
Receiving signals Di and ▲ from ▼, output signals of opposite phase To form. That is, the gates of the MISFETs Q ₂₀₂ and Q ₂₀₆ which are the inverting input terminals (−) of the first and second asymmetrical differential amplifier circuits P ₁ and P ₂ respectively have the above-mentioned signals. Is applied. And MI, which is the non-inverting input terminal (+)
The gate of SFETQ _201, Q _205, signals by the intersection connection Are respectively applied. In this embodiment, the first and second
MISFET Q ₂₀₉ forming a common constant current source is provided for the asymmetric differential amplifier circuits P ₁ and P ₂ . This MISFETQ
₂₀₉ instead of each differential MISFET Q ₂₀₁ , Q ₂₀₂ and Q ₂₀₅ , Q
A common source of ₂₀₆ may be provided with a MISFET as a constant current source.

In this embodiment, in order to increase the voltage gain in the sense amplifier, the output signals from the _first and _second asymmetric differential amplifier circuits P ₁ and P ₂ are Is applied to a _third asymmetric differential amplifier circuit P ₃ having the same configuration as the asymmetric differential amplifier circuits P ₁ and P ₂ configured by MISFETs Q _{210 to} Q ₂₁₄ .

The output signal OUT (Di ″) from the _third asymmetric differential amplifier circuit P ₃ is the data output buffer D shown in FIG.
It is transmitted to the input / output terminal IN of OB.

Further, the MISFETs Q ₂₀₉ and Q ₂₁₄ as the constant current source are
In the case of the divided sense amplifier as shown in the figure, the switch control is performed by the control circuit CONT including the inverter circuits IV ₁ and IV ₂ and the MISFETs Q _{215 to} Q ₂₁₈ which receive the control signal SAC and the memory array selection signal mi. It On the other hand, in the case of a sense amplifier which is not divided with respect to the corresponding data output buffer as in the embodiment of FIG. 3A, the signal CS12 as shown in FIG. 3B is MISFET Q ₂₀₉ as the constant current source and
_{Applied to} the gate of Q ₂₁₄ .

According to this embodiment, two asymmetrical differential amplifier circuits P ₁ , P
Balanced signal using ₂ Is formed. Therefore, even if each of the asymmetrical differential amplifier circuits P ₁ and P ₂ has an offset voltage, when they are formed in the same monolithic IC, the above-mentioned offset voltage is generated in the same manner, and the two are canceled. be able to.

Also the input signal Even if the nozzles of the same phase are mounted on these, these can be offset.

Moreover, in order to increase the amplification factor, a similar asymmetrical differential amplifier circuit P ₃ can be provided in the next stage. The offset voltage of the asymmetrical differential amplifier circuit P ₃ is transmitted to the next stage, Since the signal level of is high, it can be practically ignored.

As a result, it is possible to reduce the influence of the offset voltage and noise, and obtain a sense amplifier with high sensitivity and high amplification factor.

By the way, the signal from the common data line pair CDL, ▲ ▼ Even if the voltage difference between the two is as small as about 0.2 V, the sense amplifier SA of this embodiment can form an output signal sufficient to drive the data output buffer DOB, and the high speed operation of the static RAM can be achieved.

In the embodiment circuit of FIG. 6, the third asymmetric differential amplifier circuit P ₃ is omitted and the signal May be transmitted to the data output buffer DOB at the next stage. In this case, the data output buffer DOB shown in FIG.
, The inverter circuit G ₁₀₂ is omitted and the signal Is directly input to terminals T ₁ and T ₂ .

In this case, the balanced signal Is used as the output signal, the amplification factor can be doubled as compared with the case where one asymmetric differential amplifier circuit is used as described above. Then, as described above, the offset voltage and the common mode noise can be canceled out.

FIG. 7 shows a block diagram of another embodiment of the present invention.

In this embodiment, the asymmetric differential amplifier circuits P ₁ , P
₂ , the balanced signal To form. Then, a similar asymmetrical differential amplifier circuit P ₄ , P
₅ is provided to form the balanced output signal OUT, ▲ ▼. The specific circuit of each asymmetrical differential amplifier circuit P ₁ , P ₂ and P ₄ , P _{5 is} the same as the circuit of FIG. 6, and therefore its explanation is omitted.

In the data output buffer DOB of FIG. 5, the inverter circuit G ₁₀₃ is omitted,
It is directly input to one of the input terminals T ₁ and T ₂ of the gate circuits G ₁₀₁ and G ₁₀₂ , respectively. In this embodiment, since the output signal is also a balanced signal, the output side asymmetrical differential amplifier circuits P ₄ , P
The offset voltage of ₅ can also be canceled. Further, the amplification factor can be doubled as compared with the circuit of the embodiment shown in FIG.

As a result, it is possible to further reduce the influence of the offset voltage and noise, and obtain a sense amplifier with high sensitivity and high amplification factor.

FIG. 8 is a circuit diagram showing another specific embodiment of the asymmetrical differential amplifier circuit P.

In this embodiment, as a load of the differential MISFETQ ₂₁₉ and Q ₂₂₀ , a MISFETQ ₂₂₁ having a grounded gate and these MISFETQ ₂₁₉ and Q220 are provided.
₂₂₁ is composed of MISFET Q ₂₂₂ whose common drain is connected to its gate. In this embodiment, since the source-gate voltage of the load MISFET Q ₂₂₂ can be increased, a higher amplification factor can be obtained as compared with the case where a current mirror circuit is used, but the offset voltage becomes large. However, when the asymmetrical differential amplifier circuits P ₁ , P ₂ and P ₄ , P ₅ shown in FIGS. 6 and 7 are used, the offset voltage can be canceled out, which causes a problem. In no case, the high amplification factor is utilized.

FIG. 9 shows a layout diagram when the asymmetrical amplifier circuits P ₁ and P ₂ shown in FIGS. 6 and 7 are formed on a monolithic IC.

In the same figure, thick solid lines indicate aluminum wiring, power supply voltage Vcc, ground GND line, and differential MISFETQ.
Common source connection for ₂₀₁ , Q ₂₀₂ and Q ₂₀₅ , Q ₂₀₆ , differential MISFET
Is used for the common drain connection between the load and the load MISFET.

The thin solid line shows the conductive polysilicon layer,
It is used for the gate electrode of each MISFET and the wiring related thereto.

The broken line indicates a p-type or n-type diffusion region, which is used for connecting the source or drain of the MISFET and the gate of the differential MISFET.

The alternate long and short dash line indicates the p-type well region formed on the n-type substrate. Therefore, n in this P-Well
A channel MISFET is formed. Also, Indicates a contact.

The present invention is not limited to the above embodiment.

The system configuration of the static RAM can take various embodiments.

[Brief description of drawings]

FIG. 1 is a block diagram of a static memory system, FIG. 2A is a block diagram of the internal structure of the S-RAM IC of the embodiment, FIG. 2B is a timing diagram of the S-RAM IC of FIG. 2A, and FIG. 3A is a reference example. FIG. 3B is a block diagram of the internal structure of the S-RAM IC of FIG. 3, FIG. 3B is a timing diagram of the S-RAM IC of the reference example of FIG. 3A, and FIG. Is a circuit diagram of a data output buffer, FIG. 6 is a circuit diagram of a sense amplifier, FIG. 7 is a block diagram of another sense amplifier, and FIG. 8 is another asymmetric differential amplifier used in the sense amplifier. A circuit diagram of the circuit and FIG. 9 are layout diagrams of main parts of the sense amplifier.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masaru Yamamoto 1450, Kamimizumoto-cho, Kodaira-shi, Tokyo Hitachi, Ltd. Musashi factory (72) Inventor Kazuo Yoshizaki 1450, Kamimizumoto-cho, Kodaira-shi, Tokyo Hitachi, Ltd. Musashi Plant (72) Inventor Yukio Akima 1479, Kamimizuhonmachi, Kodaira-shi, Tokyo In-house Hitachi Micro Computer Engineering Co., Ltd. (56) References Electronics 1 May 24, 1979, vol. 52, No. 11, P. 137-141

Claims (3)

[Claims] 1. A plurality of memory arrays each having memory cells arranged in a matrix, a plurality of column selecting means provided corresponding to each of the memory arrays, and a plurality of column selecting means. A plurality of common data line pairs to which the data signals from the selected memory cells in the memory array corresponding to the column selecting means are respectively applied, and the common data line pairs are provided corresponding to the respective common data line pairs. A plurality of sense amplifiers whose input terminals are coupled to the corresponding common data line pair, and each of the plurality of sense amplifiers having a pair of differential inputs whose input terminals are coupled to the corresponding common data line. In response to the current on the output side of the element and one of the elements of the differential input element, it is combined with the current on the output side of the other element of the differential input element to reach the output point. A plurality of sense amplifiers, each of which includes an asymmetric load means for forming a current to be supplied, and a current source connected in series to a series path of the differential input element and the asymmetric load means and operation-controlled by a control signal The output points of are commonly connected to each other, and the sense amplifier corresponding to the common data line of the plurality of common data lines to be read in data reading is selectively operated by the control signal. A semiconductor memory device characterized by the following. 2. The differential input element is a first conductivity type MISFET.
2. The semiconductor memory device according to claim 1, wherein the asymmetrical load means is a current mirror load circuit including a second conductivity type MISFET. 3. The semiconductor memory device according to claim 1 or 2, wherein the current source is a second conductivity type MISFET.