JPH07192966A - Ceramic capacitor - Google Patents
Ceramic capacitorInfo
- Publication number
- JPH07192966A JPH07192966A JP5331662A JP33166293A JPH07192966A JP H07192966 A JPH07192966 A JP H07192966A JP 5331662 A JP5331662 A JP 5331662A JP 33166293 A JP33166293 A JP 33166293A JP H07192966 A JPH07192966 A JP H07192966A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic capacitor
- external electrodes
- circuit board
- ceramic
- chip type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は回路基板に直接はんだ付
けされるチップ型のセラミックコンデンサに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type ceramic capacitor which is directly soldered to a circuit board.
【0002】[0002]
【従来の技術】電子機器の小型化、高速デジタル化にと
もない、これら電子機器に用いる電子部品も小型化、高
速デジタル化対応の要請が強い。このため、電子部品の
代表的なものであるコンデンサにおいても、セラミック
誘電体を用いたチップ型のセラミックコンデンサ、例え
ば小型大容量で高周波特性に優れたチップ型積層セラミ
ックコンデンサが多用されている。2. Description of the Related Art With the miniaturization and high speed digitalization of electronic equipment, there is a strong demand for miniaturization and high speed digitalization of electronic parts used in these electronic equipment. Therefore, also in capacitors which are typical of electronic parts, chip-type ceramic capacitors using a ceramic dielectric, for example, chip-type multilayer ceramic capacitors which are small and have a large capacity and excellent in high frequency characteristics are often used.
【0003】このチップ型積層セラミックコンデンサ
は、複数の誘電体セラミック層と、その誘電体セラミッ
ク層を介して互いに積層された複数の内部電極層とから
なる積層型誘電体セラミック本体の両端部に、内部電極
の所定のものに接続される外部電極が形成されている。
そして、回路基板への実装は、図5に示すようにチップ
型積層セラミックコンデンサ1の外部電極2と回路基板
5の導体部6とをはんだ4で直接接合して行なってい
る。This chip type monolithic ceramic capacitor has a multi-layer dielectric ceramic body composed of a plurality of dielectric ceramic layers and a plurality of internal electrode layers laminated on each other via the dielectric ceramic layers. External electrodes are formed that are connected to predetermined ones of the internal electrodes.
The mounting on the circuit board is performed by directly joining the external electrodes 2 of the chip type monolithic ceramic capacitor 1 and the conductor portions 6 of the circuit board 5 with solder 4 as shown in FIG.
【0004】[0004]
【発明が解決しようとする課題】このようなチップ型積
層セラミックコンデンサは、その主要構成材料がセラミ
ックであるため可撓性がない。このため実装後のセラミ
ックコンデンサは、回路基板のたわみや熱ストレスなど
による膨脹、収縮などの物理的ストレスの影響を受けや
すく、図5に示すようにクラックC等が発生してセラミ
ックコンデンサが破損することがあった。このような破
壊は、タンタル電解コンデンサやアルミ電解コンデンサ
の代わりに、チップ型のセラミックコンデンサとして、
高周波特性や無極性を生かして、大容量、大型のチップ
型積層セラミックコンデンサを使用する場合にしばしば
起こった。Such a chip-type monolithic ceramic capacitor is not flexible because its main constituent material is ceramic. Therefore, the mounted ceramic capacitor is easily affected by physical stress such as expansion and contraction of the circuit board due to bending and thermal stress, and cracks C and the like occur as shown in FIG. 5 to damage the ceramic capacitor. There was an occasion. This kind of destruction is a chip type ceramic capacitor instead of a tantalum electrolytic capacitor or an aluminum electrolytic capacitor.
This often occurred when a large-capacity, large-sized chip type multilayer ceramic capacitor was used by taking advantage of high frequency characteristics and non-polarity.
【0005】この対策として、回路基板へはんだ付けす
るときに使用するはんだ量を極力少なくし、はんだを介
してチップ型積層セラミックコンデンサへ加わるストレ
スを押さえること等が試みられている。しかし、この方
法は量産時に再現性よくはんだ量を一定に維持すること
が難しく、一方ではんだ量が少なすぎると固着力が不足
して逆に接続の信頼性が悪くなることもあり、根本的な
解決策とはなり得ていない。As measures against this, it has been attempted to reduce the amount of solder used when soldering to a circuit board as much as possible to suppress the stress applied to the chip type multilayer ceramic capacitor through the solder. However, this method is difficult to maintain a constant amount of solder with good reproducibility during mass production. On the other hand, if the amount of solder is too small, the adhesion may be insufficient and the reliability of the connection may worsen. Not a good solution.
【0006】そこで、本発明の目的は、回路基板へ実装
後のチップ型のセラミックコンデンサに加わる物理的ス
トレスの影響を極力低減することができ、クラックや剥
離等の破損を生じることのない、信頼性の高いセラミッ
クコンデンサを提供することにある。Therefore, an object of the present invention is to minimize the effect of physical stress applied to a chip type ceramic capacitor after mounting on a circuit board, and to prevent damages such as cracks and peeling, and to improve reliability. It is to provide a ceramic capacitor having high performance.
【0007】[0007]
【課題を解決するための手段】上記目的を達成するた
め、本発明のセラミックコンデンサは、両端部に外部電
極が形成された複数個のチップ型セラミックコンデンサ
を、方向を揃えて隣接並置させ、その隣接する外部電極
同志を可撓性を有する導電性樹脂にて電気的に接続し、
外部電極が設けられていない隣接部分を可撓性を有する
絶縁性樹脂にて機械的に接合し、対向する外部電極のう
ちはんだの付く材料で形成した外部電極は互いに対角位
置に位置させたことを特徴とする。In order to achieve the above object, the ceramic capacitor of the present invention has a plurality of chip-type ceramic capacitors having external electrodes formed at both ends thereof, which are arranged side by side in the same direction. The adjacent external electrodes are electrically connected with a conductive resin having flexibility,
Adjacent parts not provided with external electrodes were mechanically joined with a flexible insulating resin, and the external electrodes formed of a material with solder among the opposing external electrodes were positioned diagonally to each other. It is characterized by
【0008】[0008]
【作用】本発明のセラミックコンデンサは、複数のセラ
ミックコンデンサを可撓性のある樹脂で隣接接合して構
成され、かつ回路基板とはんだ付けされる外部電極は、
接合したセラミックコンデンサの中で互いに対角位置に
位置されるように形成されている。したがって、回路基
板に実装後、回路基板のたわみや熱ストレス等によりは
んだ付け部分を介してセラミックコンデンサがストレス
を受けても、セラミックコンデンサを接合した可撓性樹
脂の部分が変形してそのストレスは緩和される。The ceramic capacitor of the present invention is formed by adjoining a plurality of ceramic capacitors adjacent to each other with a flexible resin, and the external electrodes soldered to the circuit board are:
It is formed so as to be positioned diagonally to each other in the joined ceramic capacitors. Therefore, after mounting on the circuit board, even if the ceramic capacitor is stressed through the soldered part due to deflection of the circuit board, thermal stress, etc., the flexible resin part to which the ceramic capacitor is bonded is deformed and the stress is reduced. Will be alleviated.
【0009】[0009]
【実施例】以下、本発明のセラミックコンデンサの実施
例を、チップ型積層セラミックコンデンサを例として図
面に基づき説明する。図1は第1の実施例を示す斜視
図、図2は図1の第1の実施例のセラミックコンデンサ
を回路基板にはんだ付け実装した状態を示す斜視図であ
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the ceramic capacitor of the present invention will be described below with reference to the drawings by taking a chip type monolithic ceramic capacitor as an example. 1 is a perspective view showing a first embodiment, and FIG. 2 is a perspective view showing a state in which the ceramic capacitor of the first embodiment of FIG. 1 is mounted on a circuit board by soldering.
【0010】本実施例のセラミックコンデンサは、2個
のチップ型積層セラミックコンデンサを隣接貼り合わせ
た構造となっている。即ち、図1において、1は互いに
方向を揃えて隣接並置されたチップ型積層セラミックコ
ンデンサ、2はAg等を主成分とする電極ペーストを塗
布・焼き付けしたはんだの付く外部電極、3はPd等を
主成分とするペーストを塗布・焼き付けしたはんだの付
かない外部電極である。7はAgを主成分とするエポキ
シ系の可撓性を有する導電性樹脂で、2つのチップ型積
層セラミックコンデンサ1の互いに隣接する外部電極2
と外部電極3とを接合し電気的に接続している。8はエ
ポキシ系の可撓性を有する絶縁性樹脂であり2つのチッ
プ型積層セラミックコンデンサ1を機械的に接合してい
る。The ceramic capacitor of this embodiment has a structure in which two chip type monolithic ceramic capacitors are adhered to each other. That is, in FIG. 1, 1 is a chip type multilayer ceramic capacitor which is arranged in parallel with each other in the same direction, 2 is an external electrode with solder applied and baked with an electrode paste containing Ag as a main component, and 3 is Pd or the like. It is an external electrode that does not have solder applied and baked with the main component paste. Reference numeral 7 denotes an epoxy-based conductive resin having Ag as a main component and having flexibility, and external electrodes 2 adjacent to each other of two chip type monolithic ceramic capacitors 1.
And the external electrode 3 are joined and electrically connected. Reference numeral 8 denotes an epoxy-based flexible insulating resin, which mechanically joins the two chip type monolithic ceramic capacitors 1.
【0011】このように形成されたセラミックコンデン
サは、前記はんだの付く外部電極2が互いに対角位置に
位置されている。このため回路基板への実装時は、図2
に示すように対角線方向に位置するはんだの付く外部電
極2のみで回路基板5の導体部6にはんだ付けされる。
しかも実装されたセラミックコンデンサは、2つの積層
セラミックコンデンサ1が可撓性を有する導電性樹脂7
および可撓性を有する絶縁性樹脂8で接合されているた
め、回路基板5のたわみや熱ストレス等によりはんだ4
を介してストレスを受けても、可撓性を有する導電性樹
脂7および可撓性を有する絶縁性樹脂8の部分が容易に
変形してストレスは緩和される。このため、ストレスに
耐え切れずにセラミックコンデンサにクラックや剥離等
が生じるという恐れがない。In the ceramic capacitor thus formed, the external electrodes 2 to which the solder is attached are located diagonally to each other. Therefore, when mounting on the circuit board,
As shown in FIG. 5, only the external electrodes 2 to which the solder is attached, which are diagonally positioned, are soldered to the conductor portion 6 of the circuit board 5.
Moreover, the mounted ceramic capacitors are made up of the conductive resin 7 having flexibility in the two monolithic ceramic capacitors 1.
Also, since the insulating resin 8 having flexibility is bonded, the solder 4 is deformed due to bending of the circuit board 5 or thermal stress.
Even if a stress is applied via, the portions of the conductive resin 7 having flexibility and the insulating resin 8 having flexibility are easily deformed, and the stress is relieved. Therefore, there is no fear that the ceramic capacitor will not be able to withstand stress and cracks or peeling will occur.
【0012】なお、チップ型積層セラミックコンデンサ
の外部電極材は、上記実施例に限定されるものではな
い。例えば、はんだの付く外部電極としては、従来から
積層セラミックコンデンサの外部電極として公知のCu
電極、Ni(下層)−Sn(上層)めっき電極またはは
んだめっき電極等を用いることができる。また、はんだ
の付かない外部電極としては、Ni系電極又はAgを主
成分とする焼き付け電極にガラスフリットを多量に添加
したもの等を用いることができる。The external electrode material of the chip type monolithic ceramic capacitor is not limited to the above embodiment. For example, as an external electrode to which solder is attached, Cu which is conventionally known as an external electrode of a laminated ceramic capacitor is used.
Electrodes, Ni (lower layer) -Sn (upper layer) plated electrodes, solder plated electrodes, or the like can be used. As the external electrode without solder, a Ni-based electrode or a baked electrode containing Ag as a main component and a large amount of glass frit added thereto can be used.
【0013】また、チップ型積層セラミックコンデンサ
の外部電極を電気的に接続する導電性樹脂、あるいはチ
ップ型積層セラミックコンデンサを接合する絶縁性樹脂
も、上記実施例に限定されるものではない。たとえば、
可撓性を有する導電性樹脂としては、導電性成分として
Ag以外にCu等を用いることができ、樹脂成分として
は、シリコン樹脂等を用いることができる。また、可撓
性を有する絶縁性樹脂としても、同様にシリコン樹脂等
を用いることができる。Further, the conductive resin for electrically connecting the external electrodes of the chip type multilayer ceramic capacitor or the insulating resin for bonding the chip type multilayer ceramic capacitor is not limited to the above embodiment. For example,
As the conductive resin having flexibility, Cu or the like can be used as the conductive component in addition to Ag, and the silicon resin or the like can be used as the resin component. Further, as the flexible insulating resin, a silicone resin or the like can be used as well.
【0014】さらに、チップ型積層セラミックコンデン
サの貼り合わせ枚数、方向は前記実施例に限定されるも
のではなく、セラミックコンデンサの静電容量、用途等
に応じて適宜設計することができる。以下に、他の実施
例を示す。Further, the number and direction of the chip type laminated ceramic capacitors to be bonded are not limited to those in the above embodiment, but can be appropriately designed according to the electrostatic capacitance of the ceramic capacitor, the application and the like. Another embodiment will be described below.
【0015】図3は第2の実施例を示し、3つのチップ
型積層セラミックコンデンサを、その厚みの薄い方向に
重ねて接合したものである。その他の部分は、第1の実
施例である図1と同一であるので、同一番号を付して説
明は省略する。また、図4は第3の実施例を示し、4つ
のチップ型積層セラミックコンデンサを接合したもので
ある。その他の部分は、第1の実施例である図1と同一
であるので、同一番号を付して説明は省略する。FIG. 3 shows a second embodiment, in which three chip type monolithic ceramic capacitors are superposed and joined in the direction of thinness. Since the other parts are the same as those in FIG. 1 which is the first embodiment, the same reference numerals are given and the description thereof will be omitted. Further, FIG. 4 shows a third embodiment in which four chip type monolithic ceramic capacitors are joined. Since the other parts are the same as those in FIG. 1 which is the first embodiment, the same reference numerals are given and the description thereof will be omitted.
【0016】なお、以上の実施例においては、セラミッ
クコンデンサとしてチップ型積層セラミックコンデンサ
の場合について説明したが、本発明はこれのみに限定さ
れることなく、広くチップ型のセラミックコンデンサの
場合に同様の効果が得られることは言うまでもない。In the above embodiments, the case of the chip type multilayer ceramic capacitor as the ceramic capacitor has been described, but the present invention is not limited to this, and is widely applied to the case of a chip type ceramic capacitor. It goes without saying that the effect can be obtained.
【0017】[0017]
【発明の効果】以上の説明で明らかなように、本発明の
セラミックコンデンサによれば、回路基板に実装した
後、基板のたわみや熱ストレス等によりはんだ付け部分
を介してセラミックコンデンサがストレスを受けても、
セラミックコンデンサを接合した可撓性樹脂の部分でそ
のストレスが緩和されて、セラミックコンデンサにクラ
ック等の損傷が起きるのを防止できる。したがって、信
頼性の高いセラミックコンデンサを得ることができる。As is apparent from the above description, according to the ceramic capacitor of the present invention, after being mounted on the circuit board, the ceramic capacitor is subjected to stress through the soldered portion due to the deflection of the board, thermal stress, or the like. Even
It is possible to prevent the stress from being relieved at the flexible resin portion to which the ceramic capacitor is joined and the ceramic capacitor from being damaged such as cracks. Therefore, a highly reliable ceramic capacitor can be obtained.
【0018】また、この効果は、タンタル電解コンデン
サやアルミ電解コンデンサの代わりとして、大容量、大
型のセラミックコンデンサに適用する場合に特に顕著と
なる。Further, this effect is particularly remarkable when applied to a large-capacity, large-sized ceramic capacitor as a substitute for the tantalum electrolytic capacitor or the aluminum electrolytic capacitor.
【図1】本発明のセラミックコンデンサの第1の実施例
を示す斜視図である。FIG. 1 is a perspective view showing a first embodiment of a ceramic capacitor of the present invention.
【図2】第1の実施例のセラミックコンデンサを回路基
板上にはんだ付け実装した状態を示す斜視図である。FIG. 2 is a perspective view showing a state where the ceramic capacitor of the first embodiment is soldered and mounted on a circuit board.
【図3】本発明のセラミックコンデンサの第2の実施例
を示す斜視図である。FIG. 3 is a perspective view showing a second embodiment of the ceramic capacitor of the present invention.
【図4】本発明のセラミックコンデンサの第3の実施例
を示す斜視図である。FIG. 4 is a perspective view showing a third embodiment of the ceramic capacitor of the present invention.
【図5】従来のセラミックコンデンサを回路基板上には
んだ付け実装した状態を示す斜視図である。FIG. 5 is a perspective view showing a state in which a conventional ceramic capacitor is mounted by soldering on a circuit board.
1 チップ型積層セラミックコンデンサ 2 はんだの付く外部電極 3 はんだの付かない外部電極 4 はんだ 5 回路基板 6 回路基板の導体部 7 可撓性を有する導電性樹脂 8 可撓性を有する絶縁性樹脂 1 Chip Type Multilayer Ceramic Capacitor 2 External Electrode with Solder 3 External Electrode without Solder 4 Solder 5 Circuit Board 6 Conductor of Circuit Board 7 Flexible Conductive Resin 8 Flexible Insulating Resin
Claims (1)
チップ型セラミックコンデンサを、方向を揃えて隣接並
置させ、その隣接する外部電極同志を可撓性を有する導
電性樹脂にて電気的に接続し、外部電極が設けられてい
ない隣接部分を可撓性を有する絶縁性樹脂にて機械的に
接合し、対向する外部電極のうちはんだの付く材料で形
成した外部電極は互いに対角位置に位置させたことを特
徴とするセラミックコンデンサ。1. A plurality of chip type ceramic capacitors having external electrodes formed on both ends thereof are arranged side by side in the same direction, and the adjacent external electrodes are electrically connected by a conductive resin having flexibility. Connected to each other, and the adjacent parts where no external electrodes are provided are mechanically joined with a flexible insulating resin. A ceramic capacitor characterized by being located at.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33166293A JP3168801B2 (en) | 1993-12-27 | 1993-12-27 | Ceramic capacitors |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33166293A JP3168801B2 (en) | 1993-12-27 | 1993-12-27 | Ceramic capacitors |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07192966A true JPH07192966A (en) | 1995-07-28 |
JP3168801B2 JP3168801B2 (en) | 2001-05-21 |
Family
ID=18246181
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP33166293A Expired - Lifetime JP3168801B2 (en) | 1993-12-27 | 1993-12-27 | Ceramic capacitors |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3168801B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000012301A (en) * | 1998-06-24 | 2000-01-14 | Murata Mfg Co Ltd | Method for mounting electronic part |
JP2012522382A (en) * | 2009-03-26 | 2012-09-20 | ケメット エレクトロニクス コーポレーション | Leaded multilayer ceramic capacitor with low ESL and ESR |
-
1993
- 1993-12-27 JP JP33166293A patent/JP3168801B2/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000012301A (en) * | 1998-06-24 | 2000-01-14 | Murata Mfg Co Ltd | Method for mounting electronic part |
JP2012522382A (en) * | 2009-03-26 | 2012-09-20 | ケメット エレクトロニクス コーポレーション | Leaded multilayer ceramic capacitor with low ESL and ESR |
Also Published As
Publication number | Publication date |
---|---|
JP3168801B2 (en) | 2001-05-21 |
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