JPH07191787A - Control card - Google Patents

Abstract

PURPOSE:To obtain a control card whereby unrequired power consumption is restrained and electric power is saved. CONSTITUTION:A judging means 3 and a storage means 7 normally receive the supply of a power source from a power source line 2 and a read/write control signal buffer 3, a timing circuit 5, a combinational circuit 6 and an input/output buffer 8 are connected to the power source line 2 with a switching means 9. While the judging means 3 judges that a selecting signal is not the signal selecting itself, the switching means 9 is in a non-conductive state so that the read/write control signal buffer 4, the timing circuit 5, the combinational circuit 6 and the data input/output buffer 8 are separated from the power source line 2. When an activating signal is outputted from the judging means 3, the switching means 9 becomes the conductive state. Then, an internal control signal is outputted, the storage means 7 writes or reads data and the switching means 9 becomes the non-conductive state when writing/reading is completed so that the circuits are separated from the power source line 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is implemented in a computer and, for example, based on a control signal transmitted by a common bus connected to the computer, it is possible to perform a specific control such as display control or communication control. The present invention relates to various control cards such as a memory card for controlling or holding data.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional control card. In FIG. 2, reference numeral 1 is connected to a computer (not shown) and a card selection signal consisting of an address signal for selecting a card, data and A common bus for transmitting control signals and the like, 2 is a power supply line for supplying power,
3 is connected to the power supply line 2 to receive power supply, receives a card selection signal transmitted to the common bus 1, and activates when it is determined that the received card selection signal is a signal that selects itself. It is a determination circuit that outputs a signal, and in this example, a decoding circuit that decodes an address signal that is a card selection signal. Reference numeral 4 is a read / write control signal buffer which is connected to the power supply line 2 to receive power and receive the read / write control signal transmitted to the common bus.

Reference numeral 5 is a timing circuit which is connected to the power supply line 2 to receive power supply and outputs a timing signal composed of a clock signal, and 6 is connected to the power supply line 2 to receive power supply and It is activated in response to the activation signal from the judging means 3, receives the read / write control signal from the read / write control signal buffer 4, and outputs an internal control signal synchronized with the timing signal from the timing circuit. It is a combinational circuit and constitutes the control means together with the timing circuit 5. Reference numeral 7 is a storage means for storing data, which is controlled based on an internal control signal from the combinational circuit 6 and is capable of writing and reading data, and 8 is connected to the power supply line and supplied with power, and It is connected between the common bus 1 and the storage means 7, transmits write data from the common bus 1 to the storage means 7, and outputs data read from the storage means 7 to the common bus 1. It is a data input / output buffer for performing.

Next, the operation of the conventional control card thus constructed will be described. The determination means 3, the read / write control signal buffer 4, the timing circuit 5, the combination circuit 6, the storage means 7, and the input / output buffer 8 are constantly supplied with power from the power supply line 2. The determination means 3 constantly monitors the card selection signal consisting of the address signal transmitted to the common bus 1, and outputs the activation signal when it determines that the card selection signal is the signal that has selected itself. At this time, the read / write control signal buffer 4 and the data input / output buffer 8 always transmit the signals transmitted to the common bus 1 to the combination circuit 6 and the storage means 7, but the combination circuit 6 determines the determination means 3. It is invalid until it is activated by receiving the activation signal from.

When the activation signal is output from the judging means 3, the combinational circuit 6 is activated and the timing circuit 5 is activated.
When the write control signal is received from the read / write control signal buffer 4 based on the timing signal of
The internal control signal necessary for writing to the storage means 7 is output to the storage means 7, and when the read control signal is received from the read / write control signal buffer 4, in order to read to the storage means 7. The necessary internal control signal is output to the storage means 7. The storage means 7, which has received the internal control signal for writing from the combinational circuit 6, writes the write data input from the common bus 1 through the data input / output buffer 8 to a predetermined address. Also,
The storage means 7, which has received the internal control signal for reading from the combinational circuit 6, reads the data stored at the predetermined address, and the read data is transmitted via the input / output buffer 8 to the common bus. It will be output to 1.

When the writing of data to the storage means 7 or the reading of data from the storage means 7 is thus completed based on the internal control signal from the combination circuit 6, the combination circuit 6 sends the data via the common bus 1. An operation end signal is output to the computer, and the computer deactivates the read / write control signal and data via the common bus 1 and finally deactivates the card selection signal to complete a series of operations. To do.

[0007]

However, in the conventional control card constructed as described above, the read / write control signal buffer 4, the timing circuit 5, the combination circuit 6 and the input / output buffer 8 are always provided. Because the power is supplied, even if the control card is not selected,
Since the read / write control signal buffer 4 and the input / output buffer 8 internally transmit the signal transmitted to the common bus 1, and the timing circuit 5 and the combination circuit 6 are also operating, the power is unnecessary. It has a problem that it consumes.

The idea of suppressing unnecessary current consumption is disclosed in, for example, Japanese Patent Laid-Open No. 63-170712, in which the supply of power supply voltage to the functional blocks controlled by the central processing unit is controlled by the central processing unit. Although it is shown by the method of controlling by the voltage supply control means in accordance with the control signal to the control signal, there is no idea to try to save power for each control card.

The present invention has been made in view of the above points, and an object of the present invention is to obtain a control card in which unnecessary power consumption is suppressed and power can be saved.

[0010]

A control card according to the present invention is connected to a power supply line and supplied with power, and also receives a card selection signal, and the received card selection signal is a signal for selecting itself. If the determination means outputs an activation signal, the one end is connected to the power supply line, becomes conductive when receiving the activation signal from the determination means, and is non-conductive when not receiving the activation signal from the determination means. The switching means in the state and the other end of the switching means are supplied with power from the power supply line through the switching means, and are activated by receiving the activation signal from the determination means. Output means, storage means for storing data controlled by an internal control signal from the control means, and the other end of the switching means. It is connected, in which is provided with receiving a supply of power from the power supply line via a switching means, and a data output buffer for performing output data read out from the storage means.

[0011]

According to the present invention, the switching means is rendered conductive when it receives the activation signal from the determination means, and is non-conductive when it does not receive the activation signal from the determination means. Power the data output buffer only when necessary.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIG. 1. In FIG. 1, reference numeral 1 is connected to a computer (not shown), and a card selection including an address signal for selecting a card. A common bus for transmitting signals, data, control signals, etc., 2 is a power supply line for supplying power, 3 is connected to the power supply line 1 to receive power supply, and is also transmitted to the common bus 1. The address signal which is the card selection signal in the present embodiment, when the received card selection signal determines that the received card selection signal is the signal that has selected itself, an activation signal is output. It is a decoding circuit that does.

One end of 9 is connected to the power supply line 2,
The switching means is in a conductive state when receiving the activation signal from the judging means 3, and is in a non-conducting state when not receiving the activation signal from the judging means 3. In this embodiment, the switching means is composed of, for example, a transistor. It has been done. Reference numeral 4 is connected to the other end of the switching means, receives power supply from the power supply line 2 through the switching means 9, and the common bus 1
And a read / write control signal buffer for receiving the read / write control signal transmitted to the. Reference numeral 5 is a timing circuit which is connected to the other end of the switching means 9, receives power from the power supply line 2 via the switching means 9, and outputs a timing signal composed of a clock signal.

Reference numeral 6 is connected to the other end of the switching means 9, receives power from the power supply line 2 through the switching means 9, and determines the judging means 3.
Is a combinational circuit that is activated by receiving an activation signal from the read / write control signal, receives the read / write control signal from the read / write control signal buffer 4, and outputs an internal control signal synchronized with the timing signal from the timing circuit. The timing circuit 5 constitutes a control means which is activated by receiving the activation signal from the determination means 3 and outputs an internal control signal. Reference numeral 7 is connected to the power supply line 1 and supplied with power, and is controlled based on an internal control signal from the combinational circuit 6 constituting the control means, and data can be written and read, and data is stored. In this embodiment, the memory means may be a DRAM type memory having a memory cell including one transistor and one capacitor, or an SRAM type memory cell having a flip-flop configuration memory cell. Also, it may be an EPROM type, or may be a simple ROM.

Reference numeral 8 is connected to the other end of the switching means 9 to receive power supply from the power supply line 2 via the switching means 9 and the common bus 1
For transmitting write data from the common bus 1 to the storage means 7 and outputting data read from the storage means 7 to the common bus 1. This is a data input / output buffer. The storage means 7 of the input / output buffer 8 is R
If it is an OM, a data output buffer for outputting the data read from the storage means 7 may be used. Reference numeral 10 is a control power supply pattern for connecting the other end of the switching means 9 and each power supply node of the read / write control signal buffer 4, the timing circuit 5, the combinational circuit 6 and the input / output buffer 8.

Next, the operation of the control card thus configured will be described. The determination means 3 and the storage means 7 are constantly supplied with power from the power supply line 2 and read / write.
The write control signal buffer 4, the timing circuit 5, the combination circuit 6, and the input / output buffer 8 are connected to the power supply line 2 via the control power supply pattern 10 and the switching means 9. The determination means 3 constantly monitors the card selection signal consisting of the address signal transmitted to the common bus 1, and outputs the activation signal when it determines that the card selection signal is the signal that has selected itself. While the determination unit 3 determines that the card selection signal is not the signal that selects itself, the switching unit 9 is in the non-conduction state because the activation signal is not output, and the read / write control signal buffer 4 is provided. , The timing circuit 5, the combinational circuit 6 and the data input / output buffer 8 are separated from the power supply line 2, and there is no unnecessary and unnecessary power consumption.

When the activating signal is output from the judging means 4, the switching means 9 receiving the activating signal becomes conductive, and the read / write control signal buffer 4, the timing circuit 5, the combination circuit 6 and the data input. The output buffer 8 receives power supply from the power supply line 2. Then, when the combination circuit 6 is activated by the activation signal from the determination means and the write control signal is received from the read / write control signal buffer 4 based on the timing signal of the timing circuit 5, the storage means 7 When the read control signal is output from the read / write control signal buffer 4 to the storage means 7, the internal control signal necessary for writing to the storage means 7 is output to the storage means 7. The control signal is output to the storage means 7.

The storage means 7, which has received the internal control signal for writing from the combinational circuit 6, writes the write data from the common bus 1 input via the data input / output buffer 8 at a predetermined address. Further, the storage means 7, which has received the internal control signal for reading from the combinational circuit 6, reads the data stored at the predetermined address, and the read data is passed through the input / output buffer 8. It will be output to the common bus 1.

When the writing of data to the storage means 7 or the reading of data from the storage means 7 is thus completed based on the internal control signal from the combination circuit 6, the combination circuit 6 sends the data via the common bus 1. An operation end signal is output to the computer, and the computer deactivates the read / write control signal and data via the common bus 1 and finally deactivates the card selection signal to complete a series of operations. To do. When the card selection signal is deactivated, the deciding means 3 does not output the activation signal, so that the switching means 9 becomes non-conductive and the read / write control signal buffer 4,
The timing circuit 5, the combination circuit 6 and the data input / output buffer 8 are separated from the power supply line 2.

Therefore, in the above embodiment, when the control card is not selected, the switching means 9 is in a non-conducting state and the control power supply pattern 10 is disconnected from the power supply line 2, so that it is necessary to operate. No power is supplied to those that do not exist, and unnecessary inter-element current does not flow, enabling minimum power consumption. Further, in the circuit design of the control card, the target circuit whose power source is uniquely controlled except for the determination unit 3 and the storage unit 7 can be used, and a complicated circuit design or the like is not required.

[0021]

As described above, the present invention is activated by receiving the activation signal from the determination means which outputs the activation signal when it is determined that the card selection signal is the signal which selects itself. One end is provided with a control means for outputting an internal control signal and a data output buffer for outputting the data read from the storage means for storing the data, which is controlled based on the internal control signal from the control means. Power is supplied from the power supply line through the switching means that is connected to the power supply line and is in the conductive state when receiving the activation signal from the judging means, and is in the non-conducting state when not receiving the activation signal from the judging means. Since there is no power supply to the control means and data output buffer when the control card is not selected, there is an effect that power consumption can be reduced. It is intended.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional control card.

[Explanation of symbols]

 2 power supply line 3 judging means 5 timing circuit constituting control means 6 combinational circuit constituting control means 7 storage means 8 data input / output buffer 9 switching means

Claims (1)

[Claims] 1. A judging means which is connected to a power supply line and receives a power supply, receives a card selection signal, and outputs an activation signal when judging that the received card selection signal is a signal which has selected itself. One end is connected to a power supply line and is in a conductive state when receiving an activation signal from the determining means, and is in a non-conducting state when not receiving an activation signal from the determining means. Control means connected to the end and supplied with power from the power supply line through the switching means, activated by receiving the activation signal from the determination means, and outputting an internal control signal. A storage unit that is controlled based on an internal control signal and stores data, is connected to the other end of the switching unit, and is connected via the switching unit. Then, the control card is provided with a data output buffer for receiving the power supply from the power supply line and outputting the data read from the storage means.