JPH0719168Y2 - Photodiode array mounting device - Google Patents
Photodiode array mounting deviceInfo
- Publication number
- JPH0719168Y2 JPH0719168Y2 JP9034887U JP9034887U JPH0719168Y2 JP H0719168 Y2 JPH0719168 Y2 JP H0719168Y2 JP 9034887 U JP9034887 U JP 9034887U JP 9034887 U JP9034887 U JP 9034887U JP H0719168 Y2 JPH0719168 Y2 JP H0719168Y2
- Authority
- JP
- Japan
- Prior art keywords
- guide pin
- photodiode array
- chip
- pda
- mounting device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Optical Transform (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Die Bonding (AREA)
- Analogue/Digital Conversion (AREA)
- Transmission And Conversion Of Sensor Element Output (AREA)
Description
【考案の詳細な説明】 ［産業上の利用分野］ 本考案は、光学式エンコーダのスリットを通過した光を
検出するフォトダイオードアレイ（以下、PDAとする）
を位置決めして取付ける装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention is a photodiode array (hereinafter, referred to as PDA) for detecting light passing through a slit of an optical encoder.
The present invention relates to a device for positioning and mounting.
［従来の技術］ 光学式エンコーダのスリットを通過した光を検出するPD
Aでは、その取付位置が精密に位置決めされていない
と、スリットの通過光が当たらなくなる。[Prior Art] PD that detects light that has passed through the slit of an optical encoder
In A, if the mounting position is not precisely positioned, the light passing through the slit will not hit.
従来、PDAの位置決め方法としては、例えば第５図に示
すように、配線板１に接着したPDAの集積回路（以下、I
Cとする）のチップ２にマークM1を付けるとともに、位
置固定された基板３にもマークM2を付け、顕微鏡により
M1とM2のマークを手作業で合せることによって位置決め
を行うようにしたものがあった。Conventionally, as a PDA positioning method, for example, as shown in FIG. 5, an integrated circuit of a PDA (hereinafter referred to as I
Mark M 1 is attached to chip 2 (referred to as C), and mark M 2 is also attached to substrate 3 whose position is fixed.
In some cases, positioning was performed by manually aligning the M 1 and M 2 marks.
［考案が解決しようとする問題点］ しかし、このような位置決め方法では、位置決めマーク
M2の距離が例えば40mmと大きく顕微鏡の一視野に入らな
い。このため顕微鏡を動かして右と左のマークを合せな
ければならない。また、チップ２と基板３の高さが異な
るため、顕微鏡の焦点合せが面倒である。[Problems to be solved by the invention] However, in such a positioning method, the positioning mark
The distance of M 2 is as large as 40 mm, for example, and it does not fit into one field of the microscope. For this reason, the microscope must be moved to align the right and left marks. Moreover, since the heights of the chip 2 and the substrate 3 are different, focusing of the microscope is troublesome.
このような位置合せは人間の手作業に依存し、きわめて
低能率であるという問題点があった。Such alignment depends on human manual work and is extremely inefficient.
本考案はこのような問題点を除去するためになされたも
のであり、容易にPDAを構造材に精密実装できるPDAの取
付装置を実現することを目的とする。The present invention has been made in order to eliminate such problems, and an object thereof is to realize a PDA mounting device that can easily and accurately mount a PDA on a structural material.
［問題点を解決するための手段］ 本考案は、 光学式エンコーダのスリットを通過した光を検出するフ
ォトダイオードアレイを位置決めして取付ける装置にお
いて、 フォトダイオードアレイのチップが接着されていて、フ
ォトダイオードアレイに対して位置決めされたガイドピ
ン穴が形成されたチップ取付部材と、 位置決めされたガイドピンが立てられていて、このガイ
ドピンが前記ガイドピン穴に嵌合されることによってチ
ップ取付部材が位置決めされて取付けられる構造材、 を具備したことを特徴とするフォトダイオードアレイの
取付け装置である。[Means for Solving Problems] The present invention relates to a device for positioning and mounting a photodiode array for detecting light passing through a slit of an optical encoder, in which a chip of the photodiode array is bonded, The chip mounting member with the guide pin hole positioned with respect to the array and the positioned guide pin are set up. The chip mounting member is positioned by fitting the guide pin into the guide pin hole. A mounting device for a photodiode array, comprising:
［実施例］ 以下、図面を用いて本考案を説明する。[Embodiment] The present invention will be described below with reference to the drawings.
第１図は本考案にかかるフォトダイオードアレイの取付
装置の一実施例の構成分解図である。第１図で第５図と
同一のものは同一符号を付ける。FIG. 1 is an exploded view of an embodiment of a photodiode array mounting device according to the present invention. 1 that are the same as those in FIG. 5 are assigned the same reference numerals.
図で、４はPDAのチップ取付部材としての配線板であ
り、PDAのICチップ２が接着されている。この配線板４
にはチップ２に対して精密に位置決めされたガイドピン
穴５が形成されている。ガイドピン穴５の穴明けは、例
えば超音波研削、エッチング等により、チップ２に付け
られたマークＭを目印にして行う。In the figure, 4 is a wiring board as a chip mounting member of the PDA, to which the IC chip 2 of the PDA is bonded. This wiring board 4
Is formed with a guide pin hole 5 precisely positioned with respect to the chip 2. The guide pin hole 5 is drilled by, for example, ultrasonic grinding, etching, or the like, using the mark M attached to the chip 2 as a mark.
６は光学式エンコーダの固定部になっている構造材であ
り、精密に位置決めされたガイドピン穴７にガイドピン
８が立てられる。ガイドピン８はガイドピン穴７に嵌
合、接着等により固定されている。Reference numeral 6 denotes a structural material that serves as a fixing portion of the optical encoder, and guide pins 8 are set up in guide pin holes 7 that are precisely positioned. The guide pin 8 is fixed to the guide pin hole 7 by fitting, bonding or the like.
立てられたガイドピン８が配線板４のガイドピン穴５に
嵌合されることによって配線板４は構造材６に精密に位
置決めされて固定される。The standing guide pin 8 is fitted into the guide pin hole 5 of the wiring board 4, whereby the wiring board 4 is precisely positioned and fixed to the structural member 6.
超音波研削、エッチング等により、ガイドピン穴５と７
の位置精度を例えば±10μｍ以内にすることができ、こ
れによってチップ２は±20μｍ以内の精度で位置決めさ
れる。Guide pin holes 5 and 7 by ultrasonic grinding, etching, etc.
Can be positioned within ± 10 μm, so that the chip 2 can be positioned with an accuracy within ± 20 μm.
第２図は本考案にかかるフォトダイオードの取付装置の
他の実施例の製造工程図である。FIG. 2 is a manufacturing process diagram of another embodiment of the photodiode mounting device according to the present invention.
第１図の取付装置ではPDAはチップ状態になってからチ
ップ取付部材に接着されるが、第２図の取付装置では、
PDAがウエハ状態にあるときにチップ取付部材に接着さ
れる。In the mounting device shown in FIG. 1, the PDA is bonded to the chip mounting member after it is in the chip state, but in the mounting device shown in FIG.
The PDA is bonded to the chip mounting member when it is in the wafer state.
以下、第２図に従って取付装置の製造工程を説明する。The manufacturing process of the mounting device will be described below with reference to FIG.
工程A1はチップ取付部材としてのウエハ接合板９の製造
工程である。この工程では、ウエハ接合板９にウエハと
接合するときの接合位置決め用穴10と、ウエハの各チッ
プ毎に設けられていてチップのPDAに対して位置決めさ
れたガイドピン穴11を形成する。これらの穴同志は所定
の相対的位置関係をもつ。ウエハ接合板９としては例え
ばセラミック板が用いられる。穴明けは超音波研削等に
より行う。Step A 1 is a step of manufacturing the wafer bonding plate 9 as a chip mounting member. In this step, a bonding positioning hole 10 for bonding with the wafer and a guide pin hole 11 provided for each chip of the wafer and positioned with respect to the PDA of the chip are formed in the wafer bonding plate 9. These holes have a predetermined relative positional relationship. As the wafer bonding plate 9, for example, a ceramic plate is used. Drilling is performed by ultrasonic grinding or the like.
工程A2はウエハプロセスである。この工程では、ウエハ
12に明ける穴13が識別できるようにウエハ12の表面に現
像を形成し、この現像をもとに穴13を明ける。穴明け
は、超音波研削、エッチング等により行う。この穴13は
ウエハ12をウエハ接合板９に接合するときに、ウエハ12
を位置合せするための穴である。Step A 2 is a wafer process. In this process, the wafer
A development is formed on the surface of the wafer 12 so that the holes 13 drilled in the holes 12 can be identified, and the holes 13 are drilled based on this development. Drilling is performed by ultrasonic grinding, etching or the like. The holes 13 are provided when the wafer 12 is bonded to the wafer bonding plate 9.
It is a hole for aligning.
工程A1とA2の後に、工程A3で接合位置決め用穴10と穴13
を合せてウエハ接合板９とウエハ12を接着する。After steps A 1 and A 2 , in step A 3 the joint positioning hole 10 and hole 13
Then, the wafer bonding plate 9 and the wafer 12 are bonded together.
その後、工程A4でダイシングをしてウエハ12をチップ14
に分割する。Then, in step A 4 , the wafer 12 is diced into chips 14 by dicing.
Split into.
工程A5は構造材６にガイドピン８を立てる工程である。
ガイドピン８は構造材６に対して精密に位置決めされて
いる。Step A 5 is a step of erecting the guide pin 8 on the structural material 6.
The guide pin 8 is precisely positioned with respect to the structural member 6.
工程A4とA5の後に、工程A6でガイドピン穴11にガイドピ
ン８を嵌め込んでチップ14を構造材６に接着する。Ｗは
配線用のワイヤである。After steps A 4 and A 5 , in step A 6 , the guide pin 8 is fitted into the guide pin hole 11 to bond the chip 14 to the structural member 6. W is a wire for wiring.
これによって、チップ14は構造材６に精密に位置決めさ
れた状態で固定される。なお、ウエハ工程で、穴13とPD
Aのパターンの現像の形成は同時に行ってもよい。As a result, the chip 14 is fixed to the structural member 6 while being precisely positioned. In the wafer process, the holes 13 and PD
The formation of the pattern A development may be performed simultaneously.
なお、配線板４がガラスエポキシ樹脂で構成されている
場合は、配線板４に明ける穴に良好な位置精度が得られ
ないため、第３図に示すように、配線板４には大まかな
位置精度の穴15を明け、この配線板４に精密穴加工がで
きる金属板16を接着し、この金属板16に精密に位置決め
されたガイドピン穴17を設けた構成にしてもよい。If the wiring board 4 is made of glass epoxy resin, good positioning accuracy cannot be obtained for the holes formed in the wiring board 4, and therefore, as shown in FIG. It is also possible to form a hole 15 of accuracy, adhere a metal plate 16 capable of precision hole processing to this wiring board 4, and provide a guide pin hole 17 precisely positioned in this metal plate 16.
また、第４図に示すように、PDAのチップ２をパッケー
ジ18に入れ、このパッケージ18にPDAに対して精密に位
置決めされたガイドピン穴19を明けた構成にしてもよ
い。Alternatively, as shown in FIG. 4, the PDA chip 2 may be placed in a package 18 and a guide pin hole 19 precisely positioned with respect to the PDA may be formed in the package 18.
［効果］ 本考案によれば、PDAが取付けられた部材にはPDAに対し
て精密に位置決めされたガイドピン穴が設けられ、また
PDAが装着される構造材にも精密に位置決めされたガイ
ドピンが立てられているため、これらを嵌め合せること
により、容易にPDAを構造材に精密実装できる。[Effect] According to the present invention, the member to which the PDA is attached is provided with the guide pin hole precisely positioned with respect to the PDA, and
Since the precisely positioned guide pins are erected on the structural material on which the PDA is mounted, the PDA can be easily and precisely mounted on the structural material by fitting them together.
第１図は本考案にかかるフォトダイオードアレイの取付
装置の一実施例の構成図、第２図は本考案にかかるフォ
トダイオードアレイの取付装置の他の実施例の製造工程
図、第３図及び第４図は本考案にかかるフォトダイオー
ドアレイの取付装置の他の実施例の構成図、第５図は従
来におけるフォトダイオードアレイの位置決め方法の一
例を示した図である。 2,14……チップ、4,9……チップ取付部材、5,7,11,17,1
9……ガイドピン穴、８……ガイドピン。FIG. 1 is a configuration diagram of an embodiment of a photodiode array mounting device according to the present invention, and FIG. 2 is a manufacturing process diagram of another embodiment of a photodiode array mounting device according to the present invention, FIG. FIG. 4 is a block diagram of another embodiment of a photodiode array mounting device according to the present invention, and FIG. 5 is a diagram showing an example of a conventional photodiode array positioning method. 2,14 …… Chip, 4,9 …… Chip mounting member, 5,7,11,17,1
9 …… Guide pin hole, 8 …… Guide pin.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/148 31/10 Ｈ０３Ｍ 1/24 Ｈ０１Ｌ 31/10 Ｚ (72)考案者 藤本 士郎 東京都武蔵野市中町２丁目９番32号 横河 電機株式会社内 (72)考案者 山県 通昭 東京都武蔵野市中町２丁目９番32号 横河 電機株式会社内 (72)考案者 斉藤 俊夫 東京都武蔵野市中町２丁目９番32号 横河 電機株式会社内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Office reference number FI Technical display location H01L 27/148 31/10 H03M 1/24 H01L 31/10 Z (72) Inventor Shirou Fujimoto Tokyo 2-9-32 Nakamachi, Musashino City Yokogawa Electric Co., Ltd. (72) Inventor Toshoaki Yama Prefecture 2-9-32 Nakamachi, Musashino City Yokogawa Electric Co., Ltd. (72) Inventor Toshio Saito Musashino, Tokyo 2-9-32 Ichinakamachi Yokogawa Electric Co., Ltd.
Claims (1)
を検出するフォトダイオードアレイを位置決めして取付
ける装置において、 フォトダイオードアレイのチップが接着されていて、フ
ォトダイオードアレイに対して位置決めされたガイドピ
ン穴が形成されたチップ取付部材と、 位置決めされたガイドピンが立てられていて、このガイ
ドピンが前記ガイドピン穴に嵌合されることによってチ
ップ取付部材が位置決めされて取付けられる構造材、 を具備したことを特徴とするフォトダイオードアレイの
取付装置。1. A device for positioning and mounting a photodiode array for detecting light passing through a slit of an optical encoder, wherein a chip of the photodiode array is adhered, and the guide pin is positioned with respect to the photodiode array. A chip mounting member having a hole formed therein, a positioned guide pin standing upright, and a structural member on which the chip mounting member is positioned and mounted by fitting the guide pin into the guide pin hole. A device for mounting a photodiode array, characterized in that
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9034887U JPH0719168Y2 (en) | 1987-06-12 | 1987-06-12 | Photodiode array mounting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9034887U JPH0719168Y2 (en) | 1987-06-12 | 1987-06-12 | Photodiode array mounting device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63200337U JPS63200337U (en) | 1988-12-23 |
| JPH0719168Y2 true JPH0719168Y2 (en) | 1995-05-01 |
Family
ID=30950124
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9034887U Expired - Lifetime JPH0719168Y2 (en) | 1987-06-12 | 1987-06-12 | Photodiode array mounting device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0719168Y2 (en) |
-
1987
- 1987-06-12 JP JP9034887U patent/JPH0719168Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63200337U (en) | 1988-12-23 |
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