JPH07191640A - Signal line driving circuit of liquid crystal display device - Google Patents

Abstract

PURPOSE:To use a high-speed transistor(TR) for a switch by connecting two switches in series and connecting their connection point to a fixed potential through another switch. CONSTITUTION:When a signal is sampled, the series-connected switches 108 and 104 are turned ON with the output of an inverter type buffer 107 to hold the potential of a video signal line 103 in a holding capacitor 116, but when the sampling is not performed, the switches 108 and 104 are turned OFF and the switch 110 is turned ON instead. This switch 110 is connected to a constant voltage line 104, so the connection point between the switches 108 and 104 is held at the same potential with the constant voltage line 104. Assuming that the potential applied to the constant voltage line is equal to the potential of a counter electrode, voltages applied to the switches 108 and 104 are reduced to <=1/2 as large as the amplitude of a video signal. Similarly, voltages applied to switches 111 and 112 of a transfer circuit are also reducible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for an active matrix type liquid crystal display device, and more particularly to a signal line drive circuit.

[0002]

2. Description of the Related Art FIG. 2 shows an example of an active matrix type analog gradation line sequential drive liquid crystal display device. The active matrix type liquid crystal display device can be roughly divided into three parts: a pixel matrix part, a signal line driving circuit, and a scanning line driving circuit. The operation will be described below with reference to the drawings.

In the pixel matrix, signal lines and scanning lines are arranged in a matrix, and pixel TFTs are arranged at the intersections thereof.
The pixel TFT has a gate connected to the scanning line, a source connected to the signal line, and a drain connected to the pixel electrode. Further, in general, the liquid crystal capacitance between the pixel electrode and the counter electrode cannot have a large value, so that a storage capacitor for holding charges is arranged near the pixel electrode. When a voltage exceeding the threshold voltage of the TFT is applied to the scanning line and the TFT turns on, TF
The drain and source of T are short-circuited, the voltage of the signal line is applied to the pixel electrode, and the liquid crystal and the storage capacitor are charged. Then, when the TFT is turned off, the drain is opened, and the electric charge stored in the liquid crystal and the storage capacitor is then transferred to TF.
Hold until T turns on.

FIG. 3 shows an example of the signal line drive circuit. The signal line driver circuit includes a shift register circuit, a sampling circuit, a transfer circuit, and an analog buffer circuit. In the case of analog gradation, the gradation signal input to the signal line drive circuit is a video signal that is continuous in time, and when the liquid crystal is normal white, the display becomes closer to black display as the absolute value of the voltage increases. To be done. A start pulse synchronized with the video signal is input to the input terminal 302 of the shift register and sequentially shifted by a clock pulse. The output of the shift register is input to the sampling circuit through the inverter type buffer circuits 308 to 313,

As shown in FIG. 4, the sampling circuit has N
Switches 314-31 called transmission gates that combine channel and P channel TFTs
6 and holding capacitors 317 to 319, the transmission gate is controlled to be turned on and off by the buffer circuit, and in the on state, the video signal line and the holding capacitor 3 are held.
17 to 319 are short-circuited, and an electric charge is stored in the storage capacitor. When the start pulse passes through the shift register, the output of the buffer circuit is inverted and the switch is turned off. The charge of the storage capacitor is held as it is, and the potential is held until the switch is turned on next time. The transfer signal is input from the transfer signal input terminal 304 until the sampling for one line is completed and the next sampling is started, whereby the switches 320 to 32
2 is turned on, holding capacitors 317 to 319 and holding capacitor 3
23 to 325 are short-circuited, and the storage capacitors 323 to 325
Potential is transmitted to. The switches 320 to 322 are also composed of transmission gates like the switches 314 to 316. At this time, if the value of the storage capacitors 323 to 325 is sufficiently smaller than the value of the storage capacitors 317 to 319, the potential change due to the short-circuiting of the storage capacitors is small. When the switches 320 to 322 are turned off, the storage capacitors 323 to 32
The potential is held at 5.

An analog buffer is connected to the storage capacitors 323 to 325, and the signal line is driven through the analog buffer. The analog buffer circuit is necessary to drive the signal line without affecting the potential of the storage capacitor. Fifth
An example of the scan line driver circuit is shown in the drawing. The scanning line driving circuit is composed of a shift register and a NAND circuit inverter type buffer, inputs a start pulse synchronized with a vertical synchronizing signal and a clock synchronized with a horizontal synchronizing signal, and sequentially drives the scanning lines.

[0007]

In the conventional signal line drive circuit, as described above, the analog switch such as the transmission gate is used in the sampling circuit.
This sampling circuit or the like is generally required to have high speed, and the TFT to be used is required to have performance such as high mobility and small capacity. However, these characteristics often conflict with the characteristics such as the withstand voltage of the TFT, so that it is necessary to sacrifice the high speed in order to secure the withstand voltage. FIG. 6 shows a sampling circuit extracted, and FIG. 7 (A).
(B) and (C) show the voltage waveforms of the gradation signal input terminal 603, the storage capacitor connection terminal 604, and the control terminal 605. The liquid crystal has a problem that its characteristics are deteriorated when a DC voltage is applied for a long time, and an AC waveform as shown in FIG.

In the example of FIG. 7, an AC signal of 14 Vpp is applied. A pulse signal is applied to the control terminal 605 as shown in (C), sampling is performed when the pulse is high, and the voltage at that time is applied to the storage capacitor 602.
When the pulse signal goes low, the switch 601 is opened and the electric charge stored in the storage capacitor 602 is maintained until the next sampling is performed. Therefore, a voltage equal to the amplitude of the AC signal may be applied between the gradation signal input terminal 603 and the storage capacitor connection terminal 604, and therefore, the TFTs forming the switch must sufficiently withstand the voltage. . Therefore, as described above, there is a problem that the high speed is sacrificed.

[0009]

In the present invention, as a sampling or selection means, two switches are connected in series, and the connection point is connected to a fixed potential via another switch.

[0010]

FIG. 8 is a schematic view of the present invention. During sampling, switches 801 and 802 are turned on at the same time,
The potential of the gradation signal input terminal 806 and the storage capacitor connection terminal 80
The potentials of 8 become equal, and a gradation signal is applied to the storage capacitor 804. Switches 801 and 80 when not sampling
2 turns off and switch 803 turns on. Since the switch 802 is opened, the storage capacitor 804 maintains the charge until the next sampling. Also switch 80
3 is connected to the constant voltage terminal 807, the switch 8
The connection point of 01 and 802 is fixed to the potential of the terminal 807. Here, if the potential of the terminal 807 is set to be equal to the potential of the counter electrode, the voltage applied to the switches 801 and 802 will be of the AC amplitude when the AC signal as shown in FIG. It can be half, 7V.

[0011]

FIG. 1 shows a first embodiment of the present invention. It is an example of a case where the present invention is applied to a sampling circuit of a signal line drive circuit. At the time of sampling, the switches 108 and 109 are turned on by the output of the inverter buffer 107, and the potential of the video signal line 103 is held in the storage capacitor 116. At the time of non-sampling, the switches 108 and 109 are held.
9 is turned off and switch 110 is turned on instead. Since the switch 110 is connected to the constant voltage line 104, the connection point between the switch 108 and the switch 109 becomes equal to the potential of the constant voltage line 104. If the potential applied to the constant voltage line is the potential of the counter electrode, the switch 108,
The voltage applied to 109 can be half the amplitude of the video signal or less. Similarly, it is possible to reduce the applied voltage to the switches 111 and 112 of the transfer circuit.

FIG. 9 shows an example in which the present invention is applied to a gradation voltage signal selection circuit of a 4-gradation digital gradation signal line drive circuit. In the digital gradation signal line drive circuit, the switch circuit has a role of selecting any of the gradation voltage lines 904, 905, 906, and 907 and short-circuiting the signal line 925. Here, when selecting the gradation signal line 904, the switches 913, 914, 918, 921, 924 are selected.
Is turned on and the switches 915, 916, 917, 91 are turned on.
9, 920, 922 and 923 are turned off. Adjust the voltage of the constant voltage terminal 908 to the grayscale voltage lines 904, 905, 906,
If it is set to an appropriate voltage between the voltages that 07 can take, the switches 916, 917, 919, and 9 that are turned off.
It is possible to reduce the voltage applied across 20, 922, 923.

[0013]

As described above, the present invention has an effect that a high-speed transistor can be used in the switch because the voltage applied to the TFT forming the switch is reduced and high withstand voltage is not required.

[Brief description of drawings]

FIG. 1 shows an analog grayscale signal line drive circuit using the present invention.

FIG. 2 shows a conventional active matrix type liquid crystal display device.

FIG. 3 shows a block diagram of a conventional signal line drive circuit.

FIG. 4 shows an equivalent circuit of a transmission gate.

FIG. 5 shows a block diagram of a scan line driver circuit.

FIG. 6 shows a conceptual diagram of a conventional sampling circuit.

FIG. 7 shows a voltage waveform of a conventional sampling circuit.

FIG. 8 shows a conceptual diagram of a sampling circuit of the present invention.

FIG. 9 shows a digital gradation signal line drive circuit using the present invention.

[Explanation of symbols]

Clock input terminal: 101 Start pulse input terminal: 102 Video signal input terminal: 103 Constant voltage input terminal: 104 Transfer signal input terminal: 105 Signal line connection terminal: 118 Inverter type buffer: 106, 107, 114,
115 switch: 108 to 113 holding capacity: 116, 117 pixel matrix: 200 signal line: 201 to 203 scanning line: 204 to 206 TFT: 207 to 210 liquid crystal: 211 to 214 holding capacity: 215 to 218 clock input terminal: 301 start Pulse input terminal: 302 Video signal input terminal: 303 Transfer signal input terminal: 304 Signal line connection terminal: 305-307 Inverter type buffer: 308-313 Switch: 314-316 320-322 Storage capacity: 317-319: 323-325 Control terminal: 401 Input terminal: 402 Output terminal: 403 Nch transistor: 404 Pch transistor: 405 Inverter: 406 Clock input terminal: 501 Start pulse input terminal: 502 NAND: 503, 04 Inverter type buffer: 505, 506 Scan line connection terminal: 507, 508 Switch: 601 Holding capacity connection terminal: 604 Gradation signal input terminal: 603 Control signal input terminal: 605 Holding capacity: 602 Gradation signal waveform (A) Holding capacity voltage Waveform (B) Control voltage waveform (C) Switch: 801, 802, 803 Holding capacitor connecting terminal: 808 Gradation signal input terminal: 806 Control signal input terminal: 809 Holding capacitor: 804 Constant voltage input terminal: 807 Inverter: 805 Clock input Terminal: 901 Start pulse input terminal: 902, 903 Gradation signal input terminal: 904 to 907 Constant voltage input terminal: 908 Inverter: 909 to 912 Switch: 913 to 924 Signal line output terminal: 925

Claims (1)

[Claims] 1. In a signal line drive circuit of an active matrix type liquid crystal display device having means for sampling or selecting an input grayscale voltage signal, first and second serially connected means are provided as the means for sampling or selecting. A signal line drive circuit for a liquid crystal display device, comprising a switch and a third switch having a connection point of the first and second switches and a fixed voltage terminal at both ends.