JP3637075B2 - Signal line drive circuit for active matrix liquid crystal display device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a driver circuit for an active matrix liquid crystal display device, and more particularly to a signal line driver circuit.
[0002]
[Prior art]
Figure 2 is an example of a liquid crystal display device of active matrix type analog gradation line sequential driving. An active matrix type liquid crystal display device can be roughly divided into a pixel matrix portion, a signal line driving circuit, and a scanning line driving circuit. The operation will be described below with reference to the drawings.
[0003]
In the pixel matrix, signal lines and scanning lines are arranged in a matrix, and pixel TFTs are arranged at intersections thereof. The gates of the pixel TFTs are connected to the scanning lines, the sources are connected to the signal lines, and the drains are connected to the pixel electrodes. In general, since the liquid crystal capacitance between the pixel electrode and the counter electrode cannot take a large value, a storage capacitor for holding charges is disposed in the vicinity of the pixel electrode. When a voltage exceeding the threshold voltage of the TFT is applied to the scanning line and the TFT is turned on, the drain and source of the TFT are short-circuited, and the voltage of the signal line is applied to the pixel electrode to charge the liquid crystal and the storage capacitor. When the TFT is turned off, the drain is opened, and the charge stored in the liquid crystal and the storage capacitor is held until the TFT is turned on next time.
[0004]
FIG. 3 shows an example of a signal line driver circuit. The signal line driver circuit includes a shift register circuit, a sampling circuit, a transfer circuit, and an analog buffer circuit. For analog gradation, the gradation signal input to the signal line driver circuit is time-continuous video signal is used, the display liquid crystal is the larger absolute value when the voltage of the normal white to approach black display Is set. A start pulse synchronized with the video signal is input to the input terminal 302 to the shift register and sequentially shifted by the clock pulse. The output of the shift register is input to the sampling circuit via the inverter type buffer circuits 308 to 313.
[0005]
As shown in FIG. 4, the sampling circuit is composed of switches 314 to 316 and holding capacitors 317 to 319 called transmission gates in which N-channel and P-channel TFTs are combined. The transmission gate is turned on and off by the buffer circuit. In the ON state, the video signal line and the storage capacitors 317 to 319 are short-circuited, and charges are stored in the storage capacitors. When the start pulse passes through the shift register, the output of the buffer circuit is inverted and the switch is turned off. The charge in the storage capacitor is held as it is, and the potential is held until the next time the switch is turned on. The transfer signal is input from the transfer signal input terminal 304 between the end of sampling for one line and the start of the next sampling. As a result, the switches 320 to 322 are turned on and the holding capacitors 317 to 319 are turned on. The storage capacitors 323 to 325 are short-circuited, and a potential is transmitted to the storage capacitors 323 to 325. Similarly to the switches 314 to 316, the switches 320 to 322 are configured by transmission gates. At this time, if the value of the storage capacitors 323 to 325 is sufficiently smaller than the value of the storage capacitors 317 to 319, the potential change due to the short-circuit of the storage capacitors is small. When the switches 320 to 322 are turned off, the potential is held in the holding capacitors 323 to 325.
[0006]
An analog buffer is connected to the storage capacitors 323 to 325, and the signal line is driven through the analog buffer. The analog buffer circuit is necessary for driving the signal line without affecting the potential of the storage capacitor. FIG. 5 shows an example of the scanning line driving circuit. The scanning line driving circuit is constituted by a shift register and a NAND circuit inverter type buffer, and inputs a start pulse synchronized with a vertical synchronizing signal and a clock synchronized with a horizontal synchronizing signal, and sequentially drives the scanning lines.
[0007]
[Problems to be solved by the invention]
In the conventional signal line driving circuit, the analog switch such as a transmission gate is used in the sampling circuit as described above. However, the sampling circuit or the like generally requires high speed, and the TFT used has high mobility and small size. Performance such as capacity was required. However, these characteristics often contradict the characteristics such as the breakdown voltage of the TFT, and when attempting to ensure the breakdown voltage, high speed must be sacrificed.
Figure 6 are those extracted sampling circuit, FIG. 7 (A) (B) (C ) in the gradation signal input terminal 603, the holding capacitor connection 604, indicating a voltage waveform of the control terminal 605. The liquid crystal has a problem that its characteristics deteriorate when a DC voltage is applied for a long time, and an AC waveform as shown in FIG.
[0008]
In the example of FIG. 7, an AC signal of 14 Vpp is applied. A pulse signal is applied to the control terminal 605 as shown in (C), sampling is performed when the pulse is high, and the voltage at that time is applied to the storage capacitor 602. When the pulse signal goes low, the switch 601 is opened, and the charge stored in the storage capacitor 602 is maintained until the next sampling is performed. Therefore, between the gradation signal input terminal 603 and the storage capacitor connection terminal 604 may receive the voltage of as much as the amplitude of the AC signal is applied, therefore, if TFT constituting the switch is sufficiently withstand voltage thereof Don't be. Therefore, as described above, there has been a problem of sacrificing high speed.
[0009]
[Means for Solving the Problems]
The present invention relates to a signal line driving circuit for driving an active matrix liquid crystal display device.
The signal line driving circuit has a sampling circuit that samples a gradation signal applied from a gradation signal input terminal and applies the gradation signal to a signal line,
The sampling circuit includes a storage capacitor, a storage capacitor connection terminal connected to the storage capacitor, a first switch and a second switch connected in series between the storage capacitor connection terminal and the gradation signal input terminal. And a constant voltage input terminal maintained at a fixed potential, and a third switch connected between the connection point of the first switch and the second switch and the constant voltage input terminal. And
The first switch is means for controlling connection / disconnection between the gradation signal input terminal and the second switch, and when turned on, the second switch passes through the connection point through the gradation signal input terminal. And the grayscale signal input terminal and the second switch are in a non-conductive state when turned off,
The second switch is means for controlling connection / disconnection between the first switch and the signal line, and when the switch is on, the first switch and the signal line are in a conductive state, and when the switch is off, the first switch The switch and the signal line in a non-conductive state,
The third switch is means for controlling connection / disconnection between the constant voltage input terminal maintained at the fixed potential and the connection point;
The constant voltage input terminal is kept at a fixed potential equal to the potential of the counter electrode,
At the time of sampling, the first switch and the second switch are simultaneously turned on, the potential of the gradation signal input terminal is equal to the potential of the storage capacitor connection terminal, and the gradation signal is supplied to the storage capacitor. Is applied,
At the time of non-sampling, the first switch and the second switch are turned off simultaneously, and the third switch is turned on, so that the storage capacitor maintains a charge until the next sampling. The connection point is connected to the constant voltage input terminal.
“Retention capacity”, “first switch”, “second switch”, and “third switch” correspond to “116”, “108”, “109”, and “110” in FIG. 1, respectively. To do.
[0010]
[Action]
FIG. 8 is a schematic diagram of the present invention. During sampling, switches 801 and 802 are turned on at the same time, equalizes the potential of the holding capacitor connection 808 of the gradation signal input terminal 806, a storage capacitor 804 bilevel signal is applied. At the time of non-sampling, the switches 801 and 802 are turned off and the switch 803 is turned on. Since the switch 802 is opened, the storage capacitor 804 maintains the charge until the next sampling. In addition, since the switch 803 is connected to the constant voltage terminal 807, the connection point of the switches 801 and 802 is fixed to the potential of the terminal 807. Here, if the potential of the terminal 807 is set to be equal to the potential of the counter electrode, when an AC signal is applied as shown in FIG. 7, the voltage applied to the switches 801 and 802 is changed to the AC amplitude. It can be half 7V.
[0011]
【Example】
FIG. 1 shows a first embodiment of the present invention. This is an example when the present invention is applied to a sampling circuit of a signal line driver circuit. At the time of sampling, the switches 108 and 109 are turned on by the output of the inverter buffer 107, and the potential of the video signal line 103 is held in the holding capacitor 116. At the time of non-sampling, the switches 108 and 109 are turned off, and the switch 110 is turned on instead. Become. Since the switch 110 is connected to the constant voltage line 104, the connection point between the switch 108 and the switch 109 is equal to the potential of the constant voltage line 104. Here, if the potential applied to the constant voltage line is the potential of the counter electrode, the voltage applied to the switches 108 and 109 can be reduced to half or less of the amplitude of the video signal. Similarly, the applied voltage can be reduced for the switches 111 and 112 of the transfer circuit.
[0012]
Figure 9 is a reference example showing a gradation voltage signal selecting circuits of the signal line driving circuit of the digital gradation of 4 grayscale. In the signal line driving circuit of the digital tone has a role switch circuit selects one of the gradation voltage lines 904,905,906,907, short to the signal line 925. Here, when selecting a gradation signal line 904, the switch 913,914,918,921,924 are turned on, the switch 915,916,917,919,920,922,923 is turned off. By setting the proper voltage between Possible voltage of the voltage gradation voltage lines 904,905,906,907 a constant voltage terminal 908, the switch is off 916,917,919,920,922, The voltage applied to both ends of 923 can be reduced.
[0013]
【The invention's effect】
As described above, the present invention reduces the voltage applied to the TFT constituting the switch and does not require high withstand voltage, so that there is an effect that a high-speed transistor can be used in the switch.
[Brief description of the drawings]
1 shows an analog tone signal line driver circuit using the present invention.
FIG. 2 shows a conventional active matrix liquid crystal display device.
FIG. 3 is a block diagram of a conventional signal line driving circuit.
FIG. 4 shows an equivalent circuit of a transmission gate.
FIG. 5 is a block diagram of a scanning line driving circuit.
FIG. 6 is a conceptual diagram of a conventional sampling circuit.
FIG. 7 shows a voltage waveform of a conventional sampling circuit.
FIG. 8 shows a conceptual diagram of a sampling circuit of the present invention.
Figure 9 shows a digital tone signal line driver circuit.
[Explanation of symbols]
Clock input terminal: 101
Start pulse input terminal: 102
Video signal input terminal: 103
Constant voltage input terminal: 104
Transfer signal input terminal: 105
Signal line connection terminal: 118
Inverter type buffer: 106, 107, 114, 115
Switch: 108-113
Holding capacity: 116, 117
Pixel matrix: 200
Signal line: 201-203
Scan line: 204-206
TFT: 207 to 210
Liquid crystal: 211-214
Holding capacity: 215 to 218
Clock input terminal: 301
Start pulse input terminal: 302
Video signal input terminal: 303
Transfer signal input terminal: 304
Signal line connection terminal: 305 to 307
Inverter type buffer: 308-313
Switch: 314 to 316
320-322
Holding capacity: 317 to 319
: 323-325
Control terminal: 401
Input terminal: 402
Output terminal: 403
Nch transistor: 404
Pch transistor: 405
Inverter: 406
Clock input terminal: 501
Start pulse input terminal: 502
NAND: 503, 504
Inverter type buffer: 505, 506
Scan line connection terminals: 507, 508
Switch: 601
Holding capacitor connection terminal: 604
Gradation signal input terminal: 603
Control signal input terminal: 605
Holding capacity: 602
Gradation signal waveform (A)
Retention capacitance voltage waveform (B)
Control voltage waveform (C)
Switch: 801, 802, 803
Holding capacitor connection terminal: 808
Gradation signal input terminal: 806
Control signal input terminal: 809
Holding capacity: 804
Constant voltage input terminal: 807
Inverter: 805
Clock input terminal: 901
Start pulse input terminal: 902, 903
Gradation signal input terminal: 904-907
Constant voltage input terminal: 908
Inverter: 909-912
Switch: 913-924
Signal line output terminal: 925

Claims (2)

In a signal line driving circuit for driving an active matrix liquid crystal display device,
The signal line driving circuit has a sampling circuit that samples a gradation signal applied from a gradation signal input terminal and applies the gradation signal to a signal line,
The sampling circuit includes a storage capacitor, a storage capacitor connection terminal connected to the storage capacitor, a first switch and a second switch connected in series between the storage capacitor connection terminal and the gradation signal input terminal. And a constant voltage input terminal maintained at a fixed potential, and a third switch connected between the connection point of the first switch and the second switch and the constant voltage input terminal. And
The first switch is means for controlling connection / disconnection between the gradation signal input terminal and the second switch, and when turned on, the second switch passes through the connection point through the gradation signal input terminal. And the grayscale signal input terminal and the second switch are in a non-conductive state when turned off.
The second switch is means for controlling connection / disconnection between the first switch and the signal line, and when the switch is on, the first switch and the signal line are in a conductive state, and when the switch is off, the first switch The switch and the signal line in a non-conductive state,
The third switch is a means for controlling the connection and disconnection between the connection point between the constant voltage input terminal held at the fixed conductive position,
The constant voltage input terminal is kept at a fixed potential equal to the potential of the counter electrode,
In the time of sampling, the first switch and the second switch is turned on at the same time, the potential of the holding capacitor connection to the potential of the gradation signal input terminal are equal, the gradation signal to said storage capacitor Is applied,
At the time of non-sampling, the first switch and the second switch are turned off simultaneously, and the third switch is turned on, so that the storage capacitor maintains a charge until the next sampling. and, the signal line driving circuit of an active matrix type liquid crystal display device, characterized in that said connecting point is connected to the constant voltage input terminal. 2. The signal line driving circuit of an active matrix liquid crystal display device according to claim 1, wherein each of the first switch and the second switch has at least one thin film transistor.

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