JPH071883B2 - Envelope assembly method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Industrial Field of the Invention The present invention is generally used for high speed data transfer,
The present invention relates to an envelope assembling method capable of transferring 48 Kbit / S, 50 Kbit / S, 56 Kbit / S with the same frame configuration only by controlling the insertion of dummy bits.

[Conventional technology]

According to the International Telegraph and Telephone Consultative Committee (CCITT) announcement X.50, 8 consecutive bits are used as an envelope, the first bit is a framing bit, the last bit is a status bit, and the remaining bits sandwiched between both bits are data bits. The 8-bit envelope to be set is set.

[Problems to be solved by the invention]

In the 8-bit envelope in CCITT Announcement, X.50, since the data bit is 6 bits, an envelope other than data having a bit rate that is a multiple of 6 cannot be assembled. That is, 50Kbit / S out of 48Kbit / S, 50Kbit / S, 56Kbit / S, which are generally used for high-speed data transfer.
56Kbit / S cannot be configured by the envelope.

[Means for solving problems]

An object of the present invention is to provide an envelope assembling method that eliminates the above-mentioned drawbacks.

The envelope assembling method of the present invention is a continuous signal bit stream having a speed of 60 Kbit / S, where 30 bits are the envelope, the head is the envelope synchronization signal, the last bit is the status bit, and the remaining bits are the data transfer bits. When transferring data having a speed of 56 Kbit / S, all the data bits are used for transferring the data, and having a speed of 50 Kbit / S. When transferring the data, a dummy of 3 bits is included in the data. When bits are inserted and data having a speed of 48 Kbit / S is transferred, 4-bit dummy bits are inserted and the envelope can be configured only by controlling the insertion of dummy bits.

〔Example〕

Next, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 (1) shows a continuous envelope composed of 30 bits in a signal bit stream having a speed of 60 Kbit / S. The leading E bit indicates an envelope synchronization bit, the D bit indicates a data transfer bit, and the final S bit indicates a status bit for transferring interface information of the data terminal. Fig. 1 (2)
Indicates a frame in which data at a speed of 56 Kbit / S is composed of an envelope. The data transfer bits of the envelope are
Since it is 28 bits, the envelope is assembled by inserting E and S bits only, and a 60 Kbit / S data stream is obtained. FIG. 1 (3) shows a frame in which data having a speed of 50 Kbit / S is composed of an envelope. At this time S
The 3 N bits before the bit indicate a dummy bit. By inserting this dummy bit, 56 Kbit / S
An envelope can be constructed in the same manner as in, and a 60 Kbit / S data stream can be obtained. FIG. 1 (4) shows that data having a speed of 48 Kbit / S is composed of an envelope. At this time, a data stream of 60 Kbit / S is obtained by setting the dummy bits N bits to 4 bits.

FIG. 2 shows a circuit that implements the envelope method described above. The data having a speed of 56, 50, 48 Kbit / S inputted from the terminal a and the status information given to the terminal e are respectively written in the FIFO1 by the clock inputted from the terminal b. In response to the 60 Kbit / S clock supplied from the terminal c, the sampling pulse generation circuit 2
Generates a sampling pulse of a 60 Kbit / S signal bit stream. The terminal d is a transmission speed selection signal input terminal. The control circuit 4 generates the insertion timing of the frame bit (FIG. 3A), the status bit and the dummy bit (FIG. 3B) based on the basic clock, and also generates the selection control signal of the selector 6. The selector 3 responds to the transmission speed selection signal given from the terminal d by 50 Kb.
A dummy bit for it / S (3 bits) or a dummy bit for 48 Kbit / S (4 bits) is selected and supplied to the AND gate 9. The output of the AND gate 9 corresponds to the read inhibit signal of the FIFO1, and the AND signal is taken from the timing signal from the timing generation circuit 2 to obtain the FIFO1 signal.
The read clock of is obtained. That is, at the frame bit and dummy bit positions, FIFO1 stops reading data. The status bit is read from the FIFO 1 together with the data and supplied to the selector 6. The selector 6 includes a frame bit from a frame bit generation circuit 7 including a flip-flop, data, and
The status bit is switched according to the selection control signal from the control circuit 4 and output as the signal shown in FIG. 3 (c).

〔The invention's effect〕

As described above, according to the present invention, 48 Kbit, 50 Kbit / S, and 56 Kbit / S generally used for high-speed data transfer can be transferred with the same frame structure only by controlling the dummy bit insertion.

[Brief description of drawings]

1 (1) to (4) are signal frames for explaining an embodiment of the present invention, and FIGS. 2 and 3 (a) to (c) are envelopes used for implementing the present invention. It is a circuit diagram of an assembled circuit and its operation waveform diagram. 1 ... FIFO, 2 ... Sampling timing generation circuit,
6 ... Select circuit, 4 ... Control circuit.

Claims (1)

[Claims] 1. A continuous 30 bits of a signal bit stream having a speed of 60 Kbits is an envelope, the beginning thereof is an envelope synchronization signal, and the last bit is a status bit for transferring interface information of a data terminal, and both bits are sandwiched between them. The remaining bits are used as data transfer bits and data having a speed of 56 Kbit / S is transferred. All the data transfer bits are used to transfer 56 Kbit data and data having a speed of 50 Kbit / S. To transfer 3 bits of the data transfer bit
Dummy bit is inserted into the bit, and it has a speed of 48 Kbit / S. When transferring data, the dummy bit of 4 bits is inserted, which is an envelope assembly method.