JPH0718451U - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0718451U JPH0718451U JP046668U JP4666893U JPH0718451U JP H0718451 U JPH0718451 U JP H0718451U JP 046668 U JP046668 U JP 046668U JP 4666893 U JP4666893 U JP 4666893U JP H0718451 U JPH0718451 U JP H0718451U
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- copper
- copper wiring
- groove
- copper plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
(57)【要約】
【目的】 高い強度を有するモールド型電力用半導体モ
ジュール用基板のを提供する。
【構成】 セラミックス基板１の表面に銅配線５を施し
て半導体チップ６をハンダ付けし、さらにセラミックス
基板１の裏面に銅板２を施し、銅またはアルミニウムで
できた放熱板４をハンダ付けした半導体装置において、
セラミックス基板１と放熱板４との間に介在させる銅板
２に、ハンダ付けの際のフラックスガス抜き用の溝部８
を形成し、その深さをその銅板２の厚さ未満に設定す
る。
(57) [Summary] [Object] To provide a mold type power semiconductor module substrate having high strength. A semiconductor device in which copper wiring 5 is provided on the surface of a ceramic substrate 1 and a semiconductor chip 6 is soldered, and a copper plate 2 is provided on the back surface of the ceramic substrate 1, and a heat dissipation plate 4 made of copper or aluminum is soldered. At
A groove portion 8 for flux gas removal at the time of soldering is provided on a copper plate 2 interposed between the ceramics substrate 1 and the heat dissipation plate 4.
Is formed and the depth thereof is set to be less than the thickness of the copper plate 2.
Description
【０００１】[0001]
本考案は、モールド型電力用半導体モジュールに使用する基板を製作する半導 体装置に関する。 The present invention relates to a semiconductor device for manufacturing a substrate used for a mold type power semiconductor module.
【０００２】[0002]
モールド型電力用半導体モジュールに使用する基板の例を図３及び図４を用い て説明する。 An example of a substrate used for the mold type power semiconductor module will be described with reference to FIGS. 3 and 4.
【０００３】 尚、以下の各図において符号は共通であり、１はセラミックス基板、２は銅板 、３はハンダ、４は放熱板、５は銅配線、６は半導体チップ、７はリード線、８ はガス抜き用溝部、９はフィン取り付け用穴部を表す。In each of the following drawings, reference numerals are common, 1 is a ceramic substrate, 2 is a copper plate, 3 is solder, 4 is a heat sink, 5 is copper wiring, 6 is a semiconductor chip, 7 is a lead wire, 8 Indicates a groove for venting gas, and 9 indicates a hole for attaching a fin.
【０００４】 図３（ａ）は従来例１のモールド型電力用半導体モジュールに使用される基板 の側面図である。セラミックス基板１の上に銅配線５を施し、半導体チップ６を 銅配線５の上にハンダ付けする。FIG. 3A is a side view of a substrate used in the mold type power semiconductor module of the first conventional example. Copper wiring 5 is provided on the ceramic substrate 1, and the semiconductor chip 6 is soldered on the copper wiring 5.
【０００５】 また通電することで発生するモジュール熱を逃がすために銅またはアルミニウ ムでできた放熱板４をセラミックス基板１の下にハンダ付けする。この際、セラ ミックス基板１と放熱板４とのハンダ付けは接着性が悪いので、セラミックス基 板１の裏面に銅板２を施して、その銅板２と放熱板４をハンダ付けする。Further, a heat sink 4 made of copper or aluminum is soldered under the ceramic substrate 1 in order to dissipate module heat generated by energization. At this time, since the ceramic substrate 1 and the heat sink 4 are poorly soldered to each other, a copper plate 2 is applied to the back surface of the ceramic substrate 1, and the copper plate 2 and the heat sink 4 are soldered.
【０００６】 図３（ａ）のＡ−Ａ’の鎖線で示された部分の断面図である図３（ｂ）に示し たように、銅板２は放熱板４との接触面積が大きいためにハンダ付けの際、発生 するフラックス（ハンダ付剤）のガス抜き用の溝部８を設けている。Since the copper plate 2 has a large contact area with the heat dissipation plate 4 as shown in FIG. 3B which is a cross-sectional view of the portion indicated by the chain line AA ′ in FIG. A groove 8 is provided for degassing the flux (soldering agent) generated when soldering.
【０００７】 このガス抜き溝部８によってセラミックス基板１が裏面で露出し、この溝部８ の位置に対応するセラミックスの表面に銅配線が通っていない場合、セラミック ス基板１が両面で露出し、その部分で機械的強度が弱く、その部分でマイクロク ラックや割れが発生している。放熱板４はファン取付け用穴９によって冷却ファ ン等に固定させる。When the ceramic substrate 1 is exposed on the back surface by the gas vent groove 8 and the copper wiring does not pass through the surface of the ceramic corresponding to the position of the groove 8, the ceramic substrate 1 is exposed on both sides and The mechanical strength is weak, and micro-cracks and cracks occur in that area. The heat radiating plate 4 is fixed to a cooling fan or the like by a fan mounting hole 9.
【０００８】 図４（ａ）は、従来例２のモールド型電力用半導体モジュールに使用される基 板の立体図である。従来例１と同様に、セラミックス基板１の上に銅配線５を施 し、半導体チップ６を銅配線５の上にハンダ付けする。FIG. 4A is a three-dimensional view of a base plate used in a mold type power semiconductor module of Conventional Example 2. Similar to the conventional example 1, the copper wiring 5 is provided on the ceramic substrate 1, and the semiconductor chip 6 is soldered on the copper wiring 5.
【０００９】 また通電することで発生するモジュール熱を逃がすために銅またはアルミニウ ムでできた放熱板４をセラミックス基板１の下にハンダ付けする。A heat sink 4 made of copper or aluminum is soldered under the ceramic substrate 1 in order to dissipate module heat generated by energization.
【００１０】 この際、セラミックス基板１と放熱板４とのハンダ付けは接着性が悪いので、 セラミックス基板１の裏面に銅板２を施して、その銅板２と放熱板４をハンダ付 けする。図４（ａ）のＡ−Ａ’の鎖線で示された部分の断面図である図４（ｂ） と、図４（ｃ）のセラミックス基板の裏面の銅板配列図に示されているように、 銅板２とフラックスガス抜き用の溝部８が交互に配されている。At this time, since the ceramic substrate 1 and the heat sink 4 are poorly soldered to each other, a copper plate 2 is applied to the back surface of the ceramic substrate 1 and the copper plate 2 and the heat sink 4 are soldered. As shown in FIG. 4 (b), which is a cross-sectional view of the portion indicated by the chain line of AA ′ in FIG. 4 (a), and the copper plate array diagram on the back surface of the ceramic substrate of FIG. 4 (c). The copper plate 2 and the groove portion 8 for flux degassing are alternately arranged.
【００１１】 したがって、セラミックス基板の表面に銅配線がなく、かつその位置に対応す る裏面が溝になっている場合、セラミックスの両面が露出していて、機械的強度 が弱い部分が存在し、その部分でマイクロクラックや割れが発生している。Therefore, when there is no copper wiring on the front surface of the ceramic substrate and the back surface corresponding to the position is a groove, both surfaces of the ceramic are exposed and there is a portion with weak mechanical strength. Micro-cracks and cracks have occurred in that part.
【００１２】[0012]
上記のようにモールド型電力用半導体モジュールに使用する基板を製作する工 程において、セラミックス基板と金属製の放熱板、銅板とでは熱膨張係数が異な る。 As described above, in the process of manufacturing the substrate used for the mold type power semiconductor module, the coefficient of thermal expansion is different between the ceramic substrate, the metal radiator plate and the copper plate.
【００１３】 従って放熱板を銅板とハンダを用いて熱処理して接着する際または接着後に、 熱応力やせん断応力が加わり、セラミックス基板が湾曲してしまうという問題が ある。[0013] Therefore, there is a problem in that the heat dissipation plate is heat-treated with a copper plate by using a solder, and after or after the adhesion, a thermal stress or a shear stress is applied and the ceramic substrate is curved.
【００１４】 また、放電板を冷却ファンに取付けた際の放熱板の反りによってもセラミック スに応力が生じ、き裂が生じる原因となる。このように組合せ応力が加わる条件 下では、セラミックス基板が銅配線や銅板で補強されていない部分に応力集中が 起き、その結果、セラミックス基板に微細な割れ目や切れ目（マイクロクラック ）が発生する。Further, the warp of the heat dissipation plate when the discharge plate is attached to the cooling fan also causes stress in the ceramics, which causes cracks. Under such conditions of combined stress, stress concentration occurs in the portion of the ceramic substrate that is not reinforced by the copper wiring or copper plate, and as a result, fine cracks or cuts (microcracks) occur in the ceramic substrate.
【００１５】 図３のようなガス抜き用溝の位置に対応するセラミックス表面に銅配線が存在 しない部分では、セラミックス基板が両面で露出している。そのような不規則な 形状の部分は他の部分より機械的強度が弱く、したがって、この部分に応力集中 が起きやすく、またこれが原因となり、マイクロクラックや割れが発生する。In a portion where copper wiring does not exist on the ceramic surface corresponding to the position of the gas vent groove as shown in FIG. 3, the ceramic substrate is exposed on both sides. Such an irregularly shaped portion has weaker mechanical strength than other portions, and thus stress concentration is more likely to occur in this portion, which causes microcracks and cracks.
【００１６】 図４のような銅配線と溝が平行になっている状態では、図４（ｂ）のｄの部分 では、セラミックスの表面に銅配線がなくかつ裏面に溝があるため、他の部分に 比較して、機械的強度が弱い構造となっている。In a state where the copper wiring and the groove are parallel to each other as shown in FIG. 4, since there is no copper wiring on the surface of the ceramic and there is a groove on the back surface in the portion d of FIG. The structure has weaker mechanical strength than the part.
【００１７】 また、セラミックス基板と銅配線や溝が平行になっているために、ｄの部分の 溝の上部に銅配線がかかる割合が少なく、セラミックスの両面が露出する長さ（ ｈ）が非常に長く、この領域に応力集中が生じ易い。Further, since the ceramic substrate and the copper wiring and the groove are parallel to each other, the proportion of the copper wiring applied to the upper part of the groove at the portion d is small, and the length (h) at which both surfaces of the ceramic are exposed is extremely small. It is long and stress concentration is likely to occur in this area.
【００１８】 セラミックス基板と放熱板とのハンダ付け後の熱膨張や圧縮による放熱板の反 りや振動等により、セラミックス基板のｄの部分の溝に沿った機械的強度が弱い 部分に、応力き裂が発生するという問題がある。Due to the warp and vibration of the heat sink due to thermal expansion and compression of the ceramic substrate and the heat sink after soldering, stress cracks are generated along the groove at the d portion of the ceramic substrate where mechanical strength is weak. There is a problem that occurs.
【００１９】 セラミックス基板の不規則な部分があると、これらの部分に応力集中が起こり 、低い荷重でも破壊することがあり、設計上重要な問題である。If there are irregular portions of the ceramic substrate, stress concentration will occur in these portions, and they may be destroyed even under a low load, which is an important design problem.
【００２０】 本考案は、上述した問題に鑑みてなされたもので、その目的とするところは、 モールド型電力用半導体モジュールに使用するセラミックス基板に不規則な機械 的強度の弱い応力集中部ができないような半導体装置を提供するにある。The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a ceramic substrate used for a mold type power semiconductor module with an irregular stress concentration portion having weak mechanical strength. It is to provide such a semiconductor device.
【００２１】[0021]
上記課題を解決するために、請求項１記載の発明は、セラミックス基板表面に 銅配線を施してその上に半導体チップをハンダ付けし、さらにセラミックス基板 の裏面に銅板を介して放熱板をハンダ付けした半導体装置において、前記銅板に 、フラックスガス抜き用の溝部を形成するとともに、前記溝部は前記銅配線と一 定角θ（θ≠０，π）で交差するように形成されていることを特徴とする半導体 装置を提供する。 In order to solve the above-mentioned problems, the invention according to claim 1 provides copper wiring on the surface of a ceramic substrate and solders a semiconductor chip on it, and further solders a heat sink on the back surface of the ceramic substrate via a copper plate. In the semiconductor device described above, a groove portion for flux gas removal is formed in the copper plate, and the groove portion is formed so as to intersect the copper wiring at a constant angle θ (θ ≠ 0, π). To provide a semiconductor device.
【００２２】 請求項２記載の発明は、セラミックス基板表面に銅配線を施してその上に半導 体チップをハンダ付けし、さらにセラミックス基板の裏面に銅板を介して放熱板 をハンダ付けした半導体装置において、前記銅板の放熱板と対抗する面にフラッ クスガス抜き用の溝部を形成するとともに、前記溝部の深さをその銅板の厚さ未 満としたことを特徴とする半導体装置を提供する。According to a second aspect of the present invention, there is provided a semiconductor device in which copper wiring is provided on a surface of a ceramic substrate, a semiconductor chip is soldered on the copper wiring, and a radiator plate is soldered on the back surface of the ceramic substrate via a copper plate. In the semiconductor device, the groove portion for removing the flux gas is formed on the surface of the copper plate facing the heat dissipation plate, and the depth of the groove portion is less than the thickness of the copper plate.
【００２３】[0023]
上記のように、セラミックス基板上の銅配線がない部分とセラミックス基板の 裏面の溝の位置が重ならないように、セラミックス基板と放熱板との間に介在さ せる銅板のフラックスガス抜き用の溝のパターンを形成し、これによってセラミ ックス基板に応力集中部分ができないようにする。 As described above, in order to prevent the copper wiring on the ceramic substrate and the groove on the back surface of the ceramic substrate from overlapping, the flux degassing groove of the copper plate interposed between the ceramic substrate and the heat dissipation plate A pattern is formed to prevent stress concentration areas on the ceramic substrate.
【００２４】 セラミックス基板上に任意に銅配線を描くという自由度をもたせた場合、その 銅配線による不規則性を裏面の銅板を配列する際に緩和させなければならない。 従って、銅板をセラミックス基板上の銅配線部分のないところに対応するセラ ミックス基板の裏面に付け、フラックスガス抜き用の溝のところに対応するセラ ミックス基板の表面に銅配線が存在するように配列することによって、セラミッ クス基板の機械的強度を高めた。When the degree of freedom of arbitrarily drawing copper wiring on the ceramics substrate is provided, the irregularity due to the copper wiring must be relaxed when the copper plate on the back surface is arranged. Therefore, attach a copper plate to the back surface of the ceramic substrate corresponding to the place where there is no copper wiring on the ceramic substrate, and arrange so that the copper wiring exists on the surface of the ceramic substrate corresponding to the groove for flux degassing. By doing so, the mechanical strength of the ceramic substrate was increased.
【００２５】[0025]
以下、本考案の実施例を説明するが、本考案は以下の実施例に限定されるもの ではない。本考案の実施例を図１と図２に基づいて説明するが、符号はすべての 図において統一されており、図３〜図４に前述された符号の説明は省略する。 Hereinafter, embodiments of the present invention will be described, but the present invention is not limited to the following embodiments. Embodiments of the present invention will be described with reference to FIGS. 1 and 2, but the reference numerals are the same in all the drawings, and the explanation of the reference numerals described above in FIGS. 3 to 4 will be omitted.
【００２６】 実施例１の半導体装置を図１（ｂ）に示す。この図に示されるように、フラッ クスのガス抜きが妨げられない程度にセラミックスの裏面を銅板で被覆し、フラ ックスガス抜き用溝部８の深さを銅板の厚み未満とし、セラミックスの裏面が溝 部８で露出しないようにした。The semiconductor device of Example 1 is shown in FIG. As shown in this figure, the back surface of the ceramic is covered with a copper plate to the extent that the degassing of the flux is not hindered, and the depth of the flux degassing groove 8 is less than the thickness of the copper plate. No exposure at 8.
【００２７】 尚、溝部は半円形型のトンネル型あるいは直方体型でも、セラミックス基板を 補強でき、かつフラックスガス抜きが効率良くできるものであれば、どのような ものでも良い。The groove may be a semi-circular tunnel type or a rectangular parallelepiped type as long as it can reinforce the ceramic substrate and efficiently remove the flux gas.
【００２８】 図２に実施例２及び実施例３の半導体装置を示す。この図に示されるように、 セラミックス基板表面上に任意に描かれた銅配線に対してセラミックス裏面の銅 板をねじれの位置に配することによって、一本の溝の上部には、必ず銅配線が存 在するようなパターンとし、セラミックス基板の両面が露出している部分、例え ば、図４（ｂ）のｄの部分の長さｈを極力短くするようにした。FIG. 2 shows a semiconductor device according to the second and third embodiments. As shown in this figure, by arranging the copper plate on the back surface of the ceramic in a twisted position with respect to the copper wiring arbitrarily drawn on the surface of the ceramic substrate, make sure that the copper wiring is always above the groove. Is present, and the length h of the portion where both surfaces of the ceramic substrate are exposed, for example, the portion of d in FIG. 4B is made as short as possible.
【００２９】 例えば、銅配線に対し、セラミックス基板の配置を実施例２の斜線状（図２（ ａ））、実施例３の放射状（図２（ｂ））、網目状や曲線状とする。このように できるだけセラミックスの表面に配線がないところに対応するセラミックスの裏 面には銅板が存在するように、かつフラックスのガス抜きが妨げられないように 銅板を設置する。For example, with respect to the copper wiring, the ceramic substrate is arranged in a diagonal pattern (FIG. 2A) of the second embodiment, a radial pattern (FIG. 2B) of the third embodiment, a mesh pattern or a curved pattern. In this way, place a copper plate on the back surface of the ceramic corresponding to the place where there is no wiring on the surface of the ceramic as much as possible, and place the copper plate so that the degassing of the flux is not obstructed.
【００３０】 セラミックス基板上に任意に描いた銅配線によって加わる応力を、セラミック ス表面に銅配線がない部分に対応するセラミックス裏面に銅板を配置することに よってセラミックス基板に加わる組合せ応力を緩和できる。The stress applied by the copper wiring arbitrarily drawn on the ceramics substrate can be relaxed by arranging the copper plate on the back surface of the ceramics corresponding to the portion where there is no copper wiring on the ceramics surface.
【００３１】 また、セラミックス表面に描く銅配線のパターンが規格化されている場合は、 その銅配線によってもたらされる応力を緩和するようなセラミックス基板の裏面 の銅板の配置を規格化する。When the pattern of copper wiring drawn on the surface of the ceramic is standardized, the arrangement of the copper plate on the back surface of the ceramic substrate is standardized so as to relieve the stress caused by the copper wiring.
【００３２】[0032]
以上の如く本考案によれば、以下に述べるような種々の効果を奏する。 As described above, according to the present invention, various effects as described below are exhibited.
【００３３】 （１）セラミックス基板の機械的に弱い構造部分を放熱板との間の銅板で保護 することによって、セラミックス基板の機械的強度を増加させ、溝部分の応力集 中を緩和し、その結果、組合せ応力によるマイクロクラックスや割れ目の低減を はかることができる。(1) The mechanical strength of the ceramics substrate is protected by the copper plate between the heat dissipation plate and the mechanically weak structure portion of the ceramics substrate, thereby increasing the mechanical strength of the ceramics substrate and relaxing the stress concentration in the groove part. As a result, it is possible to reduce microcracks and cracks due to combined stress.
【００３４】 （２）セラミックス基板の両面をなるべく露出させないために、セラミックス 表面上に設計された銅配線が存在しないところに対応するセラミックス基板の裏 面に銅板が存在するように溝パターンを形成することによって、セラミックス基 板を補強し、セラミックス基板に発生する割れ、マイクロクラックスの低減をは かることができる。(2) In order to prevent both surfaces of the ceramic substrate from being exposed as much as possible, a groove pattern is formed so that a copper plate exists on the back surface of the ceramic substrate corresponding to the place where the designed copper wiring does not exist on the ceramic surface. By doing so, it is possible to reinforce the ceramic substrate and reduce cracks and microcracks generated in the ceramic substrate.
【００３５】 （３）セラミックス基板上に任意に描いた銅配線によって加わる応力を、セラ ミックス表面に銅配線がない部分に対応するセラミックス裏面のねじれの位置に 銅板を配置することによってセラミックス基板に加わる組合せ応力を緩和できる 。(3) The stress applied by the copper wiring arbitrarily drawn on the ceramic substrate is applied to the ceramic substrate by arranging the copper plate at the twisted position on the back surface of the ceramic corresponding to the portion where the copper wiring is not present on the ceramic surface. Combined stress can be relaxed.
【図面の簡単な説明】[Brief description of drawings]
【図１】半導体装置の横断面図。FIG. 1 is a cross-sectional view of a semiconductor device.
【図２】銅板の配置パターンの説明図。FIG. 2 is an explanatory view of an arrangement pattern of copper plates.
【図３】モールド型電力用半導体モジュール用基板の説
明図。FIG. 3 is an explanatory diagram of a mold type power semiconductor module substrate.
【図４】モールド型電力用半導体モジュール用基板の説
明図。FIG. 4 is an explanatory diagram of a mold type power semiconductor module substrate.
１…セラミックス基板 ２…銅板 ３…ハンダ ４…放熱板 ５…銅配線 ６…半導体チップ ７…リード線 ８…ガス抜き用溝部 ９…フィン取り付け用穴部 DESCRIPTION OF SYMBOLS 1 ... Ceramics substrate 2 ... Copper plate 3 ... Solder 4 ... Heat sink 5 ... Copper wiring 6 ... Semiconductor chip 7 ... Lead wire 8 ... Gas vent groove 9 ... Fin mounting hole
Claims (2)
その上に半導体チップをハンダ付けし、さらにセラミッ
クス基板の裏面に銅板を介して放熱板をハンダ付けした
半導体装置において、 前記銅板に、フラックスガス抜き用の溝部を形成すると
ともに、前記溝部は前記銅配線と一定角θ（θ≠０，
π）で交差するように形成されていることを特徴とする
半導体装置。1. A semiconductor device in which copper wiring is provided on the surface of a ceramic substrate, a semiconductor chip is soldered on the copper wiring, and a heat sink is soldered on the back surface of the ceramic substrate via a copper plate. A groove for extraction is formed, and the groove forms a constant angle θ (θ ≠ 0,
A semiconductor device, which is formed so as to intersect at π).
その上に半導体チップをハンダ付けし、さらにセラミッ
クス基板の裏面に銅板を介して放熱板をハンダ付けした
半導体装置において、 前記銅板の放熱板と対抗する面にフラックスガス抜き用
の溝部を形成するとともに、前記溝部の深さをその銅板
の厚さ未満としたことを特徴とする半導体装置。2. A semiconductor device in which copper wiring is provided on the surface of a ceramic substrate, a semiconductor chip is soldered on the copper wiring, and a heat sink is soldered on the back surface of the ceramic substrate via a copper plate. A semiconductor device, characterized in that a groove for flux gas removal is formed on the opposing surface, and the depth of the groove is less than the thickness of the copper plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP046668U JPH0718451U (en) | 1993-08-27 | 1993-08-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP046668U JPH0718451U (en) | 1993-08-27 | 1993-08-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0718451U true JPH0718451U (en) | 1995-03-31 |
Family
ID=12753742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP046668U Pending JPH0718451U (en) | 1993-08-27 | 1993-08-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0718451U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013157464A (en) * | 2012-01-30 | 2013-08-15 | Mitsubishi Materials Corp | Manufacturing method of substrate for power module with heat sink |
| JP2013157524A (en) * | 2012-01-31 | 2013-08-15 | Mitsubishi Materials Corp | Manufacturing method of substrate for power module with heat sink and substrate for power module |
| JP2013157361A (en) * | 2012-01-26 | 2013-08-15 | Mitsubishi Materials Corp | Manufacturing method of substrate for power module with heat sink |
| WO2022196411A1 (en) * | 2021-03-15 | 2022-09-22 | 三菱電機株式会社 | Semiconductor device and power conversion device |
-
1993
- 1993-08-27 JP JP046668U patent/JPH0718451U/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013157361A (en) * | 2012-01-26 | 2013-08-15 | Mitsubishi Materials Corp | Manufacturing method of substrate for power module with heat sink |
| JP2013157464A (en) * | 2012-01-30 | 2013-08-15 | Mitsubishi Materials Corp | Manufacturing method of substrate for power module with heat sink |
| JP2013157524A (en) * | 2012-01-31 | 2013-08-15 | Mitsubishi Materials Corp | Manufacturing method of substrate for power module with heat sink and substrate for power module |
| WO2022196411A1 (en) * | 2021-03-15 | 2022-09-22 | 三菱電機株式会社 | Semiconductor device and power conversion device |
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