JPH07183347A - Method for evaluating semiconductor tool material - Google Patents

Method for evaluating semiconductor tool material

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Publication number
JPH07183347A
JPH07183347A JP32362593A JP32362593A JPH07183347A JP H07183347 A JPH07183347 A JP H07183347A JP 32362593 A JP32362593 A JP 32362593A JP 32362593 A JP32362593 A JP 32362593A JP H07183347 A JPH07183347 A JP H07183347A
Authority
JP
Japan
Prior art keywords
wafer
semiconductor
monitor
jig material
heat treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP32362593A
Other languages
Japanese (ja)
Other versions
JP2847228B2 (en
Inventor
Kazuhiro Minagawa
和弘 皆川
Tadahisa Arahori
忠久 荒堀
Yasuo Koike
康夫 小池
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Sumitomo Sitix Corp
Sumitomo Metal Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Application filed by Sumitomo Sitix Corp, Sumitomo Metal Industries Ltd filed Critical Sumitomo Sitix Corp
Priority to JP32362593A priority Critical patent/JP2847228B2/en
Publication of JPH07183347A publication Critical patent/JPH07183347A/en
Application granted granted Critical
Publication of JP2847228B2 publication Critical patent/JP2847228B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To detect a metal impurity released from a tool material by performing heat treatment by erecting a wafer for monitoring and the forming body of a semiconductor tool material machined in a wafer shape on a wafer board consisting of a high-purity crystal, etc., provided inside a process tube and then measuring the characteristics of the wafer for monitor. CONSTITUTION:Two forming bodies 13 of a semiconductor jig material are erected on a wafer board 12 with a fixed spacing while retaining a wafer 14 for monitor in-between, the wafer board 12 is placed inside a process tube 11 made of crystal, and then the wafer board 12 is heat-treated for a specific amount of time at a specific temperature within a certain gas atmosphere. The metal impurity released from the forming body 13 of semiconductor tool material is adhered to the wafer 14 for monitor by heat treatment. Then, various kinds of characteristics of the wafer 14 for monitor containing the metal impurity are measured, thus determining the type, amount, and distribution of the metal impurity which easily travels due to the heating of the forming body 13 of semiconductor jig material.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体治具材料の評価方
法に関し、より詳細には、ウエハボートやプロセスチュ
ーブ等、半導体の熱処理に用いられる半導体治具材料か
ら半導体への汚染に対する評価を行う半導体治具材料の
評価方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for evaluating a semiconductor jig material, and more particularly, to evaluate the contamination of a semiconductor jig material such as a wafer boat or a process tube used for heat treatment of a semiconductor with a semiconductor. A method for evaluating a semiconductor jig material.

【0002】[0002]

【従来の技術】近年、半導体産業の発達に伴い、シリコ
ンウエハ等の半導体基板上に種々の素子等を形成する際
に、様々な半導体製造プロセスが採用されている。
2. Description of the Related Art In recent years, with the development of the semiconductor industry, various semiconductor manufacturing processes have been adopted when forming various elements and the like on a semiconductor substrate such as a silicon wafer.

【0003】これらの半導体製造プロセスにおいては、
熱酸化処理等、種々の熱処理が行われるが、この種の熱
処理を行う際に用いられる容器や半導体基板を保持等す
る半導体治具が十分に高純度でない場合、これらの半導
体治具から半導体基板への金属等の汚染が発生し、この
汚染が半導体装置の誤動作の原因になる等の問題があ
る。
In these semiconductor manufacturing processes,
Various heat treatments such as thermal oxidation are performed, but if the container used for performing this kind of heat treatment or the semiconductor jig that holds the semiconductor substrate is not of sufficiently high purity, the semiconductor jig is used to remove the semiconductor substrate. There is a problem that the metal is contaminated with the metal and the contamination causes a malfunction of the semiconductor device.

【0004】従って、これらの半導体治具が、半導体基
板に悪影響を与えないか否かにつき、その純度等を厳し
くチェックしておく必要があり、また実際の熱処理条件
下で、半導体治具により半導体基板がどの程度汚染され
るかも詳しく調べておく必要がある。
Therefore, it is necessary to rigorously check the purity and the like of these semiconductor jigs to see if they adversely affect the semiconductor substrate. Also, under the actual heat treatment conditions, the semiconductor jigs should be used for semiconductor inspection. It is also necessary to investigate in detail how much the substrate is contaminated.

【0005】従来から行われている、ウエハボートやプ
ロセスチューブなどに用いられる半導体治具材料の評価
方法としては、 半導体治具材料を加圧・溶解し、原子吸光分析法、
ICP分析法等を用いて溶液中の金属不純物を定量する
ことにより、半導体治具材料に含まれる不純物の量を分
析する方法、 半導体治具材料による半導体ウエハの汚染の度合い
を調べるため、その半導体治具材料を用いて作製したプ
ロセスチューブやウエハボート等の半導体治具を実際に
使用し、金属の拡散係数がシリコンと同等かそれ以下の
金属捕集用物体を熱処理することにより、前記金属捕集
物体の汚染の程度等を測定する方法(特開平4−267
327号公報)、 前記金属捕集用物体等を用い、この金属捕集用物体
と半導体治具とを接触させた状態で熱処理し、金属捕集
物体に捕集された金属を定量する方法(月間Semiconduc
tor World 6月号 1992年 58−65頁)、等
が挙げられる。
As a conventional method for evaluating a semiconductor jig material used for a wafer boat, a process tube, etc., a semiconductor jig material is pressurized and melted, and an atomic absorption analysis method,
A method for analyzing the amount of impurities contained in a semiconductor jig material by quantifying metal impurities in a solution using an ICP analysis method or the like, and a semiconductor wafer for examining the degree of contamination of a semiconductor wafer by the semiconductor jig material. By actually using a semiconductor jig such as a process tube or a wafer boat manufactured by using a jig material, by heat-treating a metal collecting object having a metal diffusion coefficient equal to or less than that of silicon, A method for measuring the degree of contamination of a collected object (Japanese Patent Laid-Open No. 4-267)
No. 327), a method of quantifying the metal collected in the metal collecting object by heat-treating the metal collecting object and the like with the metal collecting object and the semiconductor jig being in contact with each other. Month Semiconduc
tor World June issue, 1992, pp. 58-65), and the like.

【0006】[0006]

【発明が解決しようとする課題】しかし、上記に記載
の半導体治具材料を溶解し、化学分析等で定量する方法
では、不純物の存在量はわかるが、石英、炭化珪素、炭
素等の半導体治具材料に含まれる不純物が使用される際
の条件、例えば雰囲気や温度等の違いによってどの程度
汚染度が異なるかが明確にならず、また、0.1ppm
以下といった超微量分析は簡単に行うことができないと
いう課題があった。
However, in the method of dissolving the semiconductor jig material described above and quantifying it by chemical analysis or the like, the amount of impurities is known, but the semiconductor treatment of quartz, silicon carbide, carbon, etc. It is not clear to what extent the degree of contamination differs depending on the conditions in which impurities contained in ingredients are used, such as differences in atmosphere and temperature, and 0.1 ppm
There is a problem that the following ultra-trace analysis cannot be performed easily.

【0007】また、上記に記載の半導体治具材料で作
製されたプロセスチューブやウエハボート等を実際に用
いて金属捕集用物体の熱処理を行なう方法では、複雑な
形状の治具を試作しなければならないため、評価のため
のコストが高くなり、また時間がかかる等の課題があっ
た。また金属捕集用物体と治具との距離が遠いため半導
体治具材料からの汚染が少なく精度の高い評価ができな
い等の課題もあった。
Further, in the method of heat-treating an object for collecting metal by actually using the process tube, the wafer boat, etc. made of the semiconductor jig material described above, a jig having a complicated shape must be manufactured as a prototype. Since it has to be done, there are problems that the cost for evaluation is high and it takes time. Further, since the distance between the metal collecting object and the jig is long, there is a problem that the contamination from the semiconductor jig material is small and highly accurate evaluation cannot be performed.

【0008】さらに、上記に記載の金属捕集用物体を
半導体治具材料で挟んで熱処理を行う、いわゆるサンド
イッチアニール法では、物理的な接触によって金属捕集
用物体等の表面が機械的に傷付けられるため、OSF等
により汚染を評価する方法を用いることができないとい
う課題があった。また、特殊な金属捕集用物体を必要と
するのでコストが高くなるという課題もあった。
Further, in the so-called sandwich annealing method in which the metal collecting object described above is sandwiched between semiconductor jig materials and heat-treated, the surface of the metal collecting object is mechanically damaged by physical contact. Therefore, there is a problem that the method of evaluating contamination by OSF or the like cannot be used. Further, there is a problem that the cost becomes high because a special object for collecting metal is required.

【0009】なお、前記OSF特性を用いる評価とは、
Siウエハ上に拡散した不純物が長時間の熱処理により
大きな積層欠陥を形成することを利用し、この積層欠陥
を顕微鏡等で観察することにより不純物の数や分布等を
評価する方法である。
The evaluation using the OSF characteristics is
This is a method of evaluating the number, distribution, etc. of impurities by utilizing the fact that impurities diffused on a Si wafer form large stacking faults by heat treatment for a long time and observing the stacking faults with a microscope or the like.

【0010】本発明はこのような課題に鑑みなされたも
のであり、直接接触させることにより評価用のモニター
用ウエハを傷付けるということがなく、高温熱処理中に
治具材料から放出される金属不純物を容易かつ高感度に
検出することができるとともに半導体特性への影響を明
確化することが可能となる半導体治具材料の評価方法を
提供することを目的としている。
The present invention has been made in view of the above problems, and it does not damage the monitor wafer for evaluation by directly contacting the metal wafer with the metal impurities released from the jig material during the high temperature heat treatment. It is an object of the present invention to provide a method for evaluating a semiconductor jig material which can be easily and highly sensitively detected and whose influence on semiconductor characteristics can be clarified.

【0011】[0011]

【課題を解決するための手段】上記目的を達成するため
に本発明に係る半導体治具材料の評価方法は、プロセス
チューブ内に設けた高純度石英又は高純度炭化珪素から
なるウエハボート上に、モニター用ウエハとウエハ状に
加工した半導体治具材料の成形体とを併立させて熱処理
を行い、モニター用ウエハの特性を測定することを特徴
としている。
In order to achieve the above object, a method for evaluating a semiconductor jig material according to the present invention comprises: a wafer boat made of high-purity quartz or high-purity silicon carbide provided in a process tube; A characteristic is that the characteristics of the monitor wafer are measured by arranging a monitor wafer and a molded body of a semiconductor jig material processed into a wafer in parallel and performing heat treatment.

【0012】以下、本発明に係る半導体治具材料の評価
方法について、図面に基づいて説明を行う。
A method for evaluating a semiconductor jig material according to the present invention will be described below with reference to the drawings.

【0013】図1は、本発明に係る半導体治具材料の評
価方法を実施するための装置を模式的に示した断面図で
あり、図中、11は石英製のプロセスチューブを示して
いる。
FIG. 1 is a sectional view schematically showing an apparatus for carrying out the method for evaluating a semiconductor jig material according to the present invention. In the figure, reference numeral 11 denotes a quartz process tube.

【0014】図1に示したように、ウエハボート12の
上に2個の半導体治具材料の成形体13をモニター用ウ
エハ14を間に一定の間隔をおいて併立状態で立て、こ
のウエハボート12を石英製のプロセスチューブ11の
内部に載置する。半導体治具材料の成形体13及びモニ
ター用ウエハ14をウエハボート12に立てる際には、
半導体治具材料の成形体13とモニター用ウエハ14と
が直接接触しないように所定の間隔を保って立てる必要
がある。
As shown in FIG. 1, two molded bodies 13 of semiconductor jig material are erected on the wafer boat 12 in parallel with monitor wafers 14 at regular intervals. 12 is placed inside the process tube 11 made of quartz. When the molded body 13 of the semiconductor jig material and the monitor wafer 14 are placed on the wafer boat 12,
It is necessary to keep a predetermined interval so that the molded body 13 of the semiconductor jig material and the monitor wafer 14 do not come into direct contact with each other.

【0015】半導体治具材料の成形体13等が立てられ
たウエハボート12を石英製のプロセスチューブ11に
載置した後、一定のガス雰囲気中、所定の温度、時間で
熱処理を行う。
After mounting the wafer boat 12 on which the molded body 13 of the semiconductor jig material is placed on the process tube 11 made of quartz, heat treatment is performed at a predetermined temperature and time in a constant gas atmosphere.

【0016】処理温度は実際にシリコンウエハを熱処理
する温度であることが正確な評価を行うためには好まし
いが、処理時間を短縮するためにより高い温度で行うこ
とも可能である。処理時間、雰囲気についても実際にシ
リコンウエハを熱処理する条件と同一の条件であること
が半導体治具材料の正確な評価には好ましいが、他の条
件でも行った場合でも、同一条件でそれぞれの半導体治
具材料を処理することにより半導体治具材料の相対的な
評価を行うことができる。
It is preferable that the processing temperature is the temperature at which the silicon wafer is actually heat-treated for accurate evaluation, but higher temperature can be used for shortening the processing time. It is preferable for the accurate evaluation of the semiconductor jig material that the processing time and the atmosphere are the same as the conditions for actually heat-treating the silicon wafer. By processing the jig material, it is possible to make a relative evaluation of the semiconductor jig material.

【0017】前記熱処理によって、半導体治具材料の成
形体13から放出される金属不純物がモニター用ウエハ
14上に付着する。そこで、この金属不純物を含有する
このモニター用ウエハ14の種々の特性の測定を行う。
ここで、モニター用ウエハ14の物性の測定とは、モニ
ター用ウエハ14の物理的、化学的な種々の特性を測定
することをいい、詳しくは後述するが、不純物含有量や
不純物分布等の分析も、この場合の特性の測定に含まれ
る。これにより、半導体治具材料の成形体13の加熱に
より移動し易い金属不純物の種類、量及びその分布等が
わかり、またこれらの金属の移動(汚染)により半導体
に与える影響等を評価することができる。
By the heat treatment, the metal impurities released from the molded body 13 of the semiconductor jig material adhere on the monitor wafer 14. Therefore, various characteristics of the monitor wafer 14 containing the metal impurities are measured.
Here, the measurement of physical properties of the monitor wafer 14 refers to measurement of various physical and chemical characteristics of the monitor wafer 14, which will be described in detail later, but analysis of impurity content, impurity distribution, etc. Is also included in the measurement of properties in this case. From this, it is possible to know the type, amount, and distribution of the metal impurities that are easily moved by heating the molded body 13 of the semiconductor jig material, and to evaluate the influence of the movement (contamination) of these metals on the semiconductor. it can.

【0018】本発明で用いられるモニター用ウエハ14
は、このモニター用ウエハ14に不純物が付着した場合
等に、その特性を良好に測定することができるように作
製されたものであり、例えば裏面にゲッタリング機能を
持たせる、いわゆるBD(バックダメージ)処理を行っ
ておらず、その抵抗値が5〜30Ω・cm程度、結晶方
位が(100)のN型半導体ウエハである。また、この
モニター用ウエハ14は通常熱処理等も行われていな
い。
The monitor wafer 14 used in the present invention
Is manufactured so that the characteristics of the monitor wafer 14 can be satisfactorily measured when impurities are attached to the wafer 14, for example, a so-called BD (back damage) having a gettering function on the back surface. ) It is an N-type semiconductor wafer which has not been subjected to a treatment and has a resistance value of about 5 to 30 Ω · cm and a crystal orientation of (100). Further, the monitor wafer 14 is not usually subjected to heat treatment or the like.

【0019】本発明で評価の対象となる半導体治具材料
の成形体13は、ウエハボート12の上にセットする必
要があるため、モニター用ウエハ14と同一の形状ある
いは若干大きな径を持った形状のものであることが好ま
しい。モニター用ウエハ14と比べて著しく形状が異な
るものやサイズの違うものは拡散炉内の正常なガスの流
通を妨げることにより、評価面積が減少したり、ウエハ
ボート12にセットするのに特別の治具が必要となり好
ましくない。
Since the molded body 13 of the semiconductor jig material to be evaluated in the present invention needs to be set on the wafer boat 12, it has the same shape as the monitor wafer 14 or a shape having a slightly larger diameter. It is preferred that If the shape or size of the monitor wafer 14 is significantly different from that of the monitor wafer 14, the evaluation area is reduced or a special treatment is required to set the wafer boat 12 by preventing normal gas flow in the diffusion furnace. It is not preferable because tools are required.

【0020】評価対象となっている半導体治具材料で作
製したウエハボート12等を用いて測定を行うと汚染量
は少なく、汚染領域に分布ができるため正確な評価が難
しくなる。
When the measurement is carried out using the wafer boat 12 or the like made of the semiconductor jig material which is the object of evaluation, the amount of contamination is small and the distribution can be made in the contaminated region, making accurate evaluation difficult.

【0021】半導体治具材料の成形体13およびモニタ
ー用ウエハ14をセットするために必要なウエハボート
12は高純度なものである必要があることはもちろんで
あり、一般には石英ガラス、特に高純度な合成石英ガラ
スで、含有金属不純物の含有量が0.1ppm以下のも
のであることが好ましい。また、必要とする処理温度が
1100℃を超える高温の場合は、石英ガラスよりも耐
熱性の高い高純度炭化珪素を用いるのが好ましい。この
高純度炭化珪素も含有金属不純物の含有量が0.1pp
m以下であることが好ましい。また、半導体治具材料の
成形体13とモニター用ウエハ14とは直接接触しない
ようにセットする必要がある。半導体治具材料の成形体
13とモニター用ウエハ14が物理的に接触すると傷等
による欠陥生成の要因となり、前記したOSF等の形成
による評価が正確にできなくなる。半導体治具材料の成
形体13とモニター用ウエハ14との距離は、0.5〜
20mm、さらには2〜4mm程度が好ましい。
Needless to say, the wafer boat 12 required to set the molded body 13 of the semiconductor jig material and the monitor wafer 14 needs to be of high purity, and generally quartz glass, particularly high purity. It is preferable that the content of metal impurities contained in the synthetic quartz glass is 0.1 ppm or less. Further, when the required treatment temperature is higher than 1100 ° C., it is preferable to use high-purity silicon carbide having higher heat resistance than quartz glass. This high-purity silicon carbide also contains 0.1 pp of metal impurities.
It is preferably m or less. Further, it is necessary to set the molded body 13 of the semiconductor jig material and the monitor wafer 14 so as not to come into direct contact with each other. Physical contact between the molded body 13 of semiconductor jig material and the monitor wafer 14 causes defects such as scratches, which makes it impossible to accurately evaluate the formation of the OSF and the like. The distance between the molded body 13 of the semiconductor jig material and the monitor wafer 14 is 0.5 to
It is preferably 20 mm, more preferably 2 to 4 mm.

【0022】なお、石英製のプロセスチューブ11もモ
ニター用ウエハ14への汚染を防止するためにできるだ
け高純度のものが好ましく、金属不純物含有量は0.1
ppm以下が好ましい。
The process tube 11 made of quartz is also preferably of the highest purity possible in order to prevent the monitor wafer 14 from being contaminated, and the metal impurity content is 0.1.
ppm or less is preferable.

【0023】熱処理されたモニター用ウエハ14の不純
物の分析は、モニター用ウエハ14の特性を評価するこ
とにより行うが、その方法としては、ライフタイム測定
法(μ−PCD法)、OSF法、表面酸化膜分析法等が
挙げられる。なお、必要に応じて他の特性評価を行って
も良い。
The impurities in the heat-treated monitor wafer 14 are analyzed by evaluating the characteristics of the monitor wafer 14, and the methods include the lifetime measurement method (μ-PCD method), the OSF method, and the surface. An oxide film analysis method and the like can be mentioned. It should be noted that other characteristics may be evaluated as necessary.

【0024】前記ライフタイム測定法は、レーザー光を
照射し、マイクロ波の反射強度によりモニター用ウエハ
の抵抗値を求める。そして、この値よりモニター用ウエ
ハ14中のキャリヤのライフタイムを計算する方法であ
る。また前記OSF法は、前述したモニター用ウエハ1
4にOSFを形成する方法であり、前記表面酸化膜分析
法は、酸化性雰囲気で熱処理した際に生成するモニター
用ウエハ14の酸化膜をフッ酸等の酸に溶解し、原子吸
光法により前記溶液に含有されている不純物を定量する
方法である。
In the lifetime measuring method, a resistance value of a monitor wafer is obtained by irradiating a laser beam and reflecting intensity of microwaves. Then, the lifetime of the carrier in the monitor wafer 14 is calculated from this value. Further, the OSF method is the same as the above-described monitor wafer 1
4 is a method of forming an OSF on the surface of the monitor wafer 14. In the surface oxide film analysis method, the oxide film of the monitor wafer 14 generated when heat-treated in an oxidizing atmosphere is dissolved in an acid such as hydrofluoric acid, and then the atomic absorption method is used. This is a method for quantifying impurities contained in a solution.

【0025】前記ライフタイム測定法では、キャリヤの
ライフタイムの低下という半導体特性の低下に関与する
不純物がどの程度含まれているかを評価することがで
き、OSF法では欠陥生成の要因となりやすい重金属に
よる汚染がどの場所でどの程度発生しているかを具体的
に知ることができる。また、表面酸化膜分析法では、ど
の金属がどの程度含まれているかについて、金属の種類
別に汚染の程度を知ることができ、汚染源が明確化され
る。
In the lifetime measuring method, it is possible to evaluate how much impurities are involved in deterioration of semiconductor characteristics such as deterioration of carrier lifetime. In the OSF method, heavy metals which are likely to cause defects are generated. It is possible to know specifically where and how much pollution is occurring. Further, in the surface oxide film analysis method, it is possible to know the degree of contamination by the type of metal regarding which metal is contained and to what extent, and the contamination source is clarified.

【0026】[0026]

【作用】上記構成の半導体治具材料の評価方法によれ
ば、プロセスチューブ内に設けた高純度石英又は高純度
炭化珪素からなるウエハボート上に、モニター用ウエハ
とウエハ状に加工した半導体治具材料の成形体とを併立
させて熱処理を行い、モニター用ウエハの半導体特性を
測定するので、直接接触させることにより評価用のモニ
ター用ウエハを傷付けるということがなく、高温熱処理
中に半導体治具材料から放出される金属不純物が容易か
つ高感度に検出される。また、これらの特性の測定によ
り、不純物の半導体特性への影響を明確化することが可
能となる。
According to the method for evaluating a semiconductor jig material having the above structure, a wafer for monitoring and a semiconductor jig processed into a wafer shape are mounted on a wafer boat made of high-purity quartz or high-purity silicon carbide provided in a process tube. Heat treatment is performed in parallel with the molded body of the material, and the semiconductor characteristics of the monitor wafer are measured, so there is no risk of damaging the evaluation monitor wafer by direct contact, and the semiconductor jig material during high temperature heat treatment. The metal impurities released from the can be detected easily and with high sensitivity. Further, the measurement of these characteristics makes it possible to clarify the influence of impurities on the semiconductor characteristics.

【0027】[0027]

【実施例】以下、本発明に係る半導体治具材料の評価方
法の実施例を図面に基づいて説明する。
Embodiments of the method for evaluating a semiconductor jig material according to the present invention will be described below with reference to the drawings.

【0028】[実施例1]図1に示したように、4イン
チウエハと同一の形状、寸法に加工した炭化珪素より構
成される評価用の半導体治具材料の成形体13を4イン
チのモニター用ウエハ14とともに、石英製のウエハボ
ート12(金属不純物含有量:約0.2ppm)上にセ
ットし、これらを石英製のプロセスチューブ11の中に
載置し、ドライ酸素気流中、1200℃で2時間熱処理
を行う。上記の処理を、それぞれ純度の異なる3種類
(A,B,C)の炭化珪素より構成される半導体治具材
料の成形体13につき3回行った。
[Embodiment 1] As shown in FIG. 1, a molded product 13 of a semiconductor jig material for evaluation made of silicon carbide processed into the same shape and size as a 4-inch wafer was monitored by a 4-inch monitor. A wafer boat 12 made of quartz (metal impurity content: about 0.2 ppm) is set together with the wafer 14 for use, and these are placed in the process tube 11 made of quartz, and the temperature is set to 1200 ° C. in a dry oxygen stream. Heat treatment is performed for 2 hours. The above treatment was performed three times for each of the molded bodies 13 of the semiconductor jig material composed of three types (A, B, C) of silicon carbide having different purities.

【0029】上記処理を行ったモニター用ウエハ14を
用い、ライフタイム測定法によりライフタイムを測定
し、OSF法によりモニター用ウエハ14中のOSFを
観察し、さらに表面酸化膜分析法により不純物の分析を
行った。
Using the monitor wafer 14 that has been subjected to the above-mentioned treatment, the lifetime is measured by the lifetime measurement method, the OSF in the monitor wafer 14 is observed by the OSF method, and the impurities are analyzed by the surface oxide film analysis method. I went.

【0030】なお、前記ライフタイム測定法では、測定
器機としてレオ技研製のLTA−330Aを用い、レー
ザー波長:904nm、レーザー電流値:20Aでレー
ザー光を照射し、マイクロ波の反射強度によりモニター
用ウエハ14の抵抗値を求めることによりキャリヤのラ
イフタイムを計算し、その平均値を算出した。
In the lifetime measuring method, LTA-330A manufactured by Leo Giken was used as a measuring instrument, laser light was irradiated at a laser wavelength of 904 nm and a laser current value of 20 A, and it was used for monitoring by the reflection intensity of microwaves. The carrier lifetime was calculated by obtaining the resistance value of the wafer 14, and the average value thereof was calculated.

【0031】また前記OSF法では、前記処理を行った
モニター用ウエハ14をHFで洗浄後、1000℃で1
6時間熱処理し、さらにエッチングを行った後に成長し
たOSFを顕微鏡で観察してその数を数えた。
In the OSF method, the monitor wafer 14 that has been subjected to the above-mentioned treatment is washed with HF and then at 1000 ° C. for 1 hour.
After heat treatment for 6 hours and further etching, the OSFs grown were observed with a microscope and the number thereof was counted.

【0032】また前記表面酸化膜分析法では、前記熱処
理を行い、表面を酸化させたモニター用ウエハ14にH
F蒸気を接触させることによりSiO2 膜の分解を行
い、このHF蒸気を純水で希釈、回収し、得られたフッ
酸溶液中の不純物を原子吸光法を用いて分析した。
In the surface oxide film analysis method, the heat treatment is applied to the monitor wafer 14 whose surface has been oxidized.
The SiO 2 film was decomposed by bringing it into contact with F vapor, the HF vapor was diluted with pure water and collected, and the impurities in the obtained hydrofluoric acid solution were analyzed by an atomic absorption method.

【0033】以上の分析結果を表1に示した。また、ラ
イフタイム値についての分析結果を示したモニター用ウ
エハ14上のライフタイム値分布の平面図を図2及び図
3に示した。なお、図2は材料Aについてのライフタイ
ム値分布を示した平面図であり、図3は材料Cについて
のライフタイム値分布を示した平面図である。図2及び
図3において、黒点が大きいほどライフタイムが長いこ
とを示している。
The results of the above analysis are shown in Table 1. 2 and 3 are plan views of the lifetime value distribution on the monitor wafer 14 showing the analysis results of the lifetime value. 2 is a plan view showing the lifetime value distribution of the material A, and FIG. 3 is a plan view showing the lifetime value distribution of the material C. 2 and 3, the larger the black dot, the longer the lifetime.

【0034】表1より明らかなように、半導体治具材料
の汚染性が高精度に評価できている。また、図2及び図
3に示したように、モニター用ウエハ14上のライフタ
イム値は全面にほぼ均一であった。
As is clear from Table 1, the contamination of the semiconductor jig material can be evaluated with high accuracy. Further, as shown in FIGS. 2 and 3, the lifetime value on the monitor wafer 14 was almost uniform over the entire surface.

【0035】[実施例2]実施例1で用いたものと同様
の半導体治具材料の成形体13とモニター用ウエハ14
とを、高純度炭化珪素製のウエハボート14(金属不純
物含有量:約0.2ppm)上にセットした以外は実施
例1と同一の条件で熱処理し、実施例1と同様の測定を
行った。結果を下記の表1に示した。
[Embodiment 2] Molded body 13 of semiconductor jig material and monitor wafer 14 similar to those used in Embodiment 1
Were heat-treated under the same conditions as in Example 1 except that was set on the wafer boat 14 made of high-purity silicon carbide (metal impurity content: about 0.2 ppm), and the same measurement as in Example 1 was performed. . The results are shown in Table 1 below.

【0036】炭化珪素製のウエハボート12の影響で、
モニター用ウエハ14の下部ではライフタイム値が低下
したが、その他に関しては、表1に示しているように実
施例1の結果とほぼよい一致を示した。
Due to the wafer boat 12 made of silicon carbide,
Although the lifetime value was lowered in the lower part of the monitor wafer 14, the other values were in good agreement with the results of Example 1 as shown in Table 1.

【0037】[比較例1]実施例1で用いた評価用の半
導体治具材料を加圧溶解し、原子吸光分析により不純物
金属を定量した。その結果を下記の表2に示した。
Comparative Example 1 The semiconductor jig material for evaluation used in Example 1 was melted under pressure, and the amount of impurity metal was determined by atomic absorption spectrometry. The results are shown in Table 2 below.

【0038】表2より明らかなように、試料を加圧、溶
解して、原子吸光分析法により分析する方法では、1p
pm以下での値を正確に分析することができないため、
実施例1の結果と異なり、はっきりとした値を出すこと
ができず、不純物含有量の差を明確に説明できるような
分析結果となっていない。
As is clear from Table 2, in the method of applying pressure and dissolving a sample and then analyzing by atomic absorption spectrometry, 1 p
Since the value below pm cannot be analyzed accurately,
Unlike the result of Example 1, a clear value could not be obtained, and the analysis result did not clearly explain the difference in impurity content.

【0039】[比較例2]実施例1で用いた半導体治具
材料の成形体13とモニター用ウエハ14とを石英製の
ウエハボート12上の溝に接触させてセットした以外は
実施例1と同一の条件で熱処理し、実施例1と同様の測
定を行った。結果を下記の表1に示した。
[Comparative Example 2] Example 1 except that the molded body 13 of the semiconductor jig material and the monitor wafer 14 used in Example 1 were set in contact with the groove on the wafer boat 12 made of quartz. Heat treatment was performed under the same conditions, and the same measurement as in Example 1 was performed. The results are shown in Table 1 below.

【0040】表1より明らかなように、OSFについて
は観察結果が実施例1〜2の結果と大きく異なり、評価
に信頼性がないことがわかる。
As is clear from Table 1, the observation result of OSF is significantly different from the results of Examples 1 and 2, and the evaluation is not reliable.

【0041】[比較例3]実施例1で用いたものと同様
の3種の純度の異なる炭化珪素製の半導体治具材料
(A,B,C)を用いて、実施例1で用いたウエハボー
ト12と同様の形状のウエハボートを作製した。次に、
この炭化珪素製のウエハボート12にモニター用ウエハ
14のみをにセットし、実施例1と同様に熱処理し、実
施例1と同様の測定を行った。結果を下記の表1に示し
た。また、材料Aをウエハボートとして用いて場合に得
られたモニター用ウエハ12上のライフタイム値の分布
を図4に示した。
[Comparative Example 3] The wafer used in Example 1 was prepared by using three kinds of semiconductor jig materials (A, B, C) made of silicon carbide having different purities similar to those used in Example 1. A wafer boat having the same shape as the boat 12 was manufactured. next,
Only the monitor wafer 14 was set in the wafer boat 12 made of silicon carbide, heat-treated in the same manner as in Example 1, and the same measurement as in Example 1 was performed. The results are shown in Table 1 below. The distribution of lifetime values on the monitor wafer 12 obtained when the material A was used as a wafer boat is shown in FIG.

【0042】表1より明らかなように、半導体治具材料
より構成されるウエハボート12とモニターウエハ14
との距離が離れているので、不純物金属による汚染が少
なく、各材料による金属不純物含有量の差がほとんどわ
からない。また、図4に示したように、半導体治具材料
による汚染はモニター用ウエハ14の下部に、また炉内
雰囲気による汚染はモニター用ウエハ周辺部に限定され
ており、半導体治具材料からの汚染の評価をはっきり行
うことができなかった。
As is clear from Table 1, the wafer boat 12 and the monitor wafer 14 made of the semiconductor jig material.
Since there is a large distance from, the contamination by the impurity metal is small, and the difference in the metal impurity content between the materials is almost unknown. Further, as shown in FIG. 4, contamination by the semiconductor jig material is limited to the lower portion of the monitor wafer 14, and contamination by the atmosphere in the furnace is limited to the peripheral portion of the monitor wafer. Could not be evaluated clearly.

【0043】[0043]

【表1】 [Table 1]

【0044】[0044]

【表2】 [Table 2]

【0045】以上のように、上記実施例で用いたライフ
タイム測定法、OSF法及び表面酸化膜分析法を用いる
ことにより、高温熱処理中に半導体治具材料から放出さ
れる金属不純物を容易かつ高感度に検出することができ
るとともに半導体特性への影響を明確化することが可能
となる。
As described above, by using the lifetime measuring method, the OSF method and the surface oxide film analyzing method used in the above-mentioned embodiment, the metal impurities released from the semiconductor jig material during the high temperature heat treatment can be easily and increased. The sensitivity can be detected and the influence on the semiconductor characteristics can be clarified.

【0046】[0046]

【発明の効果】以上詳述したように本発明に係る半導体
治具材料の評価方法にあっては、プロセスチューブ内に
設けた高純度石英又は高純度炭化珪素からなるウエハボ
ート上に、モニター用ウエハとウエハ状に加工した半導
体治具材料の成形体とを併立して熱処理を行い、モニタ
ー用ウエハの半導体特性を測定するので、直接接触させ
ることにより評価用のモニター用ウエハを傷付けるとい
うことがなく、高温熱処理中に半導体治具材料から放出
される金属不純物を容易かつ高感度に検出することがで
きるとともに半導体特性への影響を明確化することが可
能となり、半導体の製造歩留および信頼性向上に寄与す
るところが大きい。
As described above in detail, in the method for evaluating a semiconductor jig material according to the present invention, a wafer boat made of high-purity quartz or high-purity silicon carbide provided in a process tube is used for monitoring. Since the wafer and the molded body of the semiconductor jig material processed into a wafer shape are subjected to heat treatment in parallel to measure the semiconductor characteristics of the monitor wafer, it is possible to damage the monitor wafer for evaluation by direct contact. In addition, it is possible to easily and highly sensitively detect metal impurities emitted from semiconductor jig materials during high-temperature heat treatment, and to clarify the effect on semiconductor characteristics. It greatly contributes to the improvement.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る半導体治具材料の評価方法を模式
的に示した断面図である。
FIG. 1 is a sectional view schematically showing a method for evaluating a semiconductor jig material according to the present invention.

【図2】実施例1の半導体治具材料Aにつき、熱処理に
より得られたモニター用ウエハのライフタイム値分布を
示した平面図である。
2 is a plan view showing a lifetime value distribution of a monitor wafer obtained by heat treatment of the semiconductor jig material A of Example 1. FIG.

【図3】実施例1の半導体治具材料Cにつき、熱処理に
より得られたモニター用ウエハのライフタイム値分布を
示した平面図である。
FIG. 3 is a plan view showing a lifetime value distribution of a monitor wafer obtained by heat treatment for the semiconductor jig material C of Example 1.

【図4】比較例3の半導体治具材料Aにつき、熱処理に
より得られたモニター用ウエハのライフタイム値分布を
示した平面図である。
FIG. 4 is a plan view showing a lifetime value distribution of a monitor wafer obtained by heat treatment of the semiconductor jig material A of Comparative Example 3.

【符号の説明】[Explanation of symbols]

11 石英製のプロセスチューブ 12 ウエハボート 13 半導体治具材料の成形体 14 モニター用ウエハ 11 Quartz Process Tube 12 Wafer Boat 13 Semiconductor Jig Material Molded Body 14 Monitor Wafer

───────────────────────────────────────────────────── フロントページの続き (72)発明者 小池 康夫 佐賀県杵島郡江北町大字上小田2201番地 住友シチックス株式会社九州事業所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuo Koike 2201 Kamioda, Kamikita-cho, Kijima-gun, Saga Sumitomo Sitix Co., Ltd. Kyushu Office

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 プロセスチューブ内に設けた高純度石英
又は高純度炭化珪素からなるウエハボート上に、モニタ
ー用ウエハとウエハ状に加工した半導体治具材料の成形
体とを併立させて熱処理を行い、モニター用ウエハの特
性を測定することを特徴とする半導体治具材料の評価方
法。
1. A wafer boat made of high-purity quartz or high-purity silicon carbide provided in a process tube, a monitor wafer and a molded product of a semiconductor jig material processed into a wafer are placed side by side for heat treatment. A method for evaluating a semiconductor jig material, which comprises measuring the characteristics of a monitor wafer.
JP32362593A 1993-12-22 1993-12-22 Evaluation method of semiconductor jig material Expired - Fee Related JP2847228B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32362593A JP2847228B2 (en) 1993-12-22 1993-12-22 Evaluation method of semiconductor jig material

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32362593A JP2847228B2 (en) 1993-12-22 1993-12-22 Evaluation method of semiconductor jig material

Publications (2)

Publication Number Publication Date
JPH07183347A true JPH07183347A (en) 1995-07-21
JP2847228B2 JP2847228B2 (en) 1999-01-13

Family

ID=18156828

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32362593A Expired - Fee Related JP2847228B2 (en) 1993-12-22 1993-12-22 Evaluation method of semiconductor jig material

Country Status (1)

Country Link
JP (1) JP2847228B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010040813A (en) * 2008-08-06 2010-02-18 Shin Etsu Handotai Co Ltd Method of evaluating silicon substrate, method of detecting contamination, and method of manufacturing epitaxial substrate
JP2010040688A (en) * 2008-08-04 2010-02-18 Shin Etsu Handotai Co Ltd Method of evaluating silicon substrate, method of detecting contamination, and method of manufacturing epitaxial substrate
JP2012004284A (en) * 2010-06-16 2012-01-05 Shin Etsu Handotai Co Ltd Method of evaluating cleanness of cvd furnace and method of manufacturing epitaxial substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010040688A (en) * 2008-08-04 2010-02-18 Shin Etsu Handotai Co Ltd Method of evaluating silicon substrate, method of detecting contamination, and method of manufacturing epitaxial substrate
JP2010040813A (en) * 2008-08-06 2010-02-18 Shin Etsu Handotai Co Ltd Method of evaluating silicon substrate, method of detecting contamination, and method of manufacturing epitaxial substrate
JP2012004284A (en) * 2010-06-16 2012-01-05 Shin Etsu Handotai Co Ltd Method of evaluating cleanness of cvd furnace and method of manufacturing epitaxial substrate

Also Published As

Publication number Publication date
JP2847228B2 (en) 1999-01-13

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