JPH0718187Y2 - Electronic device including CMOS circuit - Google Patents

Description

[Detailed description of the device]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device including a CMOS circuit and a circuit for preventing the CMOS circuit from latching up.

[0002]

2. Description of the Related Art In a conventional electronic device, a CMOS-LSI is often used because of its low power consumption and easy high integration.

However, the CMOS-LSI is inferior to the bipolar LSI in terms of its speed and driving ability, and has a drawback that a latch-up phenomenon is apt to occur structurally. On the other hand, the bipolar LSI represented by ECL is
Although it has high performance such as high speed and high driving ability, it has a drawback that it consumes a large amount of power and is difficult to be highly integrated. Therefore, as a complement to the drawbacks that have the advantages of both bipolar and CMOS, Bi that integrates a bipolar transistor and a MOS transistor on one chip
CMOS gate arrays have been developed.

[0004]

By the way, the above-mentioned C
The latch-up phenomenon, which is a phenomenon peculiar to MOS circuits, is caused by excessive noise, accidental surge or other excessive voltage or current being applied to the input / output terminals of the CMOS circuit, or a sudden change in the power supply amplitude during normal operation. If you do, Vc
It is known that an abnormal current flows between c and GND, and even if the disturbance signal is cut off, the abnormal current continues, and the CMOS circuit is destroyed.

Therefore, the CM whose power is always ON
When an OS-LSI and a power supply of another CMOS-LSI, which is ON / OFF controlled through a power supply control circuit by a command signal from the CMOS-LSI, are connected to a common system bus, the power supply is turned ON / OFF. C that is always in the power-on state due to noise generated with
Since such a latch-up phenomenon occurs in the MOS-LSI and the CMOS-LSI may be destroyed eventually, such connection has been prohibited.

Therefore, an object of the present invention is to provide an electronic device which enables the above-mentioned connection and realizes high-density mounting of a printed circuit board.

[0007]

[MEANS FOR SOLVING THE PROBLEMS] The present invention is always on.
A latch-up prevention circuit is provided between the CMOS circuit in the state and the system bus, and this latch-up prevention circuit is provided along with the power supply control circuit of another CMOS circuit.
It is characterized by being configured by an i-CMOS gate array.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the basic structure of an electronic device including a CMOS circuit according to the present invention. The system bus 1 has a CMOS-LSI 2 which is always in a power ON state.
Are connected via the latch-up prevention circuit 3. A power supply 4 for another CMOS-LSI and a power supply control circuit 5 for the other CMOS-LSI are connected to the system bus 1. The power supply 4 is controlled by a control signal output from the CMOS-LSI 2 to the system bus 1. ON / OFF control is performed through the power supply control circuit 5. Further, a watchdog timer circuit 6 for monitoring the operation of the software of this electronic device is connected to the system bus 1.

The latch-up prevention circuit 3 is a CMOS
-When the LSI 2 does not need to access the outside, the signal line between the LSI and the system bus 1 is cut off so that an unnecessary signal or noise is not input to the CMOS-LSI 2 from the outside.
It prevents the latch up. In the present invention, in order to achieve high-density mounting on the printed circuit board, as shown in FIG.
And a watchdog timer 6 are integrated as a Bi-CMOS gate array 7.

FIG. 3 is a circuit diagram of the latch-up prevention circuit 3. The signal line 9 connected between the input / output terminal 8 of the CMOS-LSI 2 and the system bus 1 is connected in parallel in opposite directions. Two two 3-state TTLs 10 and 11 are provided, and the outputs of the AND gates 12 and 13 are applied to the control input terminals of these three-state TTLs 10 and 11, respectively. 2 of AND gate 12
A write request signal W and an enable signal are given to one input terminal from the CMOS-LSI 2, and a read request signal R and an enable signal are given from the CMOS-LSI 2 to the other two input terminals of the AND gate 13. It is designed to be used. Therefore, CMOS-LS
If the request from I2 is to write data, the 3-state TTL 10 is selected by the output of the AND gate 12, and the data is written to the system bus 1.
If the request from the LSI 2 is to read data from the memory, the 3-state TTL 11 is selected by the output of the AND gate 13 and the data is written to the system bus 1.

A pull-up resistor 15 is connected between the input / output terminal 8 of the CMOS-LSI 2 and the power supply line 14 to prevent noise from being input to the input / output terminal 8 from the system bus 1. At the same time, the voltage level of the input / output terminal 8 is stabilized. Furthermore, CMOS-
A signal line 17 for outputting a command signal from the CMOS-LSI 2 to the power supply control circuit 5 is connected between the other output terminal 16 of the LSI 2 and the system bus 1.
A third 3-state TTL 18 having a control input terminal to which an enable signal is applied is provided on the 7. The latch-up prevention circuit 3 according to the present embodiment is provided with the pull-up resistor 15 and the 3-state TTL 18 as described above, so that the CMOS-LSI 2 is prevented from latching up due to noise caused by turning the power supply 4 on and off. As a result, the CMOS-L with the power always on
SI2 and other CMOS whose power is turned on and off
Enables interface with LSI. Also,
In the present embodiment, although the latch-up prevention circuit 3 is provided between the system bus 1 and the CMOS-LSI 2, the latch-up prevention circuit 3 together with the power supply control circuit 5 and the watchdog timer 6 are Bi-CMOS gates. The array 7 reduces the number of components and enables high-density mounting.

[0013]

According to the present invention, the CMOS circuit can operate independently, and at the same time, the power of other CMOS circuits is turned on.
・ OFF is also possible. Moreover, latch-up of the CMOS circuit is prevented, and the CMOS circuit can be used safely. In addition, the latch-up prevention circuit is connected to other
By using a CMOS gate array, the number of parts can be reduced and high-density mounting can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of an electronic device including a CMOS circuit according to the present invention.

FIG. 2 is a block diagram of a device of the present invention in which a part of FIG. 1 is formed into a gate array.

FIG. 3 is a circuit diagram of a latch-up prevention circuit.

[Explanation of symbols]

 1 system bus 2 CMOS-LSI 3 latch-up prevention circuit 4 power supply of other CMOS-LSI 5 power supply control circuit 6 watchdog timer circuit 7 Bi-CMOS gate array 8 CMOS-LSI input / output terminals 10, 11, 18 3 states TTL 12, 13 AND gate 15 Pull-up resistor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical display location H03K 19/08 A 8839-5J 19/0948 (72) Creator Matsuo Sato Shinmeidai, Hamura-cho, Nishitama-gun, Tokyo 2-1, 1-1 Kokusai Electric Co., Ltd. Hamura Factory (56) Reference Japanese Patent Laid-Open No. 2-5457 (JP, A)

Claims (1)

[Scope of utility model registration request] 1. A CMOS circuit, which is always in a power-on state, and an O circuit through the power supply control circuit by the CMOS circuit.
The power supply of another CMOS circuit which is N / OFF controlled is connected to a common system bus, and this C bus is connected between this system bus and the CMOS circuit which is always on.
A circuit for preventing latch-up of the MOS circuit is provided,
An electronic device including a CMOS circuit, wherein the latch-up prevention circuit constitutes a Bi-CMOS gate array together with the power supply control circuit.