JPH07177041A - Serial/parallel conversion circuit - Google Patents

Abstract

PURPOSE:To attain the integration of a circuit and the reduction of a scale and to reduce a cost by constituting a line memory part of a shift register. CONSTITUTION:R, G, and B data transferred from an A/D conversion circuit at the front stage are converted into serial data R1, G1, B1, R2, G2, B2,... via a data conversion part 40, and stored in a first line memory part 43 sequentially by a shift pulse from a first shift pulse generating part 41. After data of one horizontal period are stored in all the shift registers in a memory part 43, six pulses are generated from the generating part 41 and a second shift pulse generating part 42 until the next horizontal period arrives, and they are transferred from the memory part 43 to a second line memory part 44. In the next horizontal period, the R, G, and B data are stored sequentially in the memory part 43 similarly, and the shift pulse is generated from the generating part 42, and the R, G, and B data stored in the memory part 44 are outputted to a modulation driving circuit in accordance with each electrode sequentially.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial / parallel conversion circuit used in an electrode driving circuit of a matrix driving type image display device.

[0002]

2. Description of the Related Art In recent years, a matrix drive system has been generally used for a thin display, and its drive block is being formed into an LSI aiming at low cost, downsizing, and low power consumption.

Prior to the description of the conventional serial-parallel conversion circuit used in the electrode drive circuit of the matrix drive type video display device, an example of the matrix drive type video display device will be described with reference to FIGS. 8 and 9. FIG. 8 is a block diagram of the driving device, FIG. 9A is a display panel, and FIG. 9B is a timing diagram of each electrode.

The input RGB video signal is sequentially converted into digital data by the A / D conversion circuit 20, and the serial / parallel conversion circuit 21 accumulates the data successively sent for one horizontal period and parallels the number of electrodes. Output as data. The data output in parallel drives the electrodes of the display panel 23 by the modulation drive circuit 22.

The display panel 23 drives a plurality of colors with one electrode. As shown in FIG. 9, one electrode drives two dots of three colors of R, G, B in one horizontal period in a time division manner. That is, each electrode simultaneously drives the same color at a certain time (that is, when the first electrode drives R1, the second electrode drives R3 and the nth electrode drives R2n-1). In this way, each electrode drives six colors in one horizontal period to display an image.

A conventional serial-parallel conversion circuit used in the above matrix drive type video display device will be described with reference to FIG.

In FIG. 10, reference numeral 31 denotes a first line memory section, which is composed of a plurality of flip-flop groups and sequentially stores RGB data for one horizontal period. 30 is a latch pulse generator, which uses the horizontal synchronization signal as an initialization signal,
A latch pulse is generated for each flip-flop group of the first line memory unit 31. 33 is the second
The line memory unit is composed of the same number of flip-flops as the first line memory unit 31, and the output data of the first line memory unit 31 is transferred and latched by a horizontal synchronizing signal. A switching unit 34 is composed of a plurality of 6-input 1-output selectors (34a to 34n), and outputs data (R, G, B, R, G,) from the second line memory unit 33.
B) The data of one color in the group is switched and selected. Three
A switching signal generator 5 generates a switching signal to the switching unit 34 by using the horizontal synchronizing signal as an initialization signal.

Next, the operation of the above configuration will be described with reference to FIGS.
This will be described with reference to FIG. The RGB data transferred from the A / D conversion circuit 20 is transferred to the first line memory in the latch pulse generator 30 by the transfer timing from the A / D conversion circuit 20 and the latch pulses 30a to 30n generated by the horizontal synchronizing signal. Data for one horizontal period is sequentially written in the unit 31. The data written in the first line memory unit 31 is transferred to the second line memory unit 33 all at once by the next horizontal synchronization signal after the writing to all the flip-flops of the first line memory unit 31 is completed,
Remembered. The data stored in the second line memory unit 33 is converted into R, G, B, R, respectively by the switching unit 34.
G and B are sequentially switched by the switching signal from the switching signal generator 35 and output to the modulation drive circuit 22 in the next stage. In this way, the first in one horizontal period
The six colors R, G, B, R, G, and B are simultaneously driven in time division by the electrodes to the nth electrode.

[0009]

As described above, in the conventional serial-parallel conversion circuit, the first line memory unit 31 and the second line memory unit 33 whose constituent elements are flip-flops for one horizontal period, Since it is the switching unit 34 of the 6-input 1-output selector group corresponding to the number of electrodes, there is a problem that the circuit scale is large and the cost is high. For example, in the case of performing full-color display of 640 dots per line of 8 bits for each RGB, the flip-flop alone has a gate scale that greatly exceeds 100,000 gates.

In view of the above-mentioned conventional problems, the serial-parallel conversion circuit of the present invention integrates the circuit and reduces the scale thereof, and enables a significant cost reduction.

[0011]

In order to solve the above-mentioned problems, a first line memory unit composed of a plurality of shift registers for storing RGB image signals for one horizontal period and the line memory unit for one horizontal period are provided. After the completion of storage of the signal, the signal is transferred to and stored by the next horizontal period. The second line memory section is composed of the same number of shift registers as the first line memory section.

Further, the serial conversion circuit of the present invention comprises a plurality of RAs.
The video data is sequentially written in one horizontal period and read in the next horizontal period after the writing is completed.
One of a line memory unit configured by a plurality of RAMs for storing RGB signals for one pixel at one address and repeating writing and reading operations for each horizontal period; and video data read from the line memory unit. A data switching unit that selects and outputs data of one color and a plurality of storage elements such as flip-flops are connected in parallel to the output data line of the data switching unit. A first display memory unit for respectively storing the data selected by the first display memory unit and the same number of storage elements as the first display memory unit, and after storing the data in all the storage elements of the first display memory unit, And a second display memory unit that re-stores each output data for modulation drive processing.

The serial conversion circuit of the present invention is composed of a shift register or the like, sequentially stores an input RGB data string, converts one word into a data string composed of a plurality of same color data, and outputs the data string. Data converter and multiple R
The data from the data conversion unit composed of AM is 1
A horizontal line write operation, a read operation is performed in the next horizontal time period after completion of the write operation, and a line memory unit that repeats the write operation and the read operation every horizontal period, and a plurality of storage elements such as flip-flops are output data lines of the line memory unit. And a display memory unit for storing read data from the line memory unit for modulation drive processing.

[0014]

In the serial-parallel conversion circuit of the present invention, the line memory unit, which is conventionally constituted by the flip-flop, is configured as the shift register, so that the switching unit can be reduced and the circuit scale can be eliminated. The cost can be reduced.

In the serial-parallel conversion circuit of the present invention, the circuit can be integrated by replacing the line memory unit, which is conventionally composed of flip-flops, with a RAM, and is composed of flip-flops for one horizontal period in the related art. The circuit size can be reduced and the cost can be significantly reduced by using the second line memory unit and the switching circuit, which is composed of the switching circuit corresponding to the number of electrodes, to the two flip-flop groups corresponding to the number of electrodes. It becomes.

In the serial-parallel conversion circuit of the present invention, the circuit can be integrated by replacing the line memory unit, which is conventionally constituted by flip-flops, with a RAM, and is constituted by flip-flops for one horizontal period in the past. The circuit size can be reduced and the cost can be drastically reduced by using the second line memory unit and the switching circuit, which is composed of the switching circuit for the number of electrodes, as a switching unit, which is composed of one flip-flop group for the number of electrodes. It becomes.

[0017]

【Example】

(Embodiment 1) A first embodiment of a serial / parallel conversion circuit of the present invention will be described below with reference to FIGS. 1, 8 and 9.

In FIG. 1, reference numeral 40 denotes a data conversion unit which converts the RGB data transferred from the A / D conversion units of all stages into R1 and R1.
G1, B1, R2, G2, B2. ． In this way, it is converted into serial data and output. Reference numeral 43 denotes a first line memory unit, which has six stages (one electrode is R, G, B, R, G, B.
6 color shift registers) are connected in series for the number of electrodes, and each group is composed of a shift register group capable of taking out an output from the 6th stage, and RGB data is sequentially stored for one horizontal period.

Reference numeral 41 denotes a first shift pulse generator which outputs a shift pulse for the first line memory 43 based on the horizontal synchronizing signal. A second line memory unit 44 is composed of a shift register group of six stages, each output from the first line memory unit 43 is used as each input of the shift register group, and the output is a modulation drive circuit corresponding to each electrode. By connecting to 22 the entire data of the first line memory section 43 is saved for display. A second shift pulse generator 42 generates a shift pulse to the second line memory 44 based on the horizontal synchronizing signal.

Next, the operation of the above configuration will be described with reference to FIG.
This will be described with reference to FIGS. 2, 8 and 9.

The RGB data transferred from the A / D conversion circuit 20 in the preceding stage is passed through the data conversion section 40 to R1, G1, B
1, R2, G2, B2 ,. ． Converted to serial data of
The shift pulses from the first shift pulse generating section 41 are sequentially stored in the first line memory section 43. After the data of one horizontal period is stored in all the shift registers of the first line memory unit 43, six shifts from the first shift pulse generating unit 41 and the second shift pulse generating unit 42 until the next horizontal period. A pulse is generated (A in FIG. 2)
Parts) and the first line memory unit 43 are sequentially transferred to the second line memory unit 44. That is, R1, G1, B1, R2, G2, B2 stored in the first line memory unit 43
Data is sequentially transferred from the output of 43a to the second line memory section 44 and stored therein. Similarly, R2n-1,
The data of G2n-1, B2n-1, R2n, G2n, B2n are sequentially transferred from the output of 43n to the second line memory unit 44, and the data stored in all the first line memory units 43 is the second line memory unit. It is transferred to 44 and stored.

In the next horizontal period, RGB data are sequentially stored in the first line memory section 43 in the same manner as described above,
In the line memory section 44, a shift pulse (section B in FIG. 2) is generated by the second shift pulse generating section 42, and the RGB data stored in the second line memory section 44 is sequentially R,
G, B, R, G, B are sequentially output to the modulation drive circuit corresponding to each electrode, and two dots of R, G, B, R, G, B are respectively formed in the first electrode to the nth electrode in one horizontal period. Six colors are driven simultaneously in time division.

As described above, in the serial-parallel conversion circuit of the present invention, attention is paid to the fact that one electrode drives a plurality of dots and a plurality of colors (two dots and 6 colors in the above example) in one horizontal period in a time division manner. Line memory unit 43 and second line memory unit 44
Is a shift register configuration, and the first line memory unit 43
The transfer circuit from the second line memory unit 44 to the second line memory unit 44 is performed with six shift pulses, so that the conventionally required switching circuit can be eliminated, the circuit scale can be reduced, and the cost can be reduced. Is.

(Embodiment 2) Next, a second embodiment of the serial / parallel conversion circuit of the present invention will be described with reference to FIGS. 3, 4, 8 and 9.

In FIG. 3, reference numeral 1 is a line memory unit, which is an RG.
B data is sequentially stored for one horizontal period, and the first RAM 2 and the first RAM are in a read state in the next horizontal period after the storage is completed.
The second RAM 3 operates in the same manner as 2 and is in the read state when the first RAM 2 is in the write state and is in the write state when the first RAM 2 is in the read state. Both RAMs repeat the write and read operations every horizontal period. Is.

Reference numeral 4 denotes a write address generating section which is composed of a counter or the like and generates write addresses of the first RAM 2 and the second RAM 3 from the transfer clock. Reference numeral 5 denotes a read address generation unit, which is composed of a counter and the like, and is used for the first RAM during the display period of the electrode display timing signal.
2 and the read address of the second RAM 3 are generated. A first address switching unit 6 switches the address from the write address generation unit 4 and the address from the read address generation unit 5, and outputs the address of the first RAM 2. A second address switching unit 7 switches the address from the write address generation unit 4 and the address from the read address generation unit 5, and outputs the address of the second RAM 3.

An address switching signal generator 8 generates a switching signal to the first address switching unit 6 and the second address switching unit 7 according to the horizontal synchronizing signal. A data switching unit 9 selects and outputs only the color data to be actually time-division driven among the RGB data read from the line memory unit 1. A data switching signal generator 10 generates a switching signal to the data switching unit 9 according to the address data of the read address generator 5. Reference numeral 11 denotes a first display memory unit which is composed of flip-flops corresponding to the number of electrodes, and latches and stores the data selected by the data switching unit 9.

Reference numeral 12 is a latch pulse generating section for generating latch pulses 12a to 12n of the first display memory section 11 according to the read address of the read address generating section 5. A second display memory unit 13 is composed of flip-flops corresponding to the number of electrodes, and temporarily stores the output data 11a to 11n from the first display memory unit 11 for outputting to the modulation drive circuit 22. Reference numeral 14 denotes a transfer pulse generation unit, which stores data in all the flip-flops of the first display memory unit 11 and then the second display memory unit 13
A pulse for transferring data to is generated by the electrode display timing signal.

Next, the operation of the above configuration will be described. A /
The RGB data for one horizontal period transferred from the D conversion circuit 20 is generated by the write address generation unit 4, and the address data generated according to the transfer clock from the A / D conversion circuit 20 is transmitted via the first address switching unit 6. , The first RAM2
To be sequentially written in the first RAM 2. When the writing for one horizontal period is completed, the first RAM 2 is in the read state and the second RAM 3 is in the written state by the signal from the address switching signal generating section 8, and in the next horizontal period, the same write operation is performed by the second RAM 3 as described above. Is repeated.

On the other hand, the first RAM 2 in the read state
The RGB data is sequentially read by the address generated by the read address generating unit 5. Of the R1, G1, B1 data read first, only the R1 data is selected in the data switching section 9 by the signal from the data switching signal generating section 10, and the first display memory is generated by the latch pulse 12a from the latch pulse generating section 12. It is stored in the flip-flop 11A of the unit 11. Similarly, the R3, G3, B3 data read out second from the first RAM2 is also R3.
Only the selected pulse is stored in the flip-flop 11B by the latch pulse 12b.

Similarly, the Nth read data R is read.
R2n-1 data of 2n-1, G2n-1, and B2n-1 are stored in the flip-flop 11N by the latch pulse 12n. R1, R3 ,. ． , R2n-1 is stored in all the flip-flops of the first display memory unit 11, and then the data of the first display memory unit 11 is changed by the transfer pulse (C part of FIG. 4) from the transfer pulse generating unit 14. All are transferred and stored in the second display memory unit 13. That is, the data 11a of the 11A flip-flop
Is the 11A data 11 in the 13A flip-flop.
n is transferred to 13N and stored.

Outputs 13a, 13 of the second display memory unit 13
b ,. ． , 13n are input to the modulation drive circuit 22 in the subsequent stage, so that R1, R on the display panel 23
3 ,. ． , R2n-1 are simultaneously driven (state <1> in FIG. 4).

R1, R3 ,. ． , R2n-1 data are transferred to the second display memory unit 13, and the R1, G1, B1 data read from the line memory unit 1 is selected by the data switching unit 9 only G1 data and the latch pulse 1
The flip-flop 1 of the first display memory unit 11 by 2a
It is stored in 1A. After that, the above operation is repeated, and G
1, G3 ,. ． , G2n-1 are transferred to the second display memory unit 13 by the transfer pulse (D part in FIG. 4) after the completion of storage in all the flip-flops of the first display memory unit 11, and G1, G3 ,. ． , G2n
-1 is driven (state <2> in FIG. 4).

The above operation is repeated for R, G, and B, and R, G, and R are respectively applied to the first electrode to the nth electrode in one horizontal period.
6 colors of 2 dots of B, R, G and B are sequentially and simultaneously driven in time division.

As described above, the serial-parallel conversion circuit of the present invention focuses on the fact that one electrode drives a plurality of dots and a plurality of colors (two dots and 6 colors in the above example) in one horizontal period in a time division manner. Since the color data to be driven next is read during the modulation drive (display) of data, the serial-parallel conversion circuit, which was conventionally composed of flip-flops for two horizontal periods, is used in the RAM and the flip-flops 2 for the number of electrodes. Since it can be configured in stages, the circuit can be integrated and the scale can be reduced, and the cost can be significantly reduced by about 50% compared with the conventional one.

(Third Embodiment) Next, a third embodiment of the serial-parallel conversion circuit of the present invention will be described with reference to FIGS. 5, 6, 7, and 8.
This will be described with reference to FIG. The same parts as those in the second embodiment are designated by the same reference numerals and the description thereof will be omitted.

Reference numeral 15 denotes a data conversion unit, which is composed of a shift register or the like, and sequentially stores the RGB data string (15a in FIG. 6) transferred from the A / D conversion circuit 202 by its transfer clock, and one word consists of 3 words. The data is converted into a data string (15b in FIG. 6) composed of the same color data for dots and written in the first RAM 2 or the second RAM 3 of the line memory unit 1.

Reference numeral 16 is a read address generator, which is composed of a counter or the like, and is used for the first RAM 2 and the second RAM 2 during the display blanking period (drive stop period) of the electrode display timing signal.
The read address of the RAM 3 is generated. 1
Reference numeral 7 denotes a display memory unit, which is composed of flip-flops corresponding to the number of electrodes, and sequentially latches and stores the data read from the line memory unit 1 for outputting to the modulation drive circuit 22. Reference numeral 18 denotes a latch pulse generator, which latches pulses (18a, 18b, ..., 18) of the display memory unit according to the read address of the read address generator 16.
n) is generated.

Next, the operation of the above configuration will be described. A /
The RGB data string transferred by the D conversion circuit 20 (see FIG. 6).
15a) is a data string (15 in FIG. 6) in which one word is composed of data of the same color for 3 dots by the data conversion unit 15.
It is converted into b) and sequentially written in the first RAM 2. When the writing of the data for one horizontal period is completed, the second RAM 3 enters the same write mode in the next horizontal period and the first R
AM2 is in the read mode. After that, the above operation is repeated every horizontal period.

In the read mode operation, the data is sequentially read from the line memory unit 1 by the address generated by the read address generating unit 16 during the display blanking period of the electrode display timing signal (hatched portion in FIG. 7).
The first read R1, R3, R5 data is stored in the flip-flop 17A of the display memory unit 17 by the latch pulse 18a from the latch pulse generation unit 18. Two
Similarly, the R7, R9, and R11 data read out next is also stored in the flip-flop 17B of the display memory unit 17 by the latch pulse 18b. Similarly, during the display blanking period (portion A in FIG. 7), R data is read out to all grip flops of the display memory unit 17, and when stored, its outputs 17a, 17b ,. ． , 17n are input to the modulation drive circuit 22 in the subsequent stage, and R1. R3 ,. ． , R2n-1 drive simultaneously (Fig. 7
Section B).

After the display of the R data is completed, the next display blanking period (C in FIG. 7) is the same as the above for G1 and G.
3 ,. ． , G2n-1 are read out, and G data is displayed during the display period (D portion in FIG. 7). The above operation is repeated for R, G, and B, and two dots 6 of R, G, B, R, G, and B are respectively formed on the first electrode to the n-th electrode in one horizontal period.
Colors are time-division driven.

As described above, the serial-parallel conversion device of the present invention reads out the next display data during the blanking period of the electrode display, so that the serial-parallel conversion circuit which has conventionally been composed of flip-flops for two horizontal periods. Can be composed of a RAM and one flip-flop corresponding to the number of electrodes, so that the circuit can be integrated and the scale can be reduced, and the cost can be further reduced.

[0043]

As described above, since the serial-parallel conversion circuit of the present invention enables the configuration of two flip-flops for one horizontal period, the circuit scale can be reduced and the cost can be reduced. Has the effect.

Further, since the serial-parallel conversion circuit of the present invention can be configured with a RAM and two flip-flops corresponding to the number of electrodes, the circuit can be integrated and the scale can be reduced, and the cost can be greatly reduced. It has the effect that

Further, the serial-parallel conversion circuit of the present invention is a RAM
Since it is possible to configure a single flip-flop for the number of electrodes, it is possible to further reduce the circuit scale and further reduce costs.

[Brief description of drawings]

FIG. 1 is a block diagram of a serial-parallel conversion circuit according to an embodiment of the first invention of the present invention.

FIG. 2 is a diagram showing a timing chart of the serial-parallel conversion circuit.

FIG. 3 is a block diagram of a serial-parallel conversion circuit in an embodiment of the second invention of the present invention.

FIG. 4 is a diagram showing a timing chart of the serial-parallel conversion circuit in the embodiment.

FIG. 5 is a block diagram of a serial-parallel conversion circuit in an embodiment of a third invention of the present invention.

FIG. 6 is a diagram showing a timing chart at the time of writing in the serial-parallel conversion circuit.

FIG. 7 is a diagram showing a timing chart at the time of reading of the serial-parallel conversion circuit.

FIG. 8 is a block diagram showing an example of an electrode drive circuit of a matrix drive type image display device.

9A is a diagram showing a part of a display panel of a matrix drive type video display device. FIG. 9B is a diagram showing display timing of electrodes of the matrix drive type video display device.

FIG. 10 is a block diagram showing a configuration of a serial-parallel conversion circuit in a conventional example.

[Explanation of symbols]

 1 line memory part 2 1st RAM 3 2nd RAM 5 read address generation part 9 data switching part 11 1st display memory part 13 2nd display memory part 16 read address generation part 17 display memory part 43 1st line memory part 44 2nd line Memory part

Front page continued (72) Inventor Kazuto Tanaka 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Tetsuji Miwa 1006 Kadoma, Kadoma City Osaka Prefecture Matsushita Electric Industrial Co., Ltd. Inventor Tadayuki Masumori 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (3)

[Claims] 1. A first line memory section composed of a plurality of shift registers for storing RGB image signals for one horizontal period, and the next horizontal period after the line memory section has completed storing signals for one horizontal period. A serial-parallel conversion circuit including a first line memory unit for storing the signals of the one horizontal period portion transferred up to and including a second line memory unit composed of the same number of shift registers. 2. The video data is sequentially written in one horizontal period,
A line memory unit that is configured by a plurality of random access memories that store RGB signals for one pixel at one address and that performs reading in the next horizontal period after completion of writing, and that repeats writing and reading operations for each horizontal period,
A read address generation unit that generates an address for reading data from the line memory unit during an electrode drive period, and one color data of the video data read from the line memory unit is selectively selected and output. A data switching unit, a first display memory unit configured to have a plurality of storage elements connected in parallel to output data lines of the data switching unit, and each storing data selected by the data switching unit; A second display memory including the same number of storage elements as the first display memory section, and re-storing each output data for modulation drive processing after data has been stored in all storage elements of the first display memory section And parallel-to-parallel conversion circuit including a section. 3. A data conversion unit for sequentially storing an input RGB data string, converting one word into a data string composed of a plurality of same color data, and outputting the data string, and comprising a plurality of random access memories. The data from the data conversion unit is written in one horizontal period, read out in the next horizontal period after the writing is completed, and the line memory unit that repeats the writing and reading operation every one horizontal period, and the data from the line memory unit in the drive stop period And a plurality of storage elements are connected in parallel to the output data line of the line memory unit, and the read data from the line memory unit is modulated and driven. A serial-to-parallel conversion circuit configured by a display memory unit that stores for processing.