CN100363971C - Digital data driver and liquid-crystal displaying device - Google Patents
Digital data driver and liquid-crystal displaying device Download PDFInfo
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- CN100363971C CN100363971C CNB031386938A CN03138693A CN100363971C CN 100363971 C CN100363971 C CN 100363971C CN B031386938 A CNB031386938 A CN B031386938A CN 03138693 A CN03138693 A CN 03138693A CN 100363971 C CN100363971 C CN 100363971C
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- latch
- data
- enable signal
- digital
- switch module
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Abstract
The present invention relates to a digital data driver, which comprises a plurality of data signal lines, a first shift buffer, a second shift buffer and a plurality of transmission control units, wherein each of the data signal lines transfers first data in a first time cycle and transfers second data in a second time cycle; the first shift buffer outputs a first enabling signal in the first time cycle, and the second shift buffer outputs a second enabling signal in the second time cycle; each of the transmission control units is respectively coupled to one corresponding data signal line, and each of the transmission control units outputs the first data and the second data to two different digital-analog converters according to the first enabling signal, the second enabling signal and two external signals. With the share of a digital latch unit and the digital-analog converters, the present invention has the advantage that the difficulty in line arrangement due to the increase of required transverse arrangement area when resolution is increased.
Description
Technical field
The present invention relates to a kind of data driver, be particularly related to a kind of digital data driver of LCD, by shared digital phase-locking storage and digital analog converter, when avoiding owing to the resolution increase, because needed landscape layout area increases, the degree of difficulty on the configuration that is caused.
Background technology
The digital data driver of tradition AMLCD, use Storage Register (digital phase-locking storage), a signal wire in the cycle as line buffer (line buffer) in order to the store digital signal of video signal, and under the pattern of one time one signal line, drive digital analog converter (DAC).Figure 1A and Figure 1B show the one 6 figure place font data driven architectures 10 that operate in traditionally under the one time one signal line pattern.Under this framework, retouch in the cycle of sweeping bit shift register SR in each level
nOutput can cause at enable signal and appear at the online digital image signal R[5 of signal]～B[0], be loaded in order among the corresponding first order latch Latch11.Afterwards, by " LB " control of signal, all are stored in the digital image signal R[5 among the first order latch Latch11]～B[0] can write among the latch Latch12 of the second level, be put into digital analog converter DAC-R simultaneously
n, DAC-G
n, DAC-B
nIn.And at next bit shift register SR
N+1Can cause during the enable signal of output and appear at the online digital image signal R[5 of signal]～B[0], be loaded in order among the corresponding first order latch Latch21.Afterwards, by " LB " control of signal, all are stored in the digital image signal R[5 among the first order latch Latch21]～B[0] can write among the latch Latch22 of the second level, be put into digital analog converter DAC-R simultaneously
N+1, DAC-G
N+1, DAC-B
N+1In.
Because resolution increases, data bits can and then increase, thus account for very much the Storage Register of layout area, and the number of digital analog converter also can be along with increase.Yet under the conventional arrangement mode, numeric type driver layout in the horizontal is more limited.Therefore, when the resolution increase causes the number of Storage Register and digital analog converter to increase, will increase the degree of difficulty on the configuration.
Summary of the invention
In view of this, primary and foremost purpose of the present invention is to be to provide a kind of digital data driver, by shared digital phase-locking storage and digital analog converter, when avoiding, because needed landscape layout area increases the degree of difficulty on the configuration that is caused owing to the resolution increase.
For achieving the above object, the invention provides a kind of digital data driver, comprise a plurality of data signal lines, each data signal line transmits one first data when the cycle very first time, and transmits one second data when one second time cycle; One first offset buffer in order to when the cycle very first time, is exported one first enable signal; One second offset buffer in order to when second time cycle, is exported one second enable signal; A plurality of transmission control units are coupled to the data signal line of a correspondence respectively.
Wherein each transmission control unit comprises first, second switch module, connects in parallel, and respectively has one first end and couple of a plurality of data signal lines; One first latch has one second end that an input end couples first, second switch module; The one the 3rd, the 4th switch module connects in parallel, and respectively has the output terminal that one first end couples first latch; One second latch has one second end that an input end couples the 3rd, the 4th switch module; The one the 5th, the 6th switch module connects in parallel, and respectively has the output terminal that one first end couples second latch; One the 3rd latch has one second end that an input end couples the 5th, the 6th switch module; One minion is closed assembly, has the output terminal that one first end couples the 3rd latch; One quad latch has an input end and couples one second end that minion is closed assembly; And one first phase inverter, have the output terminal that an input end couples the 3rd latch.
Wherein the first, the 3rd switch module is according to the first enable signal conducting, and in second latch, and the second switch assembly is according to the second enable signal conducting with first data storing, with second data storing in first latch.Five, minion pass assembly is according to one the 3rd enable signal conducting, and first data with being stored in second latch are stored in the quad latch, and export one first digital analog converter to.Four, the 6th switch module is will be stored in second data in first latch according to one the 4th enable signal, exports one second digital analog converter to via first phase inverter.
Description of drawings
Figure 1A～1B represents the framework of known number font data driver.
Fig. 2 is the synoptic diagram of LCD of the present invention.
Fig. 3 is the synoptic diagram of digital data driver of the present invention.
Fig. 4 A～4D is the operation chart of a transmission control unit (TCU) in the digital data driver of the present invention
Fig. 5 is the oscillogram of the enable signal of transmission control unit among the present invention.
Fig. 6 is the framework of digital data driver of the present invention.
The drawing reference numeral explanation
SR
n, SR
N+1, SR
1, SR
2: bit shift register;
Latch11, Latch22, L1～L4: latch;
TG1, TG2: transmission lock;
200: LCD; 201: the active-matrix zone;
202: scanner driver; 203: the digital data driver;
T
1～T
7: switch module; INV1: phase inverter;
DAC
1～DAC
m、DAC-R
n、DAC-G
n、DAC-B
n、DAC-R
n+1、DAC-G
n+1、
DAC-B
N+1: digital analog converter;
DL
1～DL
n: data signal line;
E
N1, E
N2, E
N3, E
N4: enable signal.
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and be described with reference to the accompanying drawings as follows.
As shown in Figure 2, for being suitable for a LCD 200 of digital data driver of the present invention.As shown in Figure 2, LCD 200 has active-matrix zone 201, one scan driver 202 and a digital data driver 203 of being lined up by a plurality of pixel at least.Scanner driver 202 is in order to open the row pixel in the active-matrix zone 201 in order.Digital data driver 203, in order to outputting data signals to respective pixel.
As shown in Figure 3, digital data driver 203 comprises a plurality of data signal line DL
1～DL
n, a plurality of offset buffer (SR
1, SR
2) and a plurality of transmission control unit TTC1～TTCn.
A plurality of offset buffers are exported activation letter in order.In this example, one first offset buffer SR
1,, export one first enable signal E in order to when the cycle very first time
N1And one second offset buffer SR
2,, export one second enable signal E in order to when next time cycle (second time cycle)
N2, wherein the cycle very first time and second time cycle are in the same display cycle (line period).Each data signal line DL
1～DL
nWhen the cycle very first time, transmit one first data, and when one second time cycle, transmit one second data.A plurality of transmission control unit TCC1～TCCn are coupled to the data signal line of a correspondence respectively.
(TTC1～TTCn) respectively comprises first, second switch module T to transmission control unit
1, T
2, connect in parallel, and respectively have one first end and couple a plurality of data signal line DL
1～DL
nOne; One first latch L1 has an input end and couples first, second switch module T
1, T
2One second end; The one the 3rd, the 4th switch module T
3, T
4, connect in parallel, and respectively have the output terminal that one first end couples the first latch L1; One second latch L2 has an input end and couples the 3rd, the 4th switch module T
3, T
4One second end; The one the 5th, the 6th switch module T
5, T
6, connect in parallel, and respectively have the output terminal that one first end couples the second latch L2; One the 3rd latch L3 has an input end and couples the 5th, the 6th switch module T
5, T
6One second end; One minion is closed assembly T
7, have the output terminal that one first end couples the 3rd latch L3; One quad latch L4 has an input end and couples minion pass assembly T
7One second end; And one first phase inverter INV1, have the output terminal that an input end couples the 3rd latch L3.In addition, quad latch is coupled to different digital analog converters with the output terminal of first phase inverter.In this example, the output terminal of quad latch is coupled to one first digital analog converter DAC
1, and the output terminal of the first phase inverter INV1 is coupled to one second digital analog converter DAC
2
Fig. 4 A～4D is the operation chart of the first transmission control unit TCC1 among the present invention, and the 5th figure is the oscillogram of the enable signal of transmission control unit TCC1.Below with reference to Fig. 4 A～4D and Fig. 5, the operation of transmission control unit of the present invention is described.
At first, in the cycle very first time of N display cycle, the first bit shift register SR
1Export the first enable signal E
N1, the first, the 3rd switch module T
1, T
3Be switched on, so the first data D0[0 on the data signal line DL0] be stored among first, second latch L1, the L2.
Follow in the next time cycle (second time cycle) of N display cycle the second bit shift register SR
2Export the second enable signal En
2, second switch assembly T
2Be switched on, so the second data D0[1 on the data signal line DL0] be stored among the first latch L1.
In N display cycle and N+1 a blanking cycle (blanking period) was arranged between the display cycle.
In one the 3rd time cycle in blanking cycle, the 5th, minion closes assembly T
5, T
7, according to one the 3rd enable signal E from external control circuit
N3, will be in first data among the second latch L2, be stored into the 3rd, among the quad latch L4, and export one first digital analog converter DAC to
1
In one the 4th time cycle in blanking cycle, the 4th, the 6th switch module T
4, T
6, according to one the 4th enable signal E from external control circuit
N4, second data with existing among the first latch L1 are stored among second, third latch L2, the L3, and export one second digital analog converter DAC to via the first phase inverter INV1
2
The operation of other transmission control unit TCC2～TCCn in the data driver of the present invention, identical with the first transmission control unit TCC1, be not repeated at this.So data driver of the present invention can be according to a plurality of offset buffer SR
1～SR
n, and output digital data is to corresponding digital analog converter DAC-R
1～DAC-R
N+1, DAC-G
1～DAC-G
N+1, DAC-B
1～DAC-B
N+1In.
Therefore, according to circuit framework of the present invention, the digital data driver among the 6th figure can be in order to replace the known number font data drive circuit among Figure 1A and Figure 1B, and wherein the circuit of the TCC1～TCCn among Fig. 6 is identical with circuit among Fig. 3.On this structure, retouch in the cycle very first time in the cycle of sweeping bit shift register SR in each level
nCause and appear at the online digital image signal R[5 of signal]～B[0] (first data), be loaded in order in the second corresponding latch.And retouch in one second time cycle in the cycle of sweeping bit shift register SR in each level
N+1Cause and appear at the online digital image signal R1[5 of signal]～B1[0] (second data), be loaded in order in the first corresponding latch.Afterwards, by the control from one the 3rd enable signal of external circuit, all are stored in the digital image signal R[5 in second latch]～B[0] be written in the quad latch, be put into digital analog converter DAC-R simultaneously
n, DAC-G
n, DAC-B
nIn.And by the control from one the 4th enable signal of external circuit, all are stored in the digital image signal R[5 in first latch]～B[0] be written in the 3rd latch, and export digital analog converter DAC-R to by phase inverter
N+1, DAC-G
N+1, DAC-B
N+1
Therefore, digital data driver of the present invention can reduce required landscape layout area, so avoided because resolution when increasing, because needed landscape layout area increases the degree of difficulty on the configuration that is caused.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, those skilled in the art, without departing from the spirit and scope of the present invention; can do some changes and retouching, so protection scope of the present invention is looked the appended claim scope and is as the criterion.
Claims (11)
1. digital data driver comprises:
A plurality of data signal lines, each data signal line transmit one first data when the cycle very first time, and transmit one second data when one second time cycle;
One first offset buffer in order to when this cycle very first time, is exported one first enable signal;
One second offset buffer in order to when this second time cycle, is exported one second enable signal; And
A plurality of transmission control units are coupled to the data signal line of a correspondence respectively, and each transmission control unit comprises one first to fourth latch and one first phase inverter at least;
Wherein each this transmission control unit according to this first enable signal and this second enable signal, deposits these second data and this first data at this first latch and this second latch respectively; And according to one the 3rd enable signal, with this first data storing of being deposited to this quad latch and export one first digital analog converter to; And export this second data storing of being deposited to one second digital analog converter to the 3rd latch and via this first phase inverter according to one the 4th enable signal,
Wherein this transmission control unit also comprises:
One first, second switch module connects in parallel, and respectively has one first end and couple of this a plurality of data signal lines, and one second end couples an input end of this first latch;
The one the 3rd, the 4th switch module connects in parallel, and respectively have the output terminal that one first end couples this first latch, and one second end couples an input end of this second latch;
The one the 5th, the 6th switch module connects in parallel, and respectively have the output terminal that one first end couples this second latch, and one second end couples an input end of the 3rd latch; And
One minion is closed assembly, have the output terminal that one first end couples the 3rd latch, and one second end couples an input end of this quad latch; Wherein this first phase inverter has the output terminal that an input end couples the 3rd latch.
2. digital data driver as claimed in claim 1, wherein this first, the 3rd switch module is according to this first enable signal conducting, with this first data storing in this second latch, and this second switch assembly is according to this second enable signal conducting, with this second data storing in this first latch; Five, minion is closed assembly according to the 3rd enable signal conducting, and these first data with being stored in this second latch are stored in this quad latch, and export this first digital analog converter to; Four, the 6th switch module will be stored in these second data in this first latch according to the 4th enable signal, export this second digital analog converter to via this first phase inverter.
3. digital data driver as claimed in claim 1, wherein this first to close assembly to minion be transmission gate.
4. digital data driver as claimed in claim 1, wherein this first to close assembly to minion be switching transistor.
5. digital data driver as claimed in claim 1, wherein the 3rd and the 4th enable signal in a blanking cycle one the 3rd time cycle and one the 4th time cycle in produce, the 3rd enable signal control the 5th and minion close assembly, the 4th enable signal is controlled the 4th and the 6th switch module.
6. LCD comprises:
A plurality of pixels are arranged in a matrix form;
The one scan driver is in order to open the row pixel in this matrix form in order; And
One digital data driver is in order to the pixel of outputting data signals to correspondence; Wherein this digital data driver comprises:
A plurality of data signal lines, each data signal line transmit one first data when the cycle very first time, and transmit one second data when one second time cycle;
One first offset buffer in order to when this cycle very first time, is exported one first enable signal;
One second offset buffer in order to when this second time cycle, is exported one second enable signal; And
A plurality of transmission control units are coupled to the data signal line of a correspondence respectively; And
A plurality of digital analog converters, in order to data-signal that will this a plurality of transmission control units output, convert simulating signal to after, output to this pixel; Each transmission control unit comprises one first to fourth latch and one first phase inverter at least;
Wherein each this transmission control unit according to this first enable signal and this second enable signal, deposits these second data and this first data at this first latch and this second latch respectively; And according to one the 3rd enable signal, with this first data storing of being deposited to this quad latch and export one first digital analog converter to; And export this second data storing of being deposited to one second digital analog converter to the 3rd latch and via this first phase inverter according to one the 4th enable signal,
Wherein this transmission control unit also comprises:
One first, second switch module connects in parallel, and respectively has one first end and couple of this a plurality of data signal lines, and one second end couples an input end of this first latch;
The one the 3rd, the 4th switch module connects in parallel, and respectively have the output terminal that one first end couples this first latch, and one second end couples an input end of this second latch;
The one the 5th, the 6th switch module connects in parallel, and respectively have the output terminal that one first end couples this second latch, and one second end couples an input end of the 3rd latch; And
One minion is closed assembly, have the output terminal that one first end couples the 3rd latch, and one second end couples an input end of this quad latch; Wherein this first phase inverter has the output terminal that an input end couples the 3rd latch.
7. LCD as claimed in claim 6, wherein this first, the 3rd switch module is according to this first enable signal conducting, with this first data storing in this second latch, and this second switch assembly is according to this second enable signal conducting, with this second data storing in this first latch; Five, minion is closed assembly according to the 3rd enable signal conducting, and these first data with existing in this second latch are stored in this quad latch, and export this first digital analog converter to; Four, will there be these second data in this first latch in the 6th switch module according to the 4th enable signal, export this second digital analog converter to via this first phase inverter.
8. LCD as claimed in claim 6, wherein this first to close assembly to minion be transmission gate.
9. LCD as claimed in claim 6, wherein this first to close assembly to minion be switching transistor.
10. LCD as claimed in claim 6, wherein the 3rd and the 4th enable signal in a blanking cycle one the 3rd time cycle and one the 4th time cycle in produce, the 3rd enable signal control the 5th and minion close assembly, the 4th enable signal is controlled the 4th and the 6th switch module.
11. LCD as claimed in claim 7, wherein this first digital analog converter and second digital analog converter, be these first data, second data that will receive, convert one first simulated data and one second simulated data to after, export the pixel of a correspondence respectively to.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031386938A CN100363971C (en) | 2003-06-03 | 2003-06-03 | Digital data driver and liquid-crystal displaying device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031386938A CN100363971C (en) | 2003-06-03 | 2003-06-03 | Digital data driver and liquid-crystal displaying device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1553427A CN1553427A (en) | 2004-12-08 |
| CN100363971C true CN100363971C (en) | 2008-01-23 |
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ID=34323785
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031386938A Expired - Lifetime CN100363971C (en) | 2003-06-03 | 2003-06-03 | Digital data driver and liquid-crystal displaying device |
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| Country | Link |
|---|---|
| CN (1) | CN100363971C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007183373A (en) * | 2006-01-05 | 2007-07-19 | Nec Electronics Corp | Display controller |
| CN100426372C (en) * | 2006-06-14 | 2008-10-15 | 友达光电股份有限公司 | Data drive circuit, liquid crystal display panel, liquid crystal display module and display |
| CN101419345B (en) * | 2007-10-22 | 2010-09-29 | 奇景光电股份有限公司 | Display driver and built-in test circuit thereof |
| CN101771402B (en) * | 2008-12-26 | 2012-07-18 | 北京京东方光电科技有限公司 | Flip latch and liquid crystal display source drive device |
Citations (5)
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|---|---|---|---|---|
| US6008801A (en) * | 1997-02-28 | 1999-12-28 | Lg Semicon Co., Ltd. | TFT LCD source driver |
| CN1281155A (en) * | 1999-06-04 | 2001-01-24 | 权五敬 | Actuator of liquid crystal display device |
| US6256024B1 (en) * | 1997-09-10 | 2001-07-03 | Sony Corporation | Liquid crystal display device |
| US20020145602A1 (en) * | 1995-02-17 | 2002-10-10 | Yojiro Matsueda | Liquid crystal display apparatus, driving method therefor, and display system |
| CN1391203A (en) * | 2001-06-07 | 2003-01-15 | Lg.菲利浦Lcd株式会社 | Liquid crystal display with two terminal data polarity reverser and drive thereof |
-
2003
- 2003-06-03 CN CNB031386938A patent/CN100363971C/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020145602A1 (en) * | 1995-02-17 | 2002-10-10 | Yojiro Matsueda | Liquid crystal display apparatus, driving method therefor, and display system |
| US6008801A (en) * | 1997-02-28 | 1999-12-28 | Lg Semicon Co., Ltd. | TFT LCD source driver |
| US6256024B1 (en) * | 1997-09-10 | 2001-07-03 | Sony Corporation | Liquid crystal display device |
| CN1281155A (en) * | 1999-06-04 | 2001-01-24 | 权五敬 | Actuator of liquid crystal display device |
| CN1391203A (en) * | 2001-06-07 | 2003-01-15 | Lg.菲利浦Lcd株式会社 | Liquid crystal display with two terminal data polarity reverser and drive thereof |
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| Publication number | Publication date |
|---|---|
| CN1553427A (en) | 2004-12-08 |
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