JP3133620B2 - Semiconductor memory and display device driving circuit using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory for temporarily storing data representing video information and a driving circuit of a display device using the semiconductor memory.

[0002]

2. Description of the Related Art Conventionally, as a display means for displaying an image taken by a television camera, various characters, and the like, an LED display panel in which a plurality of light emitting diodes (LEDs) are arranged in a matrix has been used. Since the LED display panel has a simple structure and is easily connected to a drive circuit, it is suitable for an increase in size, and is widely used for various electric display panels and the like. Further, in recent years, it has been considered that a color image comparable to that of a normal cathode ray tube is displayed by using LEDs corresponding to each color component of red, green and blue.

FIG. 3 is a circuit diagram showing the structure of a basic single-color LED display panel. A plurality of LEDs 1 are arranged in n rows and m columns in the row direction and the column direction, respectively. A signal line 2 is associated with each column of these LEDs 1 and is connected to the cathode of each LED 1. In addition, LED
The scanning line 3 is associated with each of the rows 1 and is connected to the anode of each LED 1. The m signal lines 2 have 1
Column drive signals XD1 to XDm including the video information for the rows are applied, and row drive signals YD1 to YDm for activating the LEDs 1 on a row-by-row basis at a fixed cycle are applied to the n scanning lines 3. Thereby, the column drive signal XD applied to the signal line 2
1 to XDm are supplied to the LED 1 of the row activated in response to the row drive signals YD1 to YDm, and the column drive signals XD1 to XDm
Is displayed by the light emission of each LED 1.

FIG. 4 is a block diagram showing a configuration of a driving circuit for supplying a driving signal to the LED display panel. The shift register 11 serially takes in video data DY1 of an appropriate number of bits supplied from a personal computer or the like, and outputs the data to the input data bus 12 for each data. Input data bus 12
Are alternately fetched video image data DY1 output from the shift register 11 to the input data bus 12 in units of one screen and supplied to the memory cell arrays 14a and 14b. The memory cell arrays 14a and 14b each have a capacity capable of storing video data DY1 for one screen, and the video data DY supplied from the input buffers 13a and 13b.
1 is temporarily stored in units of one screen. Two output buffers 15 connected to each memory cell array 14a, 14b
a, 15b are the respective memory cell arrays 14a, 1
The video data DY1 read from the memory 4b is taken in and output to the output data bus 16.

Two address designating circuits 17a and 17b corresponding to the memory cell arrays 14a and 14b respectively take in address data ADR from an address bus 18, and one designates one write address of the memory cell arrays 14a and 14b. The other designates the other read address of the memory cell arrays 14a, 14b. That is, two memory cell arrays 1 provided in parallel
4a and 14b are in a read state when one is in a write state in accordance with an instruction from a timing control circuit 20, which will be described later. Therefore, the addresses specified by the address specifying circuits 17a and 17b are the memory cell arrays 14a and 1b.
4b is a write address on the one hand and a read address on the other hand. The address data buffer 19 holds the address data ADR supplied from outside together with the video data DY1, and outputs the address data ADR to the address bus 18 in accordance with the operation of the memory cell arrays 14a and 14b. As a result, the video data DY1 input from the shift register 11 is stored in the memory cell array 14
The video data DY1 stored earlier is read from the other of the memory cell arrays 14a and 14b at the same time as the data is written to one of the memory cell arrays 14a and 14b.

[0006] The timing control circuit 20 generates a timing pulse for determining the operation timing of each unit based on the reference clock CLK. The X driver 21 responds to the timing pulse from the timing control circuit 20, receives the video data DY1 output from the output buffers 15a and 15b to the output data bus 16 for each row, and simultaneously drives the signal lines of the LED display panel. Column drive signal to be generated. The Y driver 22 responds to a timing pulse from the timing control circuit 20 to generate a row drive signal for periodically activating the scanning lines of the LED display panel in a predetermined order. Thus, the video data DY1 stored in the memory cell arrays 14a and 14b from the shift register 11 is
It is displayed on a predetermined line of the LED display panel in units of one line.

[0007]

The memory cell arrays 14a and 14b storing the video data DY1 for one screen are:
This is the simplest case in which the LEDs constituting the LED display panel are displayed only by blinking, and requires the same number of memory cells as the number of display pixels of the LED panel. For example, if one LED display panel is composed of 24 rows × 24 columns, at least 576 memory cells are required so that data of 576 pixels can be stored. When each LED of the LED display panel performs multi-gradation display, a plurality of bits of video data are required for one display pixel, and several times as many memory cells are required. For example, in order to display an LED with 16 gradations, the video data for one pixel is 4 bits, so the number of required memory cells is quadrupled.

The memory cell arrays 14a, 1
The configuration of 4b is set according to the number of bits of display data normally handled and the display capability of the connected LED panel. However, the memory cell arrays 14a, 14b correspond to specific display data and LED display panels.
In the case of the drive circuit in which the configuration is set, if the input display data or the condition of the connected LED display panel is changed, it cannot be handled. Therefore, there is no versatility, and the range of use is limited.

If the number of bits of the input video data DY1 is greater than the display capability of the connected LED display panel, the capacity of each of the memory cell arrays 14a and 14b must be increased more than necessary. . Such an increase in the capacity of the memory cell arrays 14a and 14b
In addition to the increase in the circuit scale of the memory cell arrays 14a and 14b themselves, the number of bits of the input buffers 13a and 13b and the output buffers 15a and 15b must be increased, thereby greatly increasing the circuit scale.

An object of the present invention is to provide a highly versatile semiconductor memory and a drive circuit for a display device using the same, while suppressing an increase in circuit scale.

[0011]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a first feature is that input means for sequentially taking in first data representing video information is provided. Data conversion means for performing an arithmetic processing based on an operation coefficient which can be arbitrarily set on the first data taken in by the input means to generate second data changed to a desired number of bits; A memory cell array that continuously stores the second data every predetermined number of data; and an output unit that reads out and outputs the second data stored in the memory cell array in a predetermined order. It is in.

A second feature is that input means for sequentially taking in first data representing video information, and an operation which can be arbitrarily set for the first data taken in by the input means. A data conversion means for performing an arithmetic process based on a coefficient to generate second data changed to a desired number of bits; a memory cell array for continuously storing the second data for each predetermined number of data; Output means for reading and outputting the second data stored in the memory cell array in a predetermined order, and a display in which a plurality of display pixels are arranged in a matrix based on the second data output from the output means Drive means for generating a drive signal corresponding to the device.

[0013]

According to the first feature of the present invention, by providing data conversion means for changing the number of bits of input data on the input side of the memory cell array, even if the number of bits of input data changes, the memory cell array can be used. Is always stored with a fixed number of bits. For this reason, the limit on the number of bits of input data is relaxed.

According to a second feature of the present invention, the drive signal of the display device is generated by reading the input data which is always converted into a fixed number of bits by the data conversion means and stored in the memory cell array. Thus, even when the information required by the display device does not match the input data, the input data can be converted into the information required by the display device by the data conversion means. Therefore, the restriction on the input data is relaxed, and the interface on the input side is expanded.

[0015]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory according to the present invention. The input control unit 31 sequentially captures and holds the video data DY1 that is continuously input, and supplies the video data DY1 to the storage data conversion unit 32 every predetermined number of data. In the input control unit 31, the video data D input serially
Y1 is converted to parallel. Storage data converter 32
Converts the coefficient data EF1 that can be set arbitrarily into the video data D
By multiplying Y1, the thinning process is performed on the video data DY1 to generate video data DY2 in which the number of bits is compressed to a desired number of bits. The coefficient data EF1 supplied to the storage data conversion unit 32 is supplied from the outside and held in the coefficient data generation unit 33, and the coefficient data EF1 is supplied from the coefficient data generation unit 33 to the data conversion processing in the storage data conversion unit 32. The data is supplied to the storage data converter 32.

The input buffer 34 is a storage data converter 3
2 is supplied to the memory cell array 35. The memory cell array 35
It has a predetermined storage capacity, and temporarily stores video data DY2 supplied from the input buffer 34 in units of a predetermined number according to the address designation from the address designation circuit 36. For example, when the video data DY1 is continuous in units of one screen, data for one screen is stored simultaneously. The output buffer 37 captures the video data DY2 read from the memory 35 and supplies the video data DY2 to the reproduction data conversion unit 38. The reproduction data converter 38 converts the video data DY2 so as to conform to a format required on the output side, and generates a drive signal DRV. The reproduced data converter 38 is, for example, a digital / digital
A drive signal DRV that is configured by an analog conversion circuit and changes the sum of pulse widths within a certain period according to the content of the video data DY2 is output. Then, the output control unit 39
In response to an output instruction from the output side, the reproduction data conversion unit 38
And outputs the drive signal DRV output from.

According to such a semiconductor memory, no matter how many bits the input display data DY1 has, a predetermined conversion process is performed in the storage data conversion unit 32. The video data DY2 is stored in the memory cell array 35. Therefore, the restriction on the number of bits of the video data DY1 given from the input side is relaxed, the input interface is expanded, the memory cell array 35 can be used efficiently, and the capacity of the memory cell array 35 increases, that is, the circuit The increase in scale can be suppressed.

FIG. 2 is a circuit diagram of an L-type memory using the semiconductor memory of the present invention.
FIG. 3 is a block diagram illustrating a configuration of a drive circuit of the ED panel.
The shift register 41 captures video data DY1 supplied from a data source represented by a personal computer or the like, and supplies the captured video data DY1 to the storage data conversion circuit 42 for each predetermined number of data. Storage data conversion circuit 42
Multiplies input data by arbitrarily set coefficient data EF1 to obtain video data D having a desired number of bits.
Y2 is generated and output to the input data bus 44. When the number of bits of the video data DY1 is larger than the target number of bits, the video data DY1 is subjected to a thinning process to compress the number of bits, and conversely,
When the number is small, the video data DY1 is generated by performing an interpolation process to expand the number of bits. The coefficient data EF1 supplied to the storage data conversion unit 42
Is supplied from the outside, is taken into a coefficient data generation circuit 43 having a register configuration, and is supplied to the storage data conversion circuit 42 in accordance with the data conversion processing in the storage data conversion unit 42.

The two input buffers 45a and 45b connected to the input data bus 44 alternately take in the video data DY2 output from the storage data conversion circuit 42 to the input data bus 44 in units of one screen, and provide a memory cell array 46a , 46b. Memory cell array 46
a and 46b temporarily store the video data DY2 supplied from the input buffers 45a and 45b in units of one screen. Two output buffers 47a and 47b connected to the respective memory cell arrays 46a and 46b take in the video data DY2 read from the respective memory cell arrays 46a and 46b and output them to the output data bus 48. Address designating circuits 49a and 49b corresponding to the memory cell arrays 46a and 46b respectively take in address data ADR from the address bus 50, and one designates one write address of the memory cell arrays 46a and 46b, and the other designates the memory cell array 46a. , 4
6b is designated. These input buffers 45a, 45b, memory cell array 46a,
46b, output buffers 47a and 47b, and addressing circuits 49a and 49b are the same as those in FIG. That is, the video data DY2 output from the storage data conversion circuit 42 to the input data bus 44 is stored in the memory cell arrays 46a and 46b.
Of the memory cell array 46
a, video data DY2 stored first from the other of 46b
Is read and output to the output data bus 48.

The pulse width modulation circuit 52 connected to the output data bus 28 takes in the video data DY2 output from the output buffers 47a and 47b for each data, and according to the content of each data, the pulse width within a certain period. Is generated variably set. The timing control circuit 53 generates a timing pulse for determining the operation timing of each unit based on the reference clock CLK. The X driver 54 responds to the timing pulse from the timing control circuit 53, receives the pulse width modulation signal PWM supplied from the pulse width modulation circuit 53 for each row, and simultaneously drives the signal lines of the LED display panel. Generate a signal. The Y driver 55 responds to a timing pulse from the timing control circuit 53 to generate a row drive signal for periodically activating the scanning lines of the LED display panel in a predetermined order. As a result, the display data DY2 stored in the memory cell arrays 46a and 46b from the storage data conversion circuit 42 is displayed on a predetermined row of the LED display panel in units of one row.

According to such an LED display panel driving circuit, the video data D input to the shift register 41
No matter how many bits Y1 has, the memory cell array 46
At the stage where the data is stored in a and 46b, the video data DY2 having a predetermined number of bits has been converted. Therefore, the restriction on the video data DY1 input to the shift register 41 is relaxed, and the interface with the data source is expanded. Further, since the number of bits of the video data DY2 to be stored can be made constant, the memory cell array 46a,
The configuration of 46b can be determined in advance, and the utilization efficiency of the memory cell arrays 46a and 46b can be improved.

In the above embodiment, the case where the driving circuit of the LED display panel is formed is exemplified. However, the present invention can be applied to a driving circuit corresponding to another display device, for example, a liquid crystal display panel or a plasma display. . If the video data DY1 is composed of a plurality of color components, a driving circuit of a display device capable of performing color display can be realized.

[0023]

According to the present invention, since the data conversion means is provided at the input stage of the video data, it is possible to cope with various video data by changing the coefficient data for the conversion process. For this reason, the interface on the input side is expanded, and the versatility can be improved. Further, since the number of bits of the video data stored in the memory cell array is determined in advance, the efficiency of use of the memory cells can be improved, and as a result, the increase in the capacity of the memory cells can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration of a drive circuit of a display device of the present invention.

FIG. 3 is a circuit diagram schematically showing an LED display panel.

FIG. 4 is a circuit diagram showing a configuration of a driving circuit of a conventional display device.

[Explanation of symbols]

 1 LED 2 signal line 3 scanning line 11, 41 shift register 12, 44 input data bus 13a, 13b, 45a, 45b input buffer 14a, 14b, 46a, 46b memory 15a, 15b, 47a, 47b output buffer 16, 48 output data Buses 17a, 17b, 49a, 49b Addressing circuit 18, 50 Address bus 19, 51 Address data register 20, 53 Timing control circuit 21, 54 X driver 22, 55 Y driver 31 Input control unit 32 Storage data conversion unit 33 Coefficient data Generation unit 34 Input buffer 35 Memory 36 Address designation unit 37 Output buffer 38 Reproduction data conversion unit 39 Output control unit 42 Storage data conversion circuit 43 Coefficient data generation circuit 52 Pulse width modulation circuit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G09G 3/20 G09G 3/36 G11C 7/00

Claims (2)

(57) [Claims] 1. A method for sequentially acquiring first data representing video information.
Input means, and the first
Based on operation coefficients that can be set arbitrarily for
Arithmetic processing, and the second data changed to the desired number of bits.
Data conversion means for generating data, and the second data
A pair of memory cells that store data alternately in fixed data units.
Rays and stored in these pairs of memory cell arrays
The second data is alternately read out in a predetermined order and output.
Output means, and the second output from the output means.
Based on the data, multiple display pixels are arranged in a matrix
Driving means for generating a driving signal corresponding to the display device;
A driving circuit for a display device, comprising: 2. The method according to claim 1, wherein the first data representing the video information is sequentially taken.
Input means, and the first
Based on operation coefficients that can be set arbitrarily for
Arithmetic processing, and the second data changed to the desired number of bits.
Data conversion means for generating data, and the second data
A pair of memory cells that store data alternately in fixed data units.
Rays and stored in these pairs of memory cell arrays
The second data is alternately read out in a predetermined order and output.
Output means, and the second output from the output means.
Based on the data, multiple display pixels are arranged in a matrix
Generate column drive signals to drive each column of the display device
In addition, a driving system that sequentially activates each line of the display device at a constant cycle.
Driving means for generating a motion signal.
Drive circuit of an information display device.