JPH07176847A - Circuit board and its manufacture - Google Patents

Circuit board and its manufacture

Info

Publication number
JPH07176847A
JPH07176847A JP31996393A JP31996393A JPH07176847A JP H07176847 A JPH07176847 A JP H07176847A JP 31996393 A JP31996393 A JP 31996393A JP 31996393 A JP31996393 A JP 31996393A JP H07176847 A JPH07176847 A JP H07176847A
Authority
JP
Japan
Prior art keywords
land portion
hole
holes
substrate
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31996393A
Other languages
Japanese (ja)
Inventor
Toshihiro Katayama
俊宏 片山
Toshiji Shimamoto
敏次 島本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokuyama Corp
Original Assignee
Tokuyama Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokuyama Corp filed Critical Tokuyama Corp
Priority to JP31996393A priority Critical patent/JPH07176847A/en
Publication of JPH07176847A publication Critical patent/JPH07176847A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates

Abstract

PURPOSE:To improve the electrical connectability between a hardened conductive body and wiring pattern by grinding the end face of the hardened conductive body formed to cover at least part of a land section to a flat face. CONSTITUTION:A wiring pattern 2 is formed on at least one surface of an insulating substrate and has a land section 5. In order to increase the contacting area of the land section 5 with a hardened conductive body 4, the width W of the section 5 is made wider under the restriction of other wiring patterns. A pierced hole 3 for through hole 3 is filled with the body 4, with the end of the body 4 being protruded from the section 5 so that the body 4 can cover at least part of the section 5, and the end face A of the body 4 is flattened. When such a constitution is used, the land section 5 can be widely covered with the body 4 without increasing the height of the body 4. Therefore, the reliability of the electrical connection between the body 4 and pattern 2 can be remarkably improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、新規な構造の回路基板
及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board having a novel structure and a method for manufacturing the same.

【0002】[0002]

【従来の技術】絶縁基板の両面に配線パターンを形成し
た回路基板の両面に存在する回路パターン間の電気的接
続は、絶縁基板にスルーホール用貫通孔を設け、該スル
ーホール用貫通孔に導電性物質を存在させることによっ
て行われている。
2. Description of the Related Art Electrical connection between circuit patterns existing on both sides of a circuit board having wiring patterns formed on both sides of an insulating substrate is performed by forming through holes for through holes in the insulating substrate and conducting through the through holes for through holes. It is done by the presence of sexual substances.

【0003】従来、上記回路基板の配線パターン間の接
続を、スルーホール用貫通孔に硬化性導電物質を充填、
硬化して行う方法が知られている。
Conventionally, the connection between the wiring patterns of the circuit board is performed by filling the through holes for through holes with a curable conductive material.
A method of performing curing is known.

【0004】かかる方法において、スルーホール用貫通
孔に充填して形成された硬化性導電物質の硬化体(以
下、単に導電性硬化体ともいう)と配線パターンとの電
気的接続の信頼性を向上させることを目的とし、配線パ
ターンとしてスルーホール用貫通孔の周囲にランド部を
形成せしめ、該ランド部に上記硬化性導電物質の硬化体
が一部を覆うように構成した回路基板が提案されてい
る。
In such a method, the reliability of the electrical connection between the hardened body of the curable conductive material (hereinafter also simply referred to as the conductive hardened body) formed by filling the through holes for through holes and the wiring pattern is improved. A circuit board is proposed in which a land portion is formed around a through hole for a through hole as a wiring pattern, and the hardened body of the curable conductive material covers a part of the land portion. There is.

【0005】[0005]

【発明が解決しようとする課題】しかしながら上記回路
基板は、電気的接続の信頼性を高度に維持するために、
該ランド部を覆う導電性硬化体の面積を多くする必要が
あるが、これに伴って該導電性硬化体の突出高さが問題
となる。
However, in order to maintain the reliability of electrical connection at a high level, the above-mentioned circuit board has the following problems.
Although it is necessary to increase the area of the conductive cured body that covers the land portion, the protrusion height of the conductive cured body becomes a problem accordingly.

【0006】即ち、回路基板に形成された配線パターン
上には、該配線パターンを保護するため、或いは、該配
線パターン上に第2の回路パターンを形成するために、
ソルダーレジスト等の絶縁層が形成されるのが一般的で
ある。
That is, in order to protect the wiring pattern on the wiring pattern formed on the circuit board or to form a second circuit pattern on the wiring pattern,
An insulating layer such as a solder resist is generally formed.

【0007】そして、上記導電性硬化体の突出部は、か
かる絶縁層の形成において、層の不均一を生じる原因と
なり、かかる層による絶縁信頼性を低下させたり、回路
間で発生するノイズのばらつきによるノイズ対策の困難
を生じせしめるという問題を有する。
The protrusions of the conductive cured body cause non-uniformity of the layers in the formation of the insulating layer, which lowers the insulation reliability due to the layer and causes variations in noise generated between circuits. However, there is a problem in that it is difficult to take measures against noise.

【0008】また、絶縁層を形成しない場合において
も、部品実装用の半田クリーム印刷時においては、半田
の量のコントロールを非常に困難なものとするという問
題を生じる。
Further, even when the insulating layer is not formed, a problem arises in that it is very difficult to control the amount of solder when printing a solder cream for mounting components.

【0009】[0009]

【課題を解決するための手段】本発明者らは上記技術課
題を解決すべく鋭意研究を行た。その結果、ランド部を
少なくとも一部を覆うように形成された導電性硬化体の
端面を研削して平坦な面を形成するという簡易な手段に
より上記問題を全て解消した回路基板が得られることを
見い出し、本発明を提案するに至った。
[Means for Solving the Problems] The inventors of the present invention have made extensive studies to solve the above technical problems. As a result, it is possible to obtain a circuit board that solves all the above problems by a simple means of grinding an end surface of a conductive cured body formed so as to cover at least a part of a land portion to form a flat surface. They found out and came to propose the present invention.

【0010】図1は、本発明の回路基板の代表的な態様
を示す断面図である。
FIG. 1 is a sectional view showing a typical embodiment of the circuit board of the present invention.

【0011】即ち、本発明は、絶縁基板1の少なくとも
一方の面にランド部5を含む配線パターン2を有し、該
ランド部5に上記絶縁基板1を貫通するスルーホール用
貫通孔3が設けられて成り、該スルーホール用貫通孔3
には、硬化性導電物質の硬化体4が上記ランド部5の少
なくとも一部を覆うように、ランド部5より突出させて
充填され、且つ該硬化体4の端面Aを平坦面で構成した
ことを特徴とする回路基板である。
That is, according to the present invention, the wiring pattern 2 including the land portion 5 is provided on at least one surface of the insulating substrate 1, and the through hole through hole 3 penetrating the insulating substrate 1 is provided in the land portion 5. The through hole 3 for the through hole
In addition, the hardened body 4 of the hardenable conductive material is filled so as to project from the land portion 5 so as to cover at least a part of the land portion 5, and the end surface A of the hardened body 4 is formed as a flat surface. It is a circuit board characterized by.

【0012】本発明において、絶縁基板1は特に制限さ
れず、公知の材質、構造を有するものが使用される。代
表的なものを例示すれば、紙基材−フェノール樹脂積層
基板、紙基材−エポキシ樹脂積層基板、紙基材−ポリエ
ステル樹脂積層基板、ガラス基材−エポキシ樹脂積層基
板、紙基材−テフロン樹脂積層基板、ガラス基材−ポリ
イミド樹脂積層基板、ガラス基材−BT(ビスマレイミ
ド−トリアジン)レジン樹脂積層基板、コンポジット樹
脂基板等の合成樹脂基板や、ポリイミド樹脂、ポリエス
テル樹脂等のフレキシブル基板や、アルミニウム、鉄、
ステンレス等の金属をエポキシ樹脂等で覆って絶縁処理
した金属系絶縁基板、セラミックス基板等のが挙げられ
る。
In the present invention, the insulating substrate 1 is not particularly limited, and one having a known material and structure is used. Typical examples are paper base material-phenolic resin laminated board, paper base material-epoxy resin laminated board, paper base material-polyester resin laminated board, glass base material-epoxy resin laminated board, paper base material-Teflon. Resin laminated substrate, glass substrate-polyimide resin laminated substrate, glass substrate-BT (bismaleimide-triazine) resin resin laminated substrate, composite resin substrate or other synthetic resin substrate, polyimide resin, polyester resin or other flexible substrate, Aluminum, iron,
Examples thereof include a metal-based insulating substrate obtained by insulating a metal such as stainless steel with an epoxy resin or the like, a ceramics substrate, and the like.

【0013】本発明において、配線パターン2は、上記
絶縁基板の少なくとも一面上に形成され且つランド部5
を有する。該配線パターンは、通常、絶縁基板に張り付
けられた銅箔、アルミ箔等の導電層を公知の方法によ
り、所定のパターンとなるようにエッチングすることに
よって得ることができる。
In the present invention, the wiring pattern 2 is formed on at least one surface of the insulating substrate and the land portion 5 is formed.
Have. The wiring pattern can be usually obtained by etching a conductive layer such as a copper foil or an aluminum foil attached to an insulating substrate into a predetermined pattern by a known method.

【0014】また、上記ランド部5の幅Wは、後述する
導電性硬化体4との接触面積を大きくするため、他の配
線パターンによる制約下において可及的に大きい方が好
ましいが、一般に、100μm以上、スルーホール用貫
通孔3の直径の3倍以下の範囲で決定することが好まし
い。
Further, the width W of the land portion 5 is preferably as large as possible under the constraint of other wiring patterns in order to increase the contact area with the conductive cured body 4 described later, but in general, It is preferable to determine in the range of 100 μm or more and 3 times or less of the diameter of the through hole 3 for through hole.

【0015】本発明において、スルーホール用貫通孔3
は、上記回路基板の配線パターン2におけるランド部5
内に形成される。該スルーホール用貫通孔3は、通常の
方法、例えば、ドリリング、パンチング等で穿孔するこ
とによって設けることができる。かかるスルーホール用
貫通孔の径は特に制限されるものではない。一般には、
硬化性導電物質を充填することが可能な程度の孔径(直
径)であればよく、通常、0.2mm以上、好ましく
は、0.3〜2mmより選択することができる。また、
形状は、通常加工性の容易さから円形が好適である。
In the present invention, the through hole 3 for through hole is used.
Is a land portion 5 in the wiring pattern 2 of the circuit board.
Formed within. The through-holes 3 for through-holes can be provided by drilling by a usual method such as drilling or punching. The diameter of the through hole for through hole is not particularly limited. In general,
The hole diameter (diameter) may be such that it can be filled with the curable conductive material, and it can be selected from usually 0.2 mm or more, preferably 0.3 to 2 mm. Also,
A circular shape is preferable because it is easy to process.

【0016】本発明の最大の特徴は、上記スルーホール
用貫通孔3に、導電性硬化体4が上記ランド部5の少な
くとも一部を覆うように、ランド部5より突出させて充
填され、且つ該硬化体4の端面Aを平坦面で構成するこ
とにある。
The greatest feature of the present invention is that the through hole 3 for through hole is filled with the conductive hardened material 4 so as to project from the land portion 5 so as to cover at least a part of the land portion 5, and The end surface A of the cured body 4 is to be a flat surface.

【0017】尚、平坦面とは、基板面に対して厳密に平
行な面をいうのではなく、ある程度の傾斜、一般に30
度以下、好ましくは、10度以下の傾斜を有するもので
あってもよい。
The flat surface does not mean a surface that is strictly parallel to the substrate surface, but has a certain degree of inclination, generally 30.
It may have an inclination of not more than 10 degrees, preferably not more than 10 degrees.

【0018】かかる構成を採用することによって、導電
性硬化体の高さを増すことなく、ランド部を広く覆うこ
とが可能であり、これにより、該導電性硬化体と配線パ
ターンとの電気的接続の信頼性を著しく向上すことがで
きる。また、導電性硬化体の端面は、基板面に対して平
行の面となるように構成することにより、その上に絶縁
層を形成する場合には、該部分における絶縁層の厚みの
変化を効果的に抑えることができ、絶縁層の厚みの設計
が容易となるばかりでなく、絶縁不良の発生を著しく低
下させることができる。
By adopting such a constitution, it is possible to widely cover the land portion without increasing the height of the conductive hardened body, whereby the electrically conductive hardened body and the wiring pattern are electrically connected. The reliability of can be significantly improved. In addition, when the end surface of the conductive cured body is configured to be a surface parallel to the substrate surface, when an insulating layer is formed on the end surface, a change in the thickness of the insulating layer at that portion is effective. The thickness of the insulating layer can be easily controlled, and the occurrence of insulation failure can be significantly reduced.

【0019】上記導電性硬化体のランド部を覆う面積
は、ランド部の10%以上を覆うように設計することが
好ましい。
It is preferable that the area of the conductive cured body covering the land portion is designed to cover 10% or more of the land portion.

【0020】また、導電性硬化体の最高部からランド部
表面までの高さhは、通常10〜100μm、好ましく
は10〜50μmとなるように設計することが好まし
い。即ち、突出部の高さが100μmを超えた場合は、
例えば、ソルダーレジスト層形成時、該層の厚みの不均
一が著しく、また半田クリーム印刷時に半田の量をコン
トロールすることが困難となる。一方、突出部hの高さ
が10μm未満の場合、導電性硬化体をランド部上に均
一に存在させることが困難となり、配線パターンとの電
気的接続の信頼性が低下し、製品の歩留まりの減少を招
く場合がある。
Further, it is preferable that the height h from the highest part of the conductive cured material to the surface of the land is designed to be usually 10 to 100 μm, preferably 10 to 50 μm. That is, when the height of the protrusion exceeds 100 μm,
For example, when the solder resist layer is formed, the thickness of the layer is significantly uneven, and it becomes difficult to control the amount of solder during solder cream printing. On the other hand, when the height of the protruding portion h is less than 10 μm, it becomes difficult to make the conductive cured body uniformly exist on the land portion, the reliability of the electrical connection with the wiring pattern decreases, and the yield of the product decreases. May cause a decrease.

【0021】本発明の回路基板の製造方法は特に制限さ
れないが、代表的な製造方法を例示すれば、絶縁基板の
少なくとも一方の面にランド部を含む配線パターンを有
し、該ランド部に上記絶縁体を貫通するスルーホール用
貫通孔が設けられた基板を用意し、該基板のスルーホー
ル用貫通孔に硬化性導電物質を、上記ランド部の少なく
とも一部を覆い且つ上記ランド部より突出させて充填、
硬化した後、該ランド部より突出した硬化性導電物質の
硬化体をその一部がランド部上に残存するように基板面
と平行な平面状に研削する方法が好適である。
The method of manufacturing the circuit board of the present invention is not particularly limited, but a typical manufacturing method is exemplified. At least one surface of the insulating substrate has a wiring pattern including a land portion, and the land portion has the above-mentioned wiring pattern. A substrate provided with through holes for through holes penetrating the insulator is prepared, and a curable conductive material is provided in the through holes for through holes of the substrate so as to cover at least a part of the land portion and project from the land portion. Filling
After curing, a method of grinding the cured body of the curable conductive material protruding from the land portion into a flat surface parallel to the substrate surface so that a part thereof remains on the land portion is preferable.

【0022】図2は、上記方法を実施する場合の代表的
な態様を示す工程図である。
FIG. 2 is a process chart showing a typical mode for carrying out the above method.

【0023】図2に従って説明すると、絶縁基板の少な
くとも一方の面にランド部を含む配線パターンを有し、
該ランド部に上記絶縁基板を貫通するスルーホール用貫
通孔が設けられた状態の基板の製造方法として、下記に
示す方法が挙げられる。
Referring to FIG. 2, a wiring pattern including a land portion is provided on at least one surface of the insulating substrate,
As a method of manufacturing a substrate in which a through hole for penetrating the insulating substrate is provided in the land portion, the following method may be mentioned.

【0024】(a)両面に導電層6が形成された絶縁基
板1を用意し、 (b)該絶縁基板1にスルーホール用貫通孔3を形成す
る。
(A) An insulating substrate 1 having conductive layers 6 formed on both sides is prepared, and (b) a through hole through hole 3 is formed in the insulating substrate 1.

【0025】上記導電層6としては、銅箔、アルミニウ
ム箔等の金属箔、銅等の金属メッキ層等が挙げられる。
また、かかる導電層の厚みは、2〜200μm程度が適
当である。
Examples of the conductive layer 6 include metal foils such as copper foil and aluminum foil, and metal plating layers such as copper.
Further, the thickness of the conductive layer is appropriately about 2 to 200 μm.

【0026】(c)次いで、導電層6を公知の方法によ
りエッチングして、スルーホール用貫通孔3の周囲にラ
ンド部5を有する配線パターン2を形成する。
(C) Next, the conductive layer 6 is etched by a known method to form the wiring pattern 2 having the land portion 5 around the through hole through hole 3.

【0027】(d)上記スルーホール用貫通孔3に硬化
性導電物質をランド部を一部覆うように該ランド部より
突出させて充填、硬化する。かかる充填量は、得られる
導電性硬化体が前記した面積でランド部を覆うように調
整することが好ましい。
(D) The through hole 3 for through hole is filled with a curable conductive material so as to protrude from the land portion so as to partially cover the land portion, and then cured. The filling amount is preferably adjusted so that the obtained conductive cured body covers the land portion with the above-described area.

【0028】本発明において、導電性硬化体を構成する
硬化性導電物質は、導電性金属成分と樹脂成分との配合
物であって、充填には流動性を有し、熱或いは光によっ
て硬化し、その硬化体が導電性を示すものであれば公知
のものが特に制限なく使用される。具体的には、銀ペー
スト、銅ペーストが挙げられる。具体的な組成として
は、金、銀、銅、ニッケル、鉛、カーボン等の導電材料
とエポキシ樹脂、フェノール樹脂等の架橋性の熱硬化性
樹脂とを必要により有機溶剤と共に混合したものが使用
される。
In the present invention, the curable conductive substance constituting the conductive cured product is a mixture of a conductive metal component and a resin component, which has fluidity in filling and is cured by heat or light. Well-known materials may be used without particular limitation as long as the cured product exhibits conductivity. Specific examples thereof include silver paste and copper paste. As a specific composition, a mixture of a conductive material such as gold, silver, copper, nickel, lead or carbon and a crosslinkable thermosetting resin such as an epoxy resin or a phenol resin, if necessary, together with an organic solvent is used. It

【0029】また、硬化性導電物質の硬化前の粘度は、
一般に20〜20000ポイズが好適である。
The viscosity of the curable conductive material before curing is
Generally, 20 to 20000 poise is suitable.

【0030】尚、ランド部を覆う面積を増大させるた
め、粘度の低い硬化性導電物質を使用することも考えら
れるが、スルーホール用貫通孔に充填された硬化性導電
物質が硬化前に流出する等の問題があり、良好な導電性
を得ることが困難である。
Although it is possible to use a curable conductive substance having a low viscosity in order to increase the area covering the land portion, the curable conductive substance filled in the through holes for through holes flows out before curing. However, it is difficult to obtain good conductivity.

【0031】更に、スルーホール貫通孔への硬化性導電
物質の充填方法は、特に制限されるものではないが、一
般的に、スクリーン印刷法あるいはピン挿入法等の方法
が好適に採用される。
Further, the method of filling the through hole through hole with the curable conductive material is not particularly limited, but generally, a method such as a screen printing method or a pin insertion method is preferably adopted.

【0032】(e)導電性硬化体4の充填された基板
は、該ランド部より突出した導電性硬化体の一部がラン
ド部上に残存するように基板面と平行な平面Aを形成す
るように研削する。
(E) The substrate filled with the conductive cured body 4 forms a plane A parallel to the substrate surface so that a part of the conductive cured body protruding from the land portion remains on the land portion. So that it is ground.

【0033】上記導電性硬化体の一部を研削する方法
は、公知の方法が特に制限なく採用されるが、具体的に
は、ベルト研削、バフ研削等の手段が好適である。
As a method of grinding a part of the above-mentioned electroconductive cured body, a known method is adopted without particular limitation, and specifically, means such as belt grinding and buff grinding are suitable.

【0034】[0034]

【発明の効果】以上の説明より理解されるように、本発
明の回路基板は、スルーホール用貫通孔に導電性硬化体
を充填して電気的に結合される配線パターン間の信頼性
が極めて高く、回路基板両面の導通に対して高い歩留ま
りを有する。
As can be understood from the above description, the circuit board of the present invention has extremely high reliability between the wiring patterns electrically connected by filling the through holes for through holes with the conductive hardened material. It is high and has a high yield for the conduction on both sides of the circuit board.

【0035】また、後工程において、ソルダーレジスト
印刷、半田ペースト印刷を行う場合において、高精度な
印刷が可能であり、極めて有利に回路基板を製造するこ
とが可能となる。
Further, when solder resist printing or solder paste printing is performed in the subsequent process, highly accurate printing is possible, and a circuit board can be manufactured extremely advantageously.

【0036】[0036]

【実施例】本発明を更に具体的に説明するため、以下に
実施例をあげて説明するが、本発明はこれらの実施例に
限定されるものではない。
EXAMPLES In order to describe the present invention more specifically, examples will be given below, but the present invention is not limited to these examples.

【0037】実施例1 以下に示す工程に従って回路基板の製造を実施した。即
ち、 (a)両面に厚さ18μmの銅箔よりなる導電層6を有
する厚さ1.6mmの紙基材フェノール樹脂基材の絶縁
層1よりなる張り積層板を使用して、 (b)直径が0.8mmのスルーホール用貫通孔をドリ
リング加工により作製した。そして、導電層6およびス
ルーホール用貫通孔の表面を、バフ研磨、超音波洗浄、
高圧洗浄の順に洗浄した。
Example 1 A circuit board was manufactured according to the following steps. That is, (a) using a laminated laminate made of a paper base phenol resin base insulating layer 1 having a thickness of 1.6 mm and having a conductive layer 6 made of a copper foil having a thickness of 18 μm on both sides, (b) Through holes for through holes having a diameter of 0.8 mm were made by drilling. Then, the surfaces of the conductive layer 6 and the through holes for through holes are buffed, ultrasonically cleaned,
The washing was performed in the order of high pressure washing.

【0038】(c)次いで、銅電層表面にエッチングレ
ジストとしてドライフィルム(ハーキュレス(株)社製
「アクアマーCF」1.5mil)をラミネートし、露
光、現像してレジストパターンを形成した。その後、塩
化第2銅エッチング液でエッチングを行い、エッチング
レジストを剥離することによって、スルーホール用貫通
孔3の周囲に幅600μmでランド部5を有する配線パ
ターン2を形成した。
(C) Next, a dry film ("Aquamer CF" 1.5 mil manufactured by Hercules Co., Ltd.) was laminated as an etching resist on the surface of the copper electrode layer, and exposed and developed to form a resist pattern. Then, etching was performed with a cupric chloride etching solution, and the etching resist was peeled off to form a wiring pattern 2 having a land portion 5 with a width of 600 μm around the through hole 3 for through hole.

【0039】(d)上記スルーホール用貫通孔3に硬化
性導電物質として、粘度200ポイズの市販の熱硬化性
銀ペースト(徳力化研(株)社製PS−652)をスク
リーン印刷法により充填した。この際、上記銀ペースト
は、ランド部の50%の面積を覆い、ランド部の面より
高さ約300μmの突出する形で形成した。
(D) A commercially available thermosetting silver paste having a viscosity of 200 poise (PS-652 manufactured by Tokuri Kaken Co., Ltd.) is filled in the through hole 3 for through hole as a curable conductive material by a screen printing method. did. At this time, the silver paste was formed so as to cover 50% of the area of the land portion and project from the surface of the land portion at a height of about 300 μm.

【0040】該銀ペーストを熱風乾燥炉で80℃4時
間、150時間2時間の条件で乾燥、硬化した。
The silver paste was dried and cured in a hot air drying oven under the conditions of 80 ° C. for 4 hours and 150 hours for 2 hours.

【0041】(e)次に、600番のバフを複数回使用
して、基板表面ランド部より突出した形で形成され、硬
化した銀ペーストの硬化体をランド部面からの高さhが
40μmとなるように残するように研削して基板面に対
して平行な面Aを形成した。
(E) Next, using a buff of No. 600 a plurality of times, the cured silver paste is formed so as to project from the land portion on the substrate surface, and the height h from the land portion surface is 40 μm. The surface A parallel to the substrate surface was formed by grinding so as to leave the surface A.

【0042】上記のようにして得られた回路基板表面
に、ソルダーレジストとして、タムラ製作所製「熱硬化
型ソルダーレジストSR−31−SE」をスクリーン印
刷法により形成し、120℃で10分間硬化した。
On the surface of the circuit board obtained as described above, "thermosetting solder resist SR-31-SE" manufactured by Tamura Manufacturing Co., Ltd. was formed as a solder resist by a screen printing method, and was cured at 120 ° C. for 10 minutes. .

【0043】形成されたソルダーレジストの状態は、厚
みのばらつきが最大でも40μmと小さく、外観上良好
であった。
The formed solder resist had a small thickness variation of 40 μm at the maximum, and had a good appearance.

【0044】また、形成されたスルーホールの抵抗値
は、該スルーホールの両面で接続する配線パターン間の
抵抗を測定したものであり、64穴の測定を行い、平均
で9.7mΩ、標準偏差が2.30mΩであった。
The resistance value of the formed through hole is obtained by measuring the resistance between the wiring patterns connected on both sides of the through hole. The measurement of 64 holes is performed, and the average value is 9.7 mΩ, standard deviation. Was 2.30 mΩ.

【0045】更に、20℃15秒・260℃5秒の繰り
返し衝撃試験を100回行った後のスルーホール抵抗値
の変化率の平均値は5%であり、ほとんど変化がなかっ
た。
Furthermore, the average rate of change of the through-hole resistance value after performing a repeated impact test at 20 ° C. for 15 seconds and 260 ° C. for 5 seconds 100 times was 5%, and there was almost no change.

【0046】比較例1 実施例1において、(e)の研削を行うことなく、他は
全く同様にして回路基板を得た。その結果、形成された
ソルダーレジストの状態は、厚みのばらつきが大きく最
大で320μmとなり、得られた回路基板に、実施例1
と同様にしてソルダーレジスト層を形成した結果、近接
するスルーホールの付近においては、レジストが全く形
成されない部分が発見された。
Comparative Example 1 A circuit board was obtained in the same manner as in Example 1 except that (e) was not ground. As a result, the state of the formed solder resist has a large variation in thickness and the maximum is 320 μm.
As a result of forming the solder resist layer in the same manner as above, a portion where no resist was formed was found in the vicinity of adjacent through holes.

【0047】比較例2 実施例1において、(e)の研削時に、基板表面ランド
面より突出した銀ペーストの硬化体の全てを、残すこと
なく研削し、他は全く同様にして回路基板を得た。その
結果、形成されたスルーホールの抵抗値は、64穴の測
定を行い、平均で17.2mΩ、標準偏差が4.81m
Ωであった。
Comparative Example 2 A circuit board was obtained in the same manner as in Example 1, except that all of the hardened silver paste particles protruding from the land surface of the substrate were ground without leaving them during the grinding of (e). It was As a result, the resistance value of the formed through holes was measured at 64 holes and the average was 17.2 mΩ, and the standard deviation was 4.81 m.
It was Ω.

【0048】また、20℃15秒・260℃5秒の繰り
返し衝撃試験を100回行った後のスルーホール抵抗値
の変化率の平均値は80%であり、大きく変化した。
The average change rate of the through-hole resistance value after 80 times of the repeated impact test at 20 ° C. for 15 seconds and 260 ° C. for 5 seconds was 80%, which was a large change.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の回路基板の代表的態様を示す断面図で
ある。
FIG. 1 is a sectional view showing a typical embodiment of a circuit board of the present invention.

【図2】本発明の回路基板の製造方法の代表的態様を示
す工程図である。
FIG. 2 is a process drawing showing a typical aspect of the method for manufacturing a circuit board of the present invention.

【符号の説明】[Explanation of symbols]

1 絶縁基板 2 配線パターン 3 スルーホール用貫通孔 4 硬化性導電物質の硬化体 5 ランド部 6 導電層 DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Wiring pattern 3 Through hole for through hole 4 Cured body of curable conductive material 5 Land portion 6 Conductive layer

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】絶縁基板の少なくとも一方の面にランド部
を含む配線パターンを有し、該ランド部に上記絶縁基板
を貫通するスルーホール用貫通孔が設けられて成り、該
スルーホール用貫通孔には、硬化性導電物質の硬化体が
上記ランド部の少なくとも一部を覆うように、ランド部
より突出させて充填され、且つ該硬化体の端面を平坦面
で構成したことを特徴とする回路基板。
1. A through-hole through hole having a wiring pattern including a land portion on at least one surface of an insulating substrate, the through-hole penetrating the insulating substrate being provided in the land portion. In the circuit, a cured body of a curable conductive material is filled so as to project from the land portion so as to cover at least a part of the land portion, and the end surface of the cured body is formed as a flat surface. substrate.
【請求項2】絶縁基板の少なくとも一方の面にランド部
を含む配線パターンを有し、該ランド部に上記絶縁体を
貫通するスルーホール用貫通孔が設けられた基板を用意
し、該基板のスルーホール用貫通孔に硬化性導電物質
を、上記ランド部の少なくとも一部を覆い且つ上記ラン
ド部より突出させて充填、硬化した後、該ランド部より
突出した硬化性導電物質の硬化体をその一部がランド部
上に残存するように、平面状に研削することを特徴とす
る回路基板の製造方法。
2. A substrate having a wiring pattern including a land portion on at least one surface of an insulating substrate and having through holes for through holes penetrating the insulator in the land portion is prepared. After the curable conductive material is filled in the through hole for through holes so as to cover at least a part of the land portion and protrude from the land portion and cured, and then the cured body of the curable conductive material protruding from the land portion is formed. A method of manufacturing a circuit board, which comprises grinding a surface so that a part of the land remains on the land.
JP31996393A 1993-12-20 1993-12-20 Circuit board and its manufacture Pending JPH07176847A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31996393A JPH07176847A (en) 1993-12-20 1993-12-20 Circuit board and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31996393A JPH07176847A (en) 1993-12-20 1993-12-20 Circuit board and its manufacture

Publications (1)

Publication Number Publication Date
JPH07176847A true JPH07176847A (en) 1995-07-14

Family

ID=18116210

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31996393A Pending JPH07176847A (en) 1993-12-20 1993-12-20 Circuit board and its manufacture

Country Status (1)

Country Link
JP (1) JPH07176847A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004273495A (en) * 2003-03-05 2004-09-30 Tdk Corp Electronic component and method of manufacturing the same
KR100522385B1 (en) * 2001-07-10 2005-10-19 가부시키가이샤후지쿠라 Multilayer wiring board assembly, multilayer wiring board assembly component and method of manufacture thereof
US7263769B2 (en) 2004-10-20 2007-09-04 Matsushita Electric Industrial Co., Ltd. Multi-layered flexible print circuit board and manufacturing method thereof
US7367116B2 (en) 2003-07-16 2008-05-06 Matsushita Electric Industrial Co., Ltd. Multi-layer printed circuit board, and method for fabricating the same
US7543376B2 (en) 2004-10-20 2009-06-09 Panasonic Corporation Manufacturing method of flexible printed wiring board
CN102791083A (en) * 2011-05-18 2012-11-21 何忠亮 Circuit board communication process
US10887988B2 (en) 2018-09-26 2021-01-05 Nichia Corporation Circuit substrate, component-mounted substrate, and methods of manufacturing circuit substrate and component-mounted substrate

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100522385B1 (en) * 2001-07-10 2005-10-19 가부시키가이샤후지쿠라 Multilayer wiring board assembly, multilayer wiring board assembly component and method of manufacture thereof
JP2004273495A (en) * 2003-03-05 2004-09-30 Tdk Corp Electronic component and method of manufacturing the same
US7367116B2 (en) 2003-07-16 2008-05-06 Matsushita Electric Industrial Co., Ltd. Multi-layer printed circuit board, and method for fabricating the same
US7263769B2 (en) 2004-10-20 2007-09-04 Matsushita Electric Industrial Co., Ltd. Multi-layered flexible print circuit board and manufacturing method thereof
US7543376B2 (en) 2004-10-20 2009-06-09 Panasonic Corporation Manufacturing method of flexible printed wiring board
CN102791083A (en) * 2011-05-18 2012-11-21 何忠亮 Circuit board communication process
US10887988B2 (en) 2018-09-26 2021-01-05 Nichia Corporation Circuit substrate, component-mounted substrate, and methods of manufacturing circuit substrate and component-mounted substrate
US11864317B2 (en) 2018-09-26 2024-01-02 Nichia Corporation Sn—Bi and copper powder conductive paste in through hole of insulating substrate

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