JPH07176728A - High-breakdown-strength mos transistor - Google Patents

Abstract

PURPOSE:To form a diffused layer so as to be shallow irrespective of whether an offset region exists or not. CONSTITUTION:In a high-breakdown-strength MOS transistor, an epitaxial layer 2 of the other conductivity type is formed on a substrate 1 of one conductivity type, and a gate electrode 11 is formed, via a gate oxide film 10, on a surface-layer part between an offset region 4 of the other conductivity type and a source region 7 at the inside of a diffused layer 12 of one conductivity type, which has been formed on the epitaxial layer 2. In the high-breakdown- strength MOS transistor, the offset region. 4 is formed in a surface-layer part which strides the epitaxial layer 2 and the diffused layer 12. In addition, an isolation region 13 of one conductivity type is formed so as to surround the epitaxial layer 2 and the diffused layer 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high breakdown voltage MOS transistor, and more particularly to a lateral high breakdown voltage MOS transistor having an offset gate structure.

[0002]

2. Description of the Related Art For example, FIG. 2 shows an example of a concrete structure of a lateral high voltage MOS transistor having an offset gate structure.
Will be described.

In this high breakdown voltage MOS transistor, an N ^- type epitaxial layer 2 is formed on a P ^- type substrate substrate 1 as shown in FIG.
Then, a P ⁻ type diffusion layer 3 is formed by selective impurity diffusion. An N ⁻ type offset region 4 is formed in the diffusion layer 3 and a drain electrode 6 is formed in the surface layer portion via an N ⁺ type drain region 5. Further, an N ⁺ type source region 7 and a P ⁺ type contact region 8 adjacent thereto are formed on the surface layer portion of the diffusion layer 3, and a source electrode 9 is formed via the source region 7 and the contact region 8. Furthermore,
A gate electrode 11 made of polysilicon or the like is formed on the surface layer portion between the offset region 4 and the source region 9 with a gate oxide film 10 interposed therebetween.

Although not shown, the high breakdown voltage MOS transistor having the above structure is incorporated on the common substrate substrate 1 together with other semiconductor elements such as bipolar transistors, and other semiconductor elements such as bipolar transistors are included. It has a structure that is isolated by the isolation region.

In this high breakdown voltage MOS transistor, when a voltage is applied between the drain electrode 6 and the source electrode 9 to increase the drain potential, the offset region 4 and the diffusion layer 3 are formed.
Since the depletion layers a and a'expand from the junction with and, the voltage applied to the gate oxide film 10 is relaxed. In this way, a high breakdown voltage MOS transistor is realized without increasing the thickness of the gate oxide film.

[0006]

By the way, in the above-mentioned conventional high breakdown voltage MOS transistor, since the offset region 4 is provided in order to relax the drain potential, the diffusion layer 3 is completely depleted and punched. The diffusion layer 3 must be deeply formed so as not to pass through. As a result, the surface area of the diffusion layer 3 must be increased,
The device itself becomes larger and the epitaxial layer 2
In addition to increasing the cost, the cost is increased, and it takes time to form the diffusion layer 4 and the epitaxial layer 3.

As a means for solving this problem, Japanese Unexamined Patent Publication No.
High breakdown voltage MOS as disclosed in Japanese Patent Publication No. 2-95863.
There is a transistor. This MOS transistor is shown in FIG.
Unlike the above-mentioned high breakdown voltage MOS transistor, the diffusion layer 3 ′ is arranged so as to surround the source region 7 and the contact region 8 without providing an offset region, and the junction with the epitaxial layer 2 is gate-oxidized as shown in FIG. Membrane 10
It has a structure formed so as to be located immediately below. As a result, the diffusion layer 3'can be formed shallowly, and the problem described above can be solved easily.

However, in the MOS transistor shown in FIG. 3, since the junction between the diffusion layer 3'and the epitaxial layer 2 is located directly below the gate oxide film 10, the channel region immediately below the gate oxide film 10 is located. Since the impurity concentration distribution becomes non-uniform and it is difficult to design a predetermined breakdown voltage, it is necessary to lengthen the channel length immediately below the gate oxide film 10 to obtain the breakdown voltage. Furthermore,
Due to the expansion of the depletion layer c from the junction between the diffusion layer 3 ′ and the epitaxial layer 2, the drain electrode 6 and the gate electrode 11
There is a problem that the gate oxide film 10 is easily broken down because it is difficult to guarantee the breakdown voltage between them.

Therefore, the present invention has been proposed in view of the above problems, and an object thereof is to provide a high breakdown voltage MOS transistor capable of forming a shallow diffusion layer regardless of the presence of an offset region. is there.

[0010]

As a technical means for achieving the above object, the present invention forms an epitaxial layer of another conductivity type on a substrate substrate of one conductivity type and forms the epitaxial layer on the epitaxial layer. A high breakdown voltage MO in which a gate electrode is formed on a surface layer portion between an offset region and a source region of another conductivity type in a diffusion layer of one conductivity type via a gate oxide film.
The S-transistor is characterized in that the offset region is formed in a surface layer portion extending over the epitaxial layer and the diffusion layer. When this high breakdown voltage MOS transistor is incorporated in a common substrate together with other semiconductor elements such as a bipolar transistor, it is desirable to form an isolation region of one conductivity type so as to surround the diffusion layer in the epitaxial layer.

[0011]

In the high voltage MOS transistor according to the present invention,
By forming the offset region in the surface layer portion that straddles the epitaxial layer and the diffusion layer, the offset region and the epitaxial layer can be bonded to each other so that the epitaxial layer has the same potential as the drain potential. It is not necessary to make the depth as deep as the drain potential does not punch through, and it is possible to set the depth as shallow as the source potential does not punch through. Further, since there is no junction immediately below the gate oxide film, the concentration distribution in the surface layer of the diffusion layer becomes uniform, which facilitates the channel design.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a high voltage MOS transistor according to the present invention will be described with reference to FIG. The same or corresponding parts as those in FIGS. 2 and 3 are designated by the same reference numerals, and a duplicate description will be omitted.

The feature of the present invention resides in that the offset region 4 is formed in the surface layer portion extending over the epitaxial layer 2 and the diffusion layer 12. As a result, the offset region 4 and the epitaxial layer 2 are joined to make the epitaxial layer 2 have the same potential as the drain potential.

In this high breakdown voltage MOS transistor, when a voltage is applied between the drain electrode 6 and the source electrode 9, the depletion layer d spreads to the offset region 4 and is depleted, so that the drain potential can be relaxed and the gate oxidation can be performed. The dielectric breakdown of the film 10 can also be suppressed. It is possible to form the diffusion layer 12 shallow so that the source potential does not punch through.
Therefore, a sufficient breakdown voltage is secured unless the diffusion layer 12 is punched through. Further, in the channel region located immediately below the gate oxide film 10, the impurity concentration is uniform in the surface layer portion of the diffusion layer 12, and the channel design is easy.

Further, in the high breakdown voltage MOS transistor having the above-mentioned structure, the structure is incorporated on the common substrate substrate 1 together with other semiconductor elements such as bipolar transistors, so that the diffusion layer is formed around the MOS transistor, that is, in the epitaxial layer 2. By arranging the P-type isolation region 13 so as to surround 12 and performing insulation isolation, the offset region 4 and the epitaxial layer 2 are bonded to each other and the epitaxial layer 2 is brought to the same potential as the drain potential as described above. It becomes possible to do.

[0016]

According to the high withstand voltage MOS transistor of the present invention, since the diffusion layer can be formed shallow, the device can be made thinner and smaller, the product cost can be easily reduced, and the gate oxidation can be performed. It is possible to provide a high breakdown voltage MOS transistor capable of suppressing dielectric breakdown of a film as much as possible and ensuring a sufficient breakdown voltage, and its practical value is great.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a high voltage MOS transistor according to the present invention.

FIG. 2 is a sectional view showing a conventional example of a high voltage MOS transistor.

FIG. 3 is a sectional view showing another conventional example of a high voltage MOS transistor.

[Explanation of symbols]

 1 Substrate Substrate 2 Epitaxial Layer 4 Offset Region 7 Source Region 10 Gate Oxide Film 11 Gate Electrode 12 Diffusion Layer 13 Isolation Region

Claims (2)

[Claims] 1. An epitaxial layer of another conductivity type is formed on a substrate substrate of one conductivity type, and a diffusion layer of one conductivity type is formed between the offset region and the source region of the other conductivity type in the epitaxial layer. A high breakdown voltage MOS transistor having a gate electrode formed on a surface layer portion via a gate oxide film, wherein the offset region is formed in a surface layer portion extending between an epitaxial layer and a diffusion layer. 2. The high breakdown voltage MOS transistor according to claim 1, wherein an isolation region of one conductivity type is formed in the epitaxial layer so as to surround a diffusion layer.