JPH07176683A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain a high integration MCM by providing an I/O circuit connected with a circuit on a semiconductor chip through bonding pads and a wiring pattern for interconnecting the semiconductor chips and connecting the semiconductor chip with an external circuit through the I/O circuit on a semiconductor board. CONSTITUTION:A semiconductor chip 210 is flip-chip bonded onto semiconductor boards 110a, 110b. An I/O circuit for the circuit formed on semiconductor chips 210a, b is formed on the semiconductor board 110. I/O transistors 112a-c constituting the I/O circuit are arranged on the board side. The I/O circuit is connected with through holes by means of aluminium deposition. The semiconductor chips 210a, b are interconnected by means of an aluminium wiring 142 formed on the semiconductor board 110 through the I/O circuit. This constitution enhances the integration.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to multichip module technology.

[0002]

2. Description of the Related Art High integration and high speed of LSI are remarkable, and chips having a large number of pins and operating at a clock frequency of 100 MHz or more have appeared. With single-chip mounting, the delay of signals propagating through the package and the printed circuit board is large, and parasitic capacitance and inductance have become non-negligible in system design. Therefore, a multi-chip module has been considered in which a plurality of semiconductor chips are mounted on a substrate with bare chips at high density.

In such a multi-chip module, by shortening the wiring length and the load capacity, the delay between chips and the power consumption of the entire module can be suppressed.
Then, as disclosed in, for example, "Japanese Patent Laid-Open No. 64-67951", a method for further increasing the mounting density has been considered. According to the method described in this document, wiring terminals are arranged over the entire surface of the semiconductor element region via a multilayer wiring layer, and the semiconductor chip is connected via bonding pads so as to face the wiring of the mounting substrate. .

[0004]

The method described in the above literature is a method of high-density mounting when there are many wiring terminals.
When there are many wiring terminals, an input / output transistor region proportional to the number of wiring terminals is required on the semiconductor chip. Therefore, even if the number of wiring terminals is increased, the input / output transistor area is increased and the primitive element area, that is, the other circuit area is reduced. Further, even if the element is miniaturized, the area of the input / output transistor cannot be miniaturized accordingly due to the ESD countermeasure, and thus the ratio of the primitive element / input / output transistor region is further deteriorated.

[0005]

In order to solve the above problems, a semiconductor integrated circuit device of the present invention has a plurality of semiconductor chips on which circuits having a predetermined function are formed and these chips are arranged on the surface thereof. A semiconductor substrate is provided, and the semiconductor chip and the semiconductor substrate are flip-chip bonded via bonding pads formed on the surfaces thereof, and the semiconductor substrate is connected to the circuit on the semiconductor chip via the bonding pads. And a wiring pattern that connects between the semiconductor chips and between the semiconductor chip and the outside via an input / output circuit.

The bonding pads may be arranged in a grid pattern on the semiconductor chip.

[0007]

In the semiconductor integrated circuit device of the present invention, the input / output circuit of the circuit having the predetermined function on the semiconductor chip requires a large area. However, this input / output circuit is formed on the semiconductor substrate, It is connected to a circuit having a predetermined function on the semiconductor chip via a bonding pad. Therefore, it is not necessary to form this input / output circuit in the semiconductor chip, and the area of this input / output circuit makes the semiconductor chip small, or becomes an area for a circuit of a predetermined function on the semiconductor chip. can do.

[0008]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an external view of a configuration example of a semiconductor integrated circuit device of the present invention. This semiconductor integrated circuit device has a semiconductor chip 210 on a semiconductor substrate 110.
Is flip-chip bonded. The semiconductor chip 210 includes a CPU, its peripheral circuits, and a circuit having a predetermined function such as a memory.

FIG. 2 shows this flip chip bonding and shows a part of the cross section of the semiconductor substrate 110 and the semiconductor chips 210a, 210b. The semiconductor chips 210a and 210b are the large silicon substrate 1
Directly connected against 10. Semiconductor chip 210
The device regions of a and b and the pad region are multi-layered, and the surfaces of the semiconductor chips 210a and 210b are covered with a silicon oxide film and a polyimide insulating film 232a and 232b. A functional circuit is formed. And this circuit includes aluminum wiring 234a-
d, the semiconductor substrate 11 via the bonding pad 222
0 is connected to the circuit above.

FIG. 3 shows the arrangement of the bonding pads 222 on the semiconductor chips 210a and 210b. The bonding pads 222 are arranged not only on the periphery of the semiconductor chips 210a and 210b but also inside. Then, elements 212a to 212d forming a circuit having a predetermined function are formed between the respective bonding pads 222 (FIG. 2).

The surface of the semiconductor substrate 110 is also covered with a silicon oxide film and polyimide insulating films 232a and 232b, and a bonding pad 222 is provided. Semiconductor substrate 1
10 and the semiconductor chips 210a and 210b are mechanically bonded by the bump 122, and also electrically connected. Then, on the semiconductor substrate 110, input / output circuits of the circuits formed on the semiconductor chips 210a and 210b are formed. This input / output circuit is composed of an open collector transistor, a buffer composed of CMOS or the like, a bidirectional buffer, etc., and the input / output transistors 112a to 112c constituting this circuit are arranged on the side of this substrate. . The input / output circuit and the bump 122 are connected by a through hole formed by aluminum vapor deposition. The semiconductor chips 210a and 210b are connected by an aluminum wiring 142 formed on the semiconductor substrate 110 via these input / output circuits. Aluminum wiring 234a-d
Is formed in the same process as the conventional one.

By using the semiconductor substrate 110 and arranging the bonding pads 222 in a grid pattern as described above, it becomes possible to form a finer pattern than when a printed circuit board is used. Even LSIs with O-pads can be flip-chip bonded.

Further, the semiconductor chip 210 is connected to the silicon mounting substrate 110 so as to face the semiconductor chip 210.
The a and b sides are all primitive circuits, and the circuit for input / output is different from the usual case, and the silicon mounting substrate 110
Since it is formed above, the elements (FET, transistor, etc.) forming the input / output circuit can be minutely formed. In particular, as the elements of the semiconductor chip become finer, the circuit for input / output requires a large area, the area on the semiconductor chip cannot be ignored, and even if the bonding pads 222 are arranged in a grid pattern, the area is high. There will be limits to integration. But,
Since the input / output circuits are formed on the substrate 110, they are stacked as a result, so that higher integration is possible.

Since there is no large-sized input / output transistor on the side of the semiconductor chips 210a, 210b, latch-up due to it is eliminated. And the silicon substrate 1
Since the input / output transistors 112a to 112c can be arranged on the transistor 10, it is possible to form a sufficiently large transistor as an ESD countermeasure. In addition, the transistors 112a to
Since the c-interval can be sufficiently secured, latch-up hardly occurs. In this way, a highly integrated multi-chip module having a higher degree of integration can be constructed.

The present invention is not limited to the above-described embodiment, but various modifications can be made.

For example, the semiconductor chip 210 on the substrate 110.
Some elements of the circuit on a and b may be made. In addition, as shown in FIG. 4, the semiconductor device configured by the silicon substrate 110 and the semiconductor chip 210 as shown in FIG. 1 is further formed on the semiconductor mounting substrate 310 as a multi-chip module in the same manner as in FIG. A configuration in which three layers are stacked is also possible.

Further, the semiconductor substrate and the semiconductor chip can be manufactured by different processes. For example, one may be configured as a bipolar and one may be configured as a CMOS.
Here, it is preferable that one having an input / output circuit is a bipolar and the other has a CMOS structure.

[0019]

As described above, according to the semiconductor integrated circuit device of the present invention, it becomes unnecessary to form an input / output circuit of a circuit having a predetermined function on the semiconductor chip on the semiconductor chip. Only, the semiconductor chip can be made small, or can be used as a region for a circuit having a predetermined function on the semiconductor chip, so that the degree of integration can be further increased.

[Brief description of drawings]

FIG. 1 is a diagram showing an appearance of a configuration example of a semiconductor integrated circuit device of the present invention.

FIG. 2 shows a semiconductor substrate 110 and a semiconductor chip 210a,
The figure which showed a part of cross section about b.

FIG. 3 is a diagram showing an arrangement of bonding pads 222.

FIG. 4 is a diagram showing an appearance of a configuration example of a semiconductor integrated circuit device of the present invention.

[Explanation of symbols]

110 ... Semiconductor substrate, 210, 210a, b ... Semiconductor chip, 122, 222 ... Bonding pad, 142,
234a-d ... Aluminum wiring.

Claims (2)

[Claims] 1. A semiconductor device having a plurality of semiconductor chips on which a circuit having a predetermined function is formed, and a semiconductor substrate having the chips arranged on the surface thereof, wherein the semiconductor chip and the semiconductor substrate are formed on the surfaces thereof. The semiconductor substrate is flip-chip bonded via a bonding pad, the semiconductor substrate is connected to a circuit on the semiconductor chip via the bonding pad, an input / output circuit between the semiconductor chip via the input / output circuit, and A semiconductor integrated circuit device having a wiring pattern for connecting between the semiconductor chip and the outside. 2. The semiconductor integrated circuit device according to claim 1, wherein the bonding pads are arranged in a grid pattern on the semiconductor chip.