JP2002368186A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, on which multiple chips can be mounted with the reduced number of wiring layers by reducing intersecting of wirings between semiconductor chips. SOLUTION: The semiconductor chip is integrally formed, by stacking in the thickness direction and second semiconductor chips 11 and 16 having terminal surfaces 11A and 16A, which are respectively provide with terminals and first and second substrates 12 and 17, which are respectively connected o the terminals and have conductive vias 15 or via lands 15L for making electrically connectings in the thickness direction and the chips 11 and 16 are stacked with the surfaces 11A and 16A facing in directions opposite to each other, with respect to the thickness direction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip package (or a multi-chip module) in which a plurality of semiconductor chips are stacked in a thickness direction and built in, and is used particularly when mixed different types of semiconductor chips. Things.

[0002]

2. Description of the Related Art In recent years, multi-chip packages have become
It is widely used in products that require thinning and miniaturization, such as cards and mobile phones. The multi-chip package is a package in which a plurality of semiconductor chips are stacked and built in the thickness direction, and is suitable for thinning and miniaturization.

FIG. 11 is a sectional view showing the structure of a conventional multichip module.

As shown in the figure, a multi-chip module has two semiconductor chips 101 and 102 mounted thereon. The semiconductor chip 101 is mounted on the wiring board 103. The wiring board 103 includes a semiconductor chip 101
The wiring layer 104 electrically connected to the terminal is formed. One main surface of the semiconductor chip 101 on which the terminals are formed is hereinafter referred to as a device surface.

The semiconductor chip 102 is mounted on the wiring board 1.
05. The wiring board 105 includes a wiring layer 10 electrically connected to terminals of the semiconductor chip 102.
6 are formed. One main surface of the semiconductor chip 102 on which the terminals are formed is hereinafter referred to as a device surface.
The two semiconductor chips 101 and 102 are stacked so as to overlap in the thickness direction.
The device surfaces on which the terminals 01 and 102 are formed are arranged so as to face in the same direction.

A prepreg 107 made of a glass epoxy substrate or the like is provided around the semiconductor chip 101 between the wiring board 103 and the wiring board 105. A substrate 108 is formed on the other main surface of the semiconductor chip 102 facing the device surface. Wiring board 1
A prepreg 109 made of a glass epoxy substrate or the like is provided around the semiconductor chip 102 between the substrate 05 and the substrate 108.
Is provided.

Further, a bump 110 for external connection is formed on the substrate 108. The prepreg 107, the wiring substrate 105, the prepreg 109, and the substrate 108 are provided with vias 111 for electrically connecting the wiring layers 104 and 106 and the bumps 110.

When a plurality of semiconductor chips of the same type are formed into a multichip, the positions of the inner pads of all the chips are the same. Therefore, the structure as shown in FIG. 11 has an advantage that the wiring layers for all the semiconductor chips can be made the same.

[0009]

However, when an existing logic chip and an existing memory chip are to be made into multi-chips, the structure shown in FIG. 11 causes a large number of cross wirings, as shown in FIG. At least two or more wiring routing layers 112 and 113 must be provided. This is because, in the existing chip, as shown in FIG.
Assuming that each of the semiconductor chips 101 and 102 is mounted on a single chip package and that these are arranged two-dimensionally on a mounting board, the arrangement of the inner pads of each of the semiconductor chips 101 and 102 may be determined. It is a big factor.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a semiconductor device capable of reducing crossing of wiring between semiconductor chips and forming a multichip with a small number of wiring layers. And

[0011]

To achieve the above object, a first semiconductor device according to the present invention comprises first and second semiconductor chips each having a terminal surface on which a terminal is formed. A semiconductor device which is electrically connected to terminals and is integrated by laminating in a thickness direction first and second substrates having conductive vias or via lands for making electrical connection in a thickness direction. The first semiconductor chip and the second semiconductor chip are stacked with their terminal surfaces facing in opposite directions in the thickness direction.

In order to achieve the above object, a second semiconductor device according to the present invention has a terminal surface on which a terminal is formed, and first and second semiconductor chips stacked in a thickness direction. A pad on which the first semiconductor chip is mounted and to which the terminal is connected; a conductive via or via land for making an electrical connection in a thickness direction; and a pad formed between the pad and the conductive via or via land. A first substrate having a first wiring layer formed thereon, a pad on which the second semiconductor chip is mounted, and a pad to which the terminal is connected, and a conductive via or via land for making electrical connection in a thickness direction. A second substrate having a second wiring layer formed between the pad and the conductive via or via land, wherein the first semiconductor chip and the second semiconductor chip are:
The semiconductor device is characterized in that the terminals are stacked with the terminal surfaces facing each other in the thickness direction.

In order to achieve the above object, a third semiconductor device according to the present invention has a terminal surface on which terminals are formed, and a first and a second semiconductor chips stacked in a thickness direction. A pad on which the first semiconductor chip is mounted and to which the terminal is connected; a conductive via or via land for making an electrical connection in a thickness direction; and a pad formed between the pad and the conductive via or via land. A first substrate having a first wiring layer formed thereon, a pad on which the second semiconductor chip is mounted, and a pad to which the terminal is connected, and a conductive via or via land for making electrical connection in a thickness direction. And a second substrate having a second wiring layer formed between the pad and the conductive via or via land, wherein a terminal surface of the first semiconductor chip and a terminal of the second semiconductor chip are provided. What is a surface? Characterized in that it is arranged so as to face are.

In order to achieve the above object, a fourth semiconductor device according to the present invention has a terminal surface on which terminals are formed, and first and second semiconductor chips stacked in a thickness direction. A pad on which the first semiconductor chip is mounted and to which the terminal is connected; a conductive via or via land for making an electrical connection in a thickness direction; and a pad formed between the pad and the conductive via or via land. A first substrate having a first wiring layer formed thereon, a pad on which the second semiconductor chip is mounted, and a pad to which the terminal is connected, and a conductive via or via land for making electrical connection in a thickness direction. And a second substrate having a second wiring layer formed between the pad and the conductive via or via land, wherein a terminal surface of the first semiconductor chip and a terminal of the second semiconductor chip are provided. What is a surface? Characterized in that it is arranged so as to face opposite outer are.

In order to achieve the above object, a fifth semiconductor device according to the present invention comprises a first and a second semiconductor chips each having a terminal surface on which a terminal is formed; A pad connected to a terminal of the first semiconductor chip and a first wiring layer connected to the pad;
A pad connected to a terminal of the second semiconductor chip and a second wiring layer connected to the pad on a second main surface opposite to the main surface of the first semiconductor chip; A first conductive via for electrically connecting the wiring layer and the second wiring layer, and a first conductive via on the first and second main surfaces, respectively.
A second substrate having a first substrate on which a second semiconductor chip is mounted and a second conductive via electrically connected to the first conductive via for making electrical connection in a thickness direction; It is characterized by being integrated by laminating a substrate in the thickness direction.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the embodiments of the present invention, the basic structure of a multichip package to which the present invention is applied will be described in detail with reference to FIGS. In the description, common parts are denoted by common reference symbols throughout the drawings.

FIG. 1 is a sectional view showing the basic structure of a multi-chip package. Here, an example in which two semiconductor chips are mounted is shown.

As shown in the figure, a semiconductor chip 11 is mounted on a first main surface of a wiring board 12 by using a flip chip method or the like. On a first main surface (device surface) 11A of the semiconductor chip 11, terminals of a circuit formed in the chip are provided. On the first main surface of the wiring board 12, connection pads 13 to which terminals of the semiconductor chip 11 are connected, wiring patterns 14, and via lands 14
L is formed. Further, the wiring board 12 has a conductive via (hereinafter referred to as a via) 15 which is conductive in the thickness direction of the wiring board, and a via land 1 formed on the via 15.
5L are formed. In the mounting, the semiconductor chip 1
Device surface 11A provided with one terminal and wiring board 1
The terminals of the semiconductor chip 11 are electrically connected to the connection pads 13. The via lands 14L and 15L are patterns formed around the via on the substrate or on another substrate to which the via is connected in order to ensure electrical connection with the via provided on the substrate.

The semiconductor chip 16 is connected to a wiring board 17.
Is mounted on the first main surface of the substrate by using a flip chip method or the like. On a first main surface (device surface) 16A of the semiconductor chip 16, terminals of a circuit formed in the chip are provided. On the first main surface of the wiring board 17, connection pads 18 to which terminals of the semiconductor chip 16 are connected, wiring patterns 19, and via lands 19L are formed. Further, a via 15 that is conductive in the thickness direction of the wiring board and a via land 15L formed on the via 15 are formed in the wiring board 17. In the mounting, the device surface 1 provided with the terminals of the semiconductor chip 16 is provided.
6A and the first main surface of the wiring board 17 are arranged to face each other, and the terminals of the semiconductor chip 16 are connected to the connection pads 18.
Is electrically connected to

Further, a wiring board 20 is arranged on a second main surface of the semiconductor chip 11 opposite to the first main surface. A board 21 is disposed on the wiring board 17. A prepreg 22 is arranged around the semiconductor chip 11 between the wiring board 12 and the wiring board 20.
The prepreg 22 is formed with a via 15 that is conductive in the thickness direction, a via land 15L on the via 15, and a wiring pattern for connecting the vias 15 as necessary.

A prepreg 23 is disposed around the semiconductor chip 16 between the wiring board 12 and the wiring board 17. The prepreg 23 includes vias 15 that are conductive in the thickness direction, via lands 15L on the vias 15, and wiring patterns 1 that connect the vias 15 as necessary.
5P is formed. The prepregs 22 and 23 are made of, for example, a glass epoxy substrate in which a glass cloth is impregnated with a resin.

The wiring board 20 is provided with a via 15 that is conductive in the thickness direction of the wiring board. Pads 24 are provided on the wiring board 20. Further, a bump 25 for external connection is formed on the pad 24. The bumps 25 are connected to the wiring board 17 and the prepreg 2.
3, wiring board 12, prepreg 22, and wiring board 20
Are electrically connected to at least the terminals of the semiconductor chip 11 via the wiring pattern 14 or to the terminals of the semiconductor chip 16 via the wiring pattern 19 by the vias 15 for internal connection, the via lands 15L, and the pads 24 provided respectively. It is connected to the.

FIGS. 2 to 4 are plan views showing examples of the layout of patterns and vias on a wiring board or prepreg in a multichip package.

FIG. 2 shows patterns and vias on the wiring board 12 on which the semiconductor chip 11 is mounted. Broken line 1
The area indicated by 1B is an area where the semiconductor chip 11 is mounted. The pad 13 provided within the broken line 11B has
The terminals of the semiconductor chip 11 are connected. Vias 15 and via lands 15L are provided in the peripheral region of each side of the wiring board 12. A wiring pattern 14 is formed between the pad 13 and the via land 15L, and the pad 13 is electrically connected to the via 15 and the via land 15L.

FIG. 3 shows a layout of vias on the prepreg 22. The via 15 and via land 15L of the prepreg 22 are electrically connected to the via 15 and via land 15L of the wiring board 12.

FIG. 4 shows a layout on the wiring board 20 on which the bumps 25 are formed. This wiring board 2
On the pad 0, a pad 24 on which a bump 25 is formed is provided. The via 15 and the via land 15L are formed in the wiring board 20. The via 15 and the via land 15L correspond to the via 15 and the via land 1 of the prepreg 22.
It is electrically connected to 5L. Further, the wiring board 20
A wiring pattern 26 is formed between the via land 15L and the pad 24, and the via 15 and the via land 15 are formed.
L and the pad 24 are electrically connected.

The multi-chip package having the sectional structure shown in FIG. 1 has a wiring board 12 on which a semiconductor chip 11 is mounted, a wiring board 17 on which a semiconductor chip 16 is mounted, between a wiring board 20 and a board 21. And prepreg 22,
23 are arranged and heated and pressed, and are integrally formed between layers using an insulating material as an adhesive or the like.

Next, first and second embodiments of the present invention will be described below in order.

[First Embodiment] The first embodiment shows an example in which two semiconductor chips are stacked.

FIG. 5 is a sectional view showing the structure of the multi-chip package according to the first embodiment.

As shown in FIG. 5, the semiconductor chip 11
It is mounted on the first main surface of the wiring board 12 using a flip chip method or the like. On a first main surface (device surface) 11A of the semiconductor chip 11, terminals of circuits formed in the chip are provided. On the first main surface of the wiring substrate 12, connection pads 13 to which terminals of the semiconductor chip 11 are connected and a wiring pattern 14 are formed.
Further, a conductive via (hereinafter, referred to as a via) 15 which is conductive in the thickness direction of the wiring board 12 and a via land 15L formed on the via 15 are formed on the wiring board 12. In the mounting, the device surface 11A on which the terminals of the semiconductor chip 11 are provided and the first main surface of the wiring board 12 face each other, and the terminals of the semiconductor chip 11 are electrically connected to the connection pads 13. Is done.

The semiconductor chip 16 is connected to the wiring board 17.
Is mounted on the first main surface of the substrate by using a flip chip method or the like. On a first main surface (device surface) 16A of the semiconductor chip 16, terminals of a circuit formed in the chip are provided. On the first main surface of the wiring board 17, connection pads 18 to which terminals of the semiconductor chip 16 are connected and a wiring pattern 19 are formed. further,
In the wiring board 17, vias 15 that are conductive in the thickness direction of the wiring board 17 and via lands 15L formed on the vias 15 are formed. In the mounting, the device surface 16 </ b> A provided with the terminals of the semiconductor chip 16 and the first main surface of the wiring board 17 are arranged to face each other, and the terminals of the semiconductor chip 16 are electrically connected to the connection pads 18. Is done.

The device surface (surface on which the terminals are provided) 11A of the semiconductor chip 11 and the device surface 16A of the semiconductor chip 16 are arranged to face each other with the wiring boards 12 and 17 interposed therebetween. . Such an arrangement shown in FIG. 5 is different from that shown in FIG. 13 in that two semiconductor chips arranged in a plane on a mounting board or the like as shown in FIG. This is the same as folding the chip on the left chip.
Therefore, even if a semiconductor chip having connection wirings as shown in FIG. 13 is used in this embodiment, no crossing of the wirings occurs.

Further, the first main surface 1 of the semiconductor chip 11
The wiring substrate 20 is arranged on the second main surface facing 1A. In the wiring board 20, a via 15 that is conductive in the thickness direction of the wiring board 20 is formed. In addition, a substrate 21 is disposed on a second main surface of the semiconductor chip 16 that faces the first main surface 16A. Substrates 20, 21
Are for protecting the semiconductor chips 11 and 16, respectively.

A prepreg 22 is arranged around the semiconductor chip 11 between the wiring board 12 and the wiring board 20. The prepreg 22 includes a via 15 that is conductive in the thickness direction, and a via land 15L formed on the via 15.
Are formed. Further, a prepreg 23 is arranged around the semiconductor chip 16 between the wiring board 17 and the board 21. The prepregs 22 and 23 are made of, for example, a glass epoxy substrate in which a glass cloth is impregnated with a resin.

On the wiring board 20, pads 24 electrically connected to the vias 15 are provided. further,
On the pad 24, a bump 25 for external connection is formed. The bumps 25 are formed on the semiconductor chip 11 via at least the wiring pattern 14 by the vias 15 for internal connection, the via lands 15L, and the pads 24 provided on the wiring boards 17, 12, the prepreg 22, and the wiring board 20, respectively. It is electrically connected to a terminal or to a terminal of the semiconductor chip 16 via a wiring pattern 19.

In this multi-chip package, a wiring board 12 on which a semiconductor chip 11 is mounted, a wiring board 17 on which a semiconductor chip 16 is mounted, and prepregs 22 and 23 are arranged between a wiring board 20 and a board 21. Are heated and pressurized, and are integrally formed between layers using an insulating material or the like as an adhesive.

The thickness of each of the semiconductor chips 11 and 16 is about 30 μm to 200 μm, preferably about 50 μm to 150 μm. Also, the wiring board 1
Reference numerals 2 and 17 are made of an insulating substrate such as a polyimide substrate or a printed laminate having a thickness of about 40 μm.

Next, a description will be given of a multichip package according to a modification of the first embodiment.

FIG. 7 is a sectional view showing the structure of a multi-chip package according to a modification of the first embodiment.

In the first embodiment, the semiconductor chip 11 is mounted on the first main surface of the wiring board 12, and the semiconductor chip 16 is mounted on the first main surface of the wiring board 17. According to the second embodiment, the semiconductor chip 16 is mounted on a second main surface of the wiring substrate 12 opposite to the first main surface.

On the second main surface of the wiring board 12, connection pads 18 to which terminals of the semiconductor chip 16 are connected are provided.
Also, a wiring pattern 19 and a via land 15L are formed. In the mounting, the device surface 16A provided with the terminals of the semiconductor chip 16 and the second main surface of the wiring board 12 are arranged so as to face each other, and the terminals of the semiconductor chip 16 are electrically connected to the connection pads 18. Is done.

As a result, the device surface (surface on which the terminals are provided) 11A of the semiconductor chip 11 and the device surface 16A of the semiconductor chip 16 are arranged so as to face each other with the wiring substrate 12 interposed therebetween. The arrangement shown in FIG. 7 is similar to the arrangement shown in FIG. 5, except that two semiconductor chips arranged in a plane as shown in FIG. This is the same as bending the right chip on the left chip as shown in FIG. Therefore, even if the semiconductor chip having the connection wirings as shown in FIG. 13 is used in the first modification, no crossing of the wirings occurs.

Further, as shown in FIG.
One of the chips 1 and 16 may have a smaller size than the other chips. FIG. 8 shows a case where the size of the semiconductor chip 16 is smaller than the size of the semiconductor chip 11. The effect in this case is the same as in the first embodiment.

As described above, in the first embodiment, the device surfaces on which the terminals of the two semiconductor chips are formed are arranged so as to face each other.
Intersecting wirings provided between semiconductor chips can be reduced, and a multi-chip structure can be realized with a small number of wiring layers.

[Second Embodiment] Next, a semiconductor device according to a second embodiment of the present invention will be described. This embodiment also shows an example in which two semiconductor chips are stacked, as in the first embodiment.

FIG. 9 is a sectional view showing the structure of the multi-chip package according to the second embodiment. The same parts as those in the configuration of the first embodiment are denoted by the same reference numerals.

As shown in FIG. 9, the semiconductor chip 11
It is mounted on the first main surface of the wiring board 12 using a flip chip method or the like. On a first main surface (device surface) 11A of the semiconductor chip 11, terminals of circuits formed in the chip are provided. On the first main surface of the wiring board 12, connection pads 13 to which terminals of the semiconductor chip 11 are connected and a wiring pattern 14 are formed.
Further, a via 15 that is conductive in the thickness direction of the wiring board 12 and a via land 15L formed on the via 15 are formed in the wiring board 12. In the mounting, a device surface 11A provided with terminals of the semiconductor chip 11;
The terminals of the semiconductor chip 11 are electrically connected to the connection pads 13 so as to face the first main surface of the wiring board 12.

The semiconductor chip 16 is connected to the wiring board 17.
Is mounted on the first main surface of the substrate by using a flip chip method or the like. On a first main surface (device surface) 16A of the semiconductor chip 16, terminals of a circuit formed in the chip are provided. On the first main surface of the wiring board 17, connection pads 18 to which terminals of the semiconductor chip 16 are connected, wiring patterns 19, and via lands 15L are formed. In the mounting, the device surface 16 </ b> A provided with the terminals of the semiconductor chip 16 and the first main surface of the wiring board 17 are arranged to face each other, and the terminals of the semiconductor chip 16 are electrically connected to the connection pads 18. Is done.

The device surface (surface on which the terminals are provided) 11A of the semiconductor chip 11 and the device surface 16A of the semiconductor chip 16 are arranged so as to face outwardly opposite directions. That is, two semiconductor chips 11,
16 are arrange | positioned so that back surfaces may mutually face.

Such an arrangement shown in FIG. 9 is different from the arrangement shown in FIG. 13 in that two semiconductor chips arranged two-dimensionally on a mounting board or the like are shown on the drawing with an axis between the chips.
This is the same as bending the right chip below the left chip as shown in FIG. Therefore, even if a semiconductor chip having connection wirings as shown in FIG. 13 is used in this embodiment, no crossing of wirings occurs.

Further, a prepreg 27 is provided around the semiconductor chips 11 and 16 between the wiring board 12 and the wiring board 17.
Is arranged. The prepreg 27 has a via 15 that is conductive in the thickness direction. The prepreg 27
For example, it is made of a glass epoxy substrate in which a glass cloth is impregnated with a resin.

On the wiring board 12, pads 24 electrically connected to the vias 15 are provided. further,
On the pad 24, a bump 25 for external connection is formed. The bumps 25 are provided to the terminals of the semiconductor chip 11 via at least the wiring patterns 14 or the wiring patterns 19 by the internal connection vias 15, via lands 15 L, and pads 24 provided on the prepreg 27 and the wiring board 12, respectively. Are electrically connected to the terminals of the semiconductor chip 16 through the terminals.

This multi-chip package includes a wiring board 12 on which a semiconductor chip 11 is mounted and a semiconductor chip 1
6 are mounted, and the prepreg 2
7 are arranged and heated and pressurized, and are integrally formed using an insulating material as an adhesive between the layers.

The thickness of each of the semiconductor chips 11 and 16 is about 30 μm to 200 μm, preferably 50 μm.
It is about μm to 150 μm. Each of the wiring substrate 12 and the wiring substrate 17 is formed of an insulating substrate such as a polyimide substrate or a printed laminate having a thickness of about 40 μm.

Note that the second embodiment shown in FIG. 9 includes a second main surface (back surface) facing the first main surface of the semiconductor chip 11 and a first main surface of the semiconductor chip 16. Although the example in which the second main surface (rear surface) opposed to is in direct contact is shown,
An insulating material such as an adhesive or a substrate may be formed between the back surface of the semiconductor chip 11 and the back surface of the semiconductor chip 14.

As described above, in the second embodiment, the wiring provided between the semiconductor chips intersects by arranging the device surfaces of the two semiconductor chips so as to face in opposite directions (outside). Can be reduced, and a multi-chip can be realized with a small number of wiring layers.

In the first and second embodiments described above, an example in which two semiconductor chips are stacked is shown. However, the present invention is not limited to two semiconductor chips stacked. . The present invention is also applicable to a case where two or more semiconductor chips are stacked. In addition, various modifications can be made without departing from the spirit of the present invention.

[0059]

As described above, according to the present invention, it is possible to provide a semiconductor device capable of reducing crossing of wirings between semiconductor chips and forming a multi-chip with a small number of wiring layers.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a basic structure of a multi-chip package.

FIG. 2 is a plan view showing a pattern layout of a wiring board on which a semiconductor chip is mounted in a multi-chip package.

FIG. 3 is a plan view showing a pattern layout of a prepreg in a multi-chip package.

FIG. 4 is a plan view showing a pattern layout of a wiring board on which bumps are formed in a multi-chip package.

FIG. 5 is a sectional view showing the structure of the multi-chip package according to the first embodiment of the present invention.

FIG. 6 is a perspective view conceptually showing wiring of the multi-chip package according to the first embodiment.

FIG. 7 is a cross-sectional view illustrating a structure of a multi-chip package according to a modification of the first embodiment.

FIG. 8 is a cross-sectional view illustrating a structure of a multi-chip package according to another modification of the first embodiment.

FIG. 9 is a sectional view showing a structure of a multi-chip package according to a second embodiment of the present invention.

FIG. 10 is a perspective view conceptually showing wiring of the multi-chip package according to the second embodiment.

FIG. 11 is a cross-sectional view showing the structure of a conventional multichip module.

FIG. 12 is a sectional view showing the structure of another conventional multi-chip module.

FIG. 13 is a perspective view conceptually showing wiring of a single-chip package arranged two-dimensionally on a conventional mounting board.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Semiconductor chip 11A ... 1st main surface (device surface) of semiconductor chip 11 12 ... Wiring board 13 ... Connection pad 14 ... Wiring pattern 14L ... Via land 15 ... Conductive via (via) 15L ... Via land 15P ... Wiring pattern 16 ... Semiconductor chip 16A ... First main surface (device surface) of semiconductor chip 16 17 ... Wiring board 18 ... Connection pad 19 ... Wiring pattern 19L ... Via land 20 ... Wiring board 21 ... Substrate 22 ... Prepreg 23 ... Prepreg 24 ... Pad 25 ... Bump 26 ... Wiring pattern 27 ... Prepreg

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takashi Yamazaki 1 Toshiba-cho, Komukai-Toshiba-cho, Saitama-ku, Kawasaki-shi, Kanagawa Inside Toshiba Microelectronics Center Co., Ltd.

Claims (10)

[Claims] 1. A first and a second semiconductor chip each having a terminal surface on which a terminal is formed, and a conductive via or via land electrically connected to the terminal and for making an electrical connection in a thickness direction. A semiconductor device integrated by laminating in a thickness direction a first and a second substrate, wherein the first semiconductor chip and the second semiconductor chip are arranged in the thickness direction. , Wherein the semiconductor devices are stacked with their terminal surfaces facing each other. 2. A semiconductor device comprising: first and second semiconductor chips, each having a terminal surface on which a terminal is formed, stacked in a thickness direction, the first semiconductor chip being mounted, and the terminals being connected to each other; A first substrate having a pad, a conductive via or via land for making electrical connection in a thickness direction, and a first wiring layer formed between the pad and the conductive via or via land; A second semiconductor chip mounted thereon, a pad to which the terminal is connected, a conductive via or via land for making an electrical connection in a thickness direction, and a second pad formed between the pad and the conductive via or via land. A second substrate having two wiring layers, wherein the first semiconductor chip and the second semiconductor chip are stacked with the terminal surfaces facing each other in the thickness direction. Features Semiconductor device. 3. A first and a second semiconductor chip, each having a terminal surface on which a terminal is formed, stacked in a thickness direction, and the first semiconductor chip is mounted, and the terminal is connected. A first substrate having a pad, a conductive via or via land for making electrical connection in a thickness direction, and a first wiring layer formed between the pad and the conductive via or via land; A second semiconductor chip mounted thereon, a pad to which the terminal is connected, a conductive via or via land for making an electrical connection in a thickness direction, and a second pad formed between the pad and the conductive via or via land. A second substrate having two wiring layers, wherein a terminal surface of the first semiconductor chip and a terminal surface of the second semiconductor chip are arranged so as to face each other. Semiconductor equipment Place. 4. The first and second semiconductor chips each have a back surface facing the terminal surface, and a first insulating substrate is disposed on the back surface of the first semiconductor chip. 4. The semiconductor device according to claim 3, wherein a second insulating substrate is disposed on a back surface of the second semiconductor chip. 5. A semiconductor device comprising: first and second semiconductor chips, each having a terminal surface on which a terminal is formed, stacked in a thickness direction; and mounting the first semiconductor chip, and connecting the terminals. A first substrate having a pad, a conductive via or via land for making electrical connection in a thickness direction, and a first wiring layer formed between the pad and the conductive via or via land; A second semiconductor chip mounted thereon, a pad to which the terminal is connected, a conductive via or via land for making an electrical connection in a thickness direction, and a second pad formed between the pad and the conductive via or via land. A second substrate having two wiring layers, wherein a terminal surface of the first semiconductor chip and a terminal surface of the second semiconductor chip are arranged so as to face mutually opposite outer sides. Characterized by Semiconductor device. 6. The semiconductor device according to claim 1, further comprising a third substrate formed around the first and second semiconductor chips between the first substrate and the second substrate. 6. The semiconductor device according to 2 or 5. 7. The semiconductor device according to claim 7, wherein a conductive via for electrically connecting a first wiring layer of the first substrate and a second wiring layer of the second substrate is formed on the third substrate. 7. The semiconductor device according to claim 6, wherein: 8. The method according to claim 1, wherein the conductive vias of the first and second substrates electrically connect a first wiring layer of the first substrate and a second wiring layer of the second substrate. 4. The semiconductor device according to claim 2, wherein: 9. A first and second semiconductor chip each having a terminal surface on which a terminal is formed, a pad to which a terminal of the first semiconductor chip is connected on a first main surface, and A pad connected to a terminal of the second semiconductor chip and a second pad connected to the pad, on a second main surface opposite to the first main surface, the first wiring layer being connected to the first wiring layer; And a first conductive via electrically connecting the first wiring layer and the second wiring layer in a thickness direction, and a first conductive via on the first and second main surfaces is provided. A first substrate on which first and second semiconductor chips are mounted, respectively; and a second conductive layer electrically connected to the first conductive via and electrically connecting in a thickness direction. A semiconductor device, wherein a second substrate having a via is integrated with a second substrate by laminating in a thickness direction. 10. The first and second semiconductor chips each have a back surface facing the terminal surface, and a first insulating substrate is disposed on the back surface of the first semiconductor chip. The semiconductor device according to claim 9, wherein the second substrate is disposed on a back surface of the second semiconductor chip.