JPH07176150A - Digital data recording method - Google Patents

Abstract

PURPOSE:To enhance an error correcting ability and to reduce the scale of circuits by arranging inputted data into prescribed words, correcting and coding them and also constituting a code word with plural symbols of one track. CONSTITUTION:At the time of recording data, inputted data are made to be data A at every data of (mXk1) in a formatter 10 to be stored in a first memory 11. Data A are inputted from the memory 11 to a first error correction and coding circuit 12 and a first error correction and coding is performed to make data E, which are outputted to the memory 11. Data A and E of the memory 11 are divided into (f) divisions to be data J and are outputted successively to a second error correction circuit 13. In the circuit 13, the error correction and coding is performed to data J and a parity is generated to make data V-The circuit 13 outputs data J and V to a third error correction and coding circuit 14. In the circuit 14, data J and V are constituted to be a block and the error correction and coding is performed and a parity is generated to be added to the block, which is outputted to a recording circuit 15 to be recorded on a magnetic tape 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording method for recording digital data on a recording medium.

[0002]

2. Description of the Related Art Currently, a digital VTR for digitizing video and audio, compressing it, and recording and reproducing it on a magnetic tape.
Has been put to practical use. This digital VTR performs recording and reproduction by forming the track shown in FIG. 18 by helical scan recording. Here, 100 is a tape, 101 is a track, 103 is a tracking information area, 104 is an audio signal recording area, 105 is a video signal recording area, 106 is an auxiliary signal recording area, 107 is a gap, and 108 is a sync block.

An area formed by one scan of the head is a track 101, and the track 101 has a tracking information area 103, an audio signal recording area 104, a video signal recording area 105, and an auxiliary signal recording area 1 as shown in FIG.
06 and the gap 107. The audio signal area 104 is an area in which an audio signal is subjected to audio signal processing, and then subjected to error correction coding and predetermined signal processing to be recorded. A video signal area 105 is subjected to video signal processing of the video signal and then subjected to error correction coding and predetermined. This is an area for performing signal processing and recording. The tracking information area 103 is an area for recording information for checking the position of the head on the tape at the time of recording or reproducing, and the auxiliary signal area 106 stores information for searching for a video signal or an audio signal. This is an area for recording. The gap 107 is an area for absorbing an error in the recording position when rewriting each area individually.

FIG. 19 is a block diagram of a conventional apparatus for recording / reproducing video. Here, 110 is a first video signal processing circuit, 111 is a video outer error correction coding circuit, 112 is a first audio signal processing circuit, 113 is a sound outer error correction coding circuit, and 114 is an inner error correction coding circuit. Circuit, 115 a recording circuit, 116 a recording head,
117 is a magnetic tape, 118 is a reproducing head, 119 is a reproducing circuit, 120 is an inner error correcting circuit, 121 is a video outer error correcting circuit, 122 is a second video signal processing circuit, 123 is an audio outer error correcting circuit, and 124 is Second
Is an audio signal processing circuit.

At the time of recording the video signal and the audio signal, the input video signal is input to the first video signal processing circuit 110, is subjected to processing such as digitization and compression, and is output to the video outer error correction coding circuit 111. It The video outer error correction coding circuit 111 performs outer error correction coding on the input video data in track units to generate outer parity, and outputs the outer parity to the inner error correction coding circuit 114 together with the video data. Further, the input voice signal is input to the first voice signal processing circuit 112, subjected to processing such as digitization and compression, and output to the voice outer error correction coding circuit 113. The audio outer error correction coding circuit 113 performs outer error correction coding on the input sound data in track units, generates outer parity, and outputs the outer parity to the inner error correction coding circuit 114 together with the sound data.

In the inner error correction coding circuit 114,
The input data and the outer parity are subjected to inner error correction coding, the inner parity is added, and the recording circuit 1
Output to 15. In the recording circuit 115, a sync pattern and an address are added to the error correction coded data to form a sync block, which is modulated, output to the recording head 116, and recorded on the magnetic tape 117.

At the time of reproduction, the reproducing head 118 reads the magnetic tape 117 and outputs it to the reproducing circuit 119. The reproduction circuit 119 demodulates and the inner error corrector 12
Output to 0. The inner error correction coding circuit 120 performs inner correction using the inner parity, outputs the video data and its corresponding outer parity to the video outer error correction circuit 121, and outputs the audio data and its outer parity to the audio outer error correction circuit 123. Output. The video outer error correction circuit 121 performs outer correction on the input video data using the outer parity, and outputs the video data to the second video signal processing circuit 122. The second video signal processing circuit 122 decodes the data into a video signal and outputs it. The outer audio error correction circuit 123 performs outer correction on the input audio data by using the outer parity, and outputs the audio data to the second audio signal processing circuit 124. The second audio signal processing circuit 124 decodes the data into an audio signal and outputs it. As described above, the video signal is recorded and reproduced as digital data.

In the above method, the error correction code is constructed for each track as shown in FIG. Here, 130 is a video data area, 131 is a video inner parity area, 13
Reference numeral 2 is a video outer parity area, 133 is an audio data area, 134 is an audio inner parity area, and 135 is an audio outer parity area. The inner codeword is composed of sync block units, and the outer codeword is composed of the nth symbol of each sync block. The order of recording on the tracks is as shown by the arrows. Digital VT
Since data is recorded digitally in R, it is possible to record data from a computer or other digital data as it is. Further, a method is known in which the third error correction is performed between tracks to improve the correction capability.

[0009]

In the compressed image,
In comparison with the fact that even if an error occurs, it is possible to correct the error and the error is not propagated, computer data often cannot tolerate the error. Further, in recording a video signal compressed by a method in which error propagation widely occurs, it is necessary to have a low error rate. However, the above recording / reproducing apparatus has a high error rate for recording data in a computer or the like. Further, since the error correction is performed on a track-by-track basis, the ability to correct burst errors is low.

Further, in the third error correction method, the correction unit has conventionally become longer along with its correction capability. In the case of a recording / reproducing apparatus using a digital VTR, the capacity per track is large, and in order to increase the correction unit, it is unavoidable to increase the capacity of the memory of the correction circuit and the like, and the increase in the circuit scale is a problem. Has become.

[0011]

According to the present invention, in order to solve the above-mentioned problems, the data A of the input (m × k1) symbol is used.
Into m words k of k1 symbols, and the first error correction coding is performed on each word D (n1-k
1) A parity word E of a symbol is added to form a word H, and the data I, which is a collection of m pieces of the word H, is divided into f parts.
f data J, each data J is subjected to a second error correction coding to generate a parity V, the data J is divided into k2 words Y, and each word Y is divided into k words Y. Third error correction coding and predetermined recording signal processing to record in the first data recording area of the track,
The parity V is divided into (n2-k2) words Z, and the third error correction coding and the predetermined recording signal processing are performed on each of the words Z, and the second data recording area of the track. It is configured to be recorded in.

Further, according to the present invention, the data A of the input (m × k1) symbol is divided into m, and the word D of m k1 symbols is divided.
Then, the first error correction coding is performed, and the parity word E of (n1-k1) symbols is added to each of the words D to form a word H, and the data I in which the m pieces of the word H are collected is divided into f. To make f pieces of data J, the data J is divided into k2 words Y, and each word Y is subjected to the second error correction coding and predetermined recording signal processing to obtain a track data recording area. It is configured to be recorded in.

[0013]

According to the present invention, when recording / reproducing digital data, an error is corrected, data having a low error rate is obtained, and the correction unit is shortened to reduce the circuit scale of the recording / reproducing apparatus.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital data recording method of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a recording / reproducing apparatus to which the digital data recording method of the present invention can be applied. Here, 10 is a formatter, 11 is a first memory, 12 is a first error correction coding circuit, 13 is a second error correction coding circuit, 14 is a third error correction coding circuit, and 15 is a recording. Circuit, 16 is a recording head, 17 is an address control circuit, 1
8 is a magnetic tape, 19 is a reproducing head, 20 is a reproducing circuit,
Reference numeral 21 is a third error correction circuit, 22 is a second error correction circuit, 23 is a second memory, 24 is a first error correction circuit,
Reference numeral 25 is a deformatter, and 26 is an address control circuit.

At the time of recording data, the input data is converted into data A for every (m × k1) data by the formatter 10 and stored in the first memory 11. Then, the data A from the first memory 11 is sent to the first error correction coding circuit 12.
Enter. The first error correction coding circuit 12 performs the first error correction coding on the data A and outputs the data E to the first memory 11. After that, the first memory 11
The data A and the data E are divided into f to form data J, which are sequentially output to the second error correction circuit 13. In the second error correction circuit 13, the data J is subjected to the second error correction coding, and the parity is generated as the data V. Further, the second error correction circuit 13 outputs the data J and the data V to the third error correction coding circuit 14. The third error correction coding circuit 14 forms the input data J and data V into blocks, performs the third error correction coding, generates and adds a parity, and outputs the parity to the recording circuit 15. In the recording circuit 15, the ID and the sync pattern are added to the block and the parity to form a sync block for modulation, and the recording head 16
And is recorded on the magnetic tape 18. At this time, the address control circuit 17 stores the data input / output to / from the first memory 11 at a predetermined address or outputs it to the first address.
Of the memory 11 of FIG.

At the time of reproducing data, the data recorded on the magnetic tape 18 by the reproducing head 19 is reproduced by the reproducing circuit 20.
Output to. The reproduction circuit 10 demodulates while detecting the sync block and outputs it to the third error correction circuit 21.
The third error correction circuit 21 corrects block errors,
The data J and the data V are output to the second error correction circuit 22. The second error correction coding circuit 22 performs error correction on the input data J using the data V and outputs the data J to the second memory 23. Then, the data A and the data E are reconstructed from the f data J, and the data A is error-corrected by the first error correction circuit 24 using the data E. After that, the corrected data A in the second memory 23 is output to the deformatter 25 and is output as data. At this time, the address control circuit 26 controls the second memory 23 to store or output the data input / output to / from the second memory 23 at a predetermined address.

The data input at this time is recorded on the f track of the magnetic tape as follows. First, as shown in FIG. 2, the input bit stream is divided into (m × k1) symbol data A. Here, 31 is the input bit stream, and 32 is the data A. The bit stream 31 is sequentially set as data A for each (m × k1) symbol. A (0), a (1), ..., a (p0), ..., a (m × k1−
The formatter 10 forms the data A so as to be 1) and outputs it to the first memory 11.

Next, as shown in FIG. 3, the data A of (m × k1) symbols is divided into a group G having k1 m symbols. Here, 32 is data A and 34 is group G. Divide k1 groups into G (0), G (1), ...,
Let G (p1), ..., G (k1-1). The m symbols of group G (p1) are symbol g (p1,0), g (p1,1), ..., g (p
, P2), ..., G (p1, m-1), the division of the symbol of g (p1, p2) and a (p0) is p0 = p1 × m + p2. This can be realized by grouping the symbols a in order of m symbols each.

Next, as shown in FIG. 4, m words D are formed from k1 groups G. Here, 36 is the word D. m words D in order D (0), D (1), ...,
Let D (p3), ..., D (m-1). The word D is composed of k1 symbols, and the symbols of the word D (p3) are sequentially d (p3,
0), d (p3,1), ..., d (p3, p4), ..., d (p3, k1-1). The symbol d (p3, p4) is one of the symbols of the group G (p4), and the symbol d (p of the m word D is used.
A word D is constructed from the group G so that the symbols g (p1, p2) of the group G of (3, p4) and k1 groups G are mapped one-to-one. For example, this is the symbol d (p3, p4) and the symbol g (p
This can be achieved by configuring (1, p2) such that p1 = p4 and p2 = p3.

Next, as shown in FIG.
The first error correction coding is performed by the 1, k1, n1-k1 + 1) code. Here, 38 is the word E and 39 is the word H.
The parity generated by performing the first error correction coding on one word D by the (n1, k1, n1-k1 + 1) code is referred to as a word E. When the word E (p3) is generated by performing the first error correction coding on the word D (p3), the number of symbols of each word E is (n1−k1) and belongs to the word E (p3). n1-k1) symbols in order of e
(p3,0), e (p3,1), ..., e (p3, p5), ..., e (p3, n1-k
1-1). Then, the word D and the word E are connected to form the word H. The m words H are H (0), H (1), ...
H (p3), ..., H (m-1), and word H (p3) is word D
(p3) and the word E (p3) generated from the word D (p3). The symbol of the word H (p3) is h (p3,0), h (p3,
1), ..., h (p3, p6), ..., h (p3, n1-1),
The relation with the symbol d (p3, p4) is p6 = p4, and the symbol e (p3, p4
The relationship with 5) is p6 = p5 + k1.

Next, as shown in FIG. 6, m words H are converted into (m
Xn1) The data I having the symbols is formed, and the data I is further divided into f to form f data J. Where 41
Is data I and 42 is data J. Word I is m × n1
I (0), i
(1), ..., i (p7), ..., i (m × n1-1). The relationship between the symbol h (p3, p6) and the symbol i (p7) is p7 = m × p6 +
p3. In addition, f pieces of data J are sequentially J (0), J (1), ...
,, J (p8), ..., J (f-1), and the symbols of the data J (p8) are j (p8,0), j (p8,1), ..., j (p8, p9), ...,
j (p8, t1-1). Here, t1 is the number of symbols of the data J to be recorded on one track, and t1 = m × n1 / f. The relationship between the symbol i (p7) and the symbol j (p8, p9) is p7 = t1 × p8 + p9. The data J (p8) configured in this way is configured in sync blocks in the first data recording area of the (p8 + 1) th track of f tracks, and is sequentially recorded.

As described above, the address control circuit 17 configures the data A recorded in the first memory 11 as the word D and outputs the word D to the first error correction coding circuit 12 by the first memory. The address of 11 is controlled to output the data of the first memory 11 to the first error correction coding circuit 12. In addition, the first error correction coding circuit 12 performs the error correction coding to generate the parity as the data E.
Output to the memory 11. After that, the first memory 11
Data A and data E recorded in
The address control circuit 17 controls the address of the first memory 11 so as to output to the second error correction encoding circuit 13 to the second error correction encoding circuit 13.
The data of is output.

The data J (p8) thus generated is subjected to the second error correction coding as shown in FIG. Here, 51 is the word R, 52 is the word U, and 53 is the data V.
Is. When the number of information symbols of the sync block is Ns, the number of code words of the second error correction code is Ns. First,
The data J (p8) is divided into words R which are the information symbols of the second error correction coding. The data J (p8) is divided into Ns number of words R, and R (0), R (1), ..., R (q0) ,.
R (Ns-1). The symbols of the word R (q0) are sequentially r (q
0,0), r (q0,1), ..., r (q0, q1), ..., r (q0, t1 / Ns-
1), symbol j (p8, p9) and symbol r (q0, q1)
Let p9 = q1 × Ns + q0.

The code of the second error correction code is (n2, k2, n2-k2
+1) code and the generated parity is word U. k2
Is the number of information symbols of the second error correction code, and k2 = t1 /
Ns. The number of symbols of the generated word U is (n2-k
2) The word U generated from the word R (q0) is referred to as the word U (q0). The symbols of the word U (q0) are sequentially changed to u (q
0,0), u (q0,1), ・ ・ ・, u (q0, q2), ・ ・ ・, u (q0, n2-k2-
1) Furthermore, the data J (p8) recorded on one track
Data V (p8) is the parity generated from
The symbols of (p8) are v (p8,0), v (p8,1), ..., v (p
8, q3), ..., v (p8, t2-1). t2 is the number of symbols of the parity generated by the second error correction coding of one track, and t2 = (n2-k2) * Ns. At this time, the relation between the symbol u (q0, q2) and the symbol v (p8, q3) is q3 = q2 × Ns
Set to + q0. Parity data V by the second error correction code for the data J generated in this way is formed in a sync block as described later in the second data recording area of the same track as the corresponding data J, and is sequentially recorded. .

The data J (p8) is composed of sync blocks as shown in FIG. Here, 60 is a sync block, 61
Is a word Y generated from the data J (p8), 62 is a sync pattern, 63 is an address, and 64 is a parity word generated from the word Y. First, data J (p8)
Each Ns symbol is divided into k2 words Y. The parity word generated by performing the third error correction coding on this word Y is added after the word Y. Further, a sync pattern 62 and an address 63 are added to the head to form a sync block 60. After that, they are sequentially recorded in the first data recording area of the (p8 + 1) th track. The address 62 indicates the address of the sync block 60, and the sync pattern 62 is a specific bit pattern that is a mark when detecting the sync block 60.

The data V (p8) is also composed of sync blocks as shown in FIG. Here, 65 is a word Z generated from the data V (p8), and 66 is a parity word generated from the word Z. First, the data V (p8) is divided into Ns symbols in order to form (n2-k2) number of words Z. A parity word generated by performing the third error correction coding on this word Z is added after the word Z. Also, a sync pattern 62 and an address 63 are added to the head to form a sync block 60. After that, they are sequentially recorded in the second data recording area of the (p8 + 1) th track.

FIG. 10 shows a track pattern diagram. Here, 70 is a magnetic tape, 71 is a track, 72 is a tracking information area, 73 is a first data recording area, 74 is a second data recording area, 75 is an auxiliary information recording area, and 76 is.
Is a gap, and 77 is a sync block. Truck 7
Reference numeral 1 is an area formed by recording one scan of the head. The tracking information area 72 is an area for recording information for checking the position of the head on the tape during recording or reproduction. Further, the first data recording area 73 is an area for recording the data J, and the second data recording area 74
Is an area for recording the data V. Auxiliary information recording area 7
Reference numeral 5 is an area for recording information and the like for retrieval. The gap 76 is an area for absorbing a recording position error when rewriting a part of the track of the tape. FIG. 11 shows the structure of the data recorded on the f tracks thus structured. Here, 80 is the data A1
A recording area 81 is a data E1 recording area. first of f
The data recording area 73 is composed of a data A1 recording area 80 and a data E1 recording area. With the above configuration, it is possible to record the data A in the first half and the data E in the second half of the f first data recording areas.

As described above, by using the first correction code performed between the tracks outside the inner correction code and the outer correction code used in the digital VTR, a sufficient error rate can be obtained in a device for recording digital data. It is possible to secure the data, record the input data in that order in the track, and distinguish the input data and the generated parity on the track. Further, by performing error correction between tracks, it becomes possible to enhance the correction capability for burst errors. Further, by constructing a code word for error correction performed between tracks from a plurality of symbols in one track, a correction unit is shorter than in the conventional case, and thus a recording / reproducing apparatus having a small circuit scale can be configured.

Another method of forming the data A into another data J'will be described. The group G at this time is referred to as a group G ′. Data A symbols a (0), a (1), ..., a (p0),
..., a (m × k1-1), k1 groups G '(0),
G '(1), ..., G' (p1), ..., G '(p1, k1-1), and the symbols of the group G' (p1) are g '(p1,0), g '(p1,1),
..., g '(p1, p2), ..., g' (p1, m-1). At this time, the relationship between the symbol a (p0) and the symbol g '(p1, p2) is p1.
= (P0 mod t1) / Ns, p2 = | p0 / t1 | × Ns + (p0 mod Ns)
And

Next, m words D'are formed from the k1 groups G '. m word D'in order D '(0), D' (1),
..., D '(p3), ..., D' (m-1). Word D'is k
It consists of one symbol, and the symbols of the word D '(p3) are d' (p3,0), d '(p3,1), ..., d' (p3, p4), ..., d in order. '
(p3, k1-1). The symbol d '(p3, p4) is the group G' (p
It is one of the symbols 4), and is the symbol d ′ (p3, p4) of m word D ′ and the symbol g ′ of k1 group G ′.
The word D'is constructed from the group G'so that (p1, p2) maps one-to-one. This is for example the symbol d '(p3, p4)
And the symbol g ′ (p1, p2) is p1 = p4, p2 = p3.

Next, (n1, k1, n1-k1 +) is added to the m number of words D '.
1) The first error correction coding is performed by the code. (n1, k1, n1
The parity generated by performing the first error correction coding on one word D ′ by the −k1 + 1) code is a word E ′. If the word E '(p3) is generated by performing the first error correction coding on the word D' (p3), the number of symbols of each word E'is (n1-k1),
The (n1-k1) symbols belonging to the word E '(p3) are sequentially represented by e' (p
3,0), e '(p3,1), ..., e' (p3, p5), ..., e '(p3, n1-
k1-1). Then, the word D'and the word E'are connected to form a word H '. m words H'are H '(0), H'in order
(1), ..., H '(p3), ..., H' (m-1), and word H '
(p3) consists of word D '(p3) and word E' (p3) generated from word D '(p3). The symbols of the word H '(p3) are h' (p3,0), h '(p3,1), ..., h' (p3, p6), ..., h '
When (p3, n1-1), the relation with symbol d '(p3, p4) is p
6 = p4, and the relation with the symbol e '(p3, p5) is p6 = p5 + k1.

Next, m words H'are formed into data I'having (m × n1) symbols, and the data I'is divided into f parts to form f data J '. The word I ′ consists of (m × n1) symbols, and the symbol is i ′, and i ′ (0),
i '(1), ..., i' (p7), ..., i '(m × n1-1).
The relation between the symbol h '(p3, p6) and the symbol i' (p7) is p7 =
| P6 / Ns | × t1 + p6 mod Ns + p3 × Ns. In addition, f pieces of data J'are sequentially J '(0), J' (1), ..., J '(p8), ...
,, J '(f-1), and the symbols of the data J' (p8) are sequentially j '
(p8,0), j '(p8,1), ..., j' (p8, p9), ..., j '(p8, t
1-1). Here, t1 is the number of symbols of the data J ′ recorded on one track, and t1 = m × n1 / f. Symbol i '(p
The relationship between 7) and the symbol j '(p8, p9) is p7 = p8 x t1 + p9.

Then, the data J'is the same as the data J in the second
Error-correction coding is performed and recorded on the tape. FIG. 12 shows the structure of the data recorded on the f tracks thus structured. Here, 82 is a data A2 recording area, and 83 is a data E2 recording area. The f first data recording areas 73 are composed of the data A1 recording area 82 and the data E1.
It is composed of a recording area 83. In the configuration method described above, the data A in the first half of the f first data recording areas 73 is recorded.
However, the data E is recorded in the latter half, but in the method of configuring the data A into the group G ′, the data A is recorded in the first half of the first data recording area of one track and the data E is recorded in the latter half. This method is convenient because, for example, when recording constant data for each track, the amount of data and parity for each track is constant.

In this embodiment, the input bit stream 3
1 is divided into (m × k1) symbols for data A,
Signal processing such as data compression, encryption, and block processing is applied to arbitrary input, or meaningless data is added, and (m
× k1) By using symbol data, it is possible to record and reproduce arbitrary data.

Further, the relationship between the symbols g (p1, p2) and d (p3, p2) is p1 = p4, p2 = p3, but p2 = (p3 + p4) mod m, and the data is circulated within the group. By doing the second
It is possible to prevent the error correction code and the code word from partially matching and the error correction capability from being deteriorated. Further, this may be circulated in any small group within the group, and even in other methods, the present invention can be configured without contradiction as long as the symbols have a one-to-one correspondence between g and d.

Further, although n1 is a natural number in this embodiment,
By setting n1 to be t1 / Ns which is the number of sync blocks in one track of the first data recording area, the same number of code words can be obtained even if the track configuration is changed, which is more convenient. This is because, for example, when only the video signal recording area is the first data recording area and the second data recording area, and when both the video signal recording area and the audio signal recording area are the first data recording area and the second data recording area. The number of code words does not change even when the track structure changes and the recordable capacity changes, such as when the area is a data recording area, and the structure of the recording / reproducing circuit can be simplified.

Further, in the present embodiment, t1 = m × n1 / f is set. However, by setting t1 = m × n1 / f + t5 (t5 is a natural number), the data J is not limited to the word H but also to the part of t5. It is possible to record the data W of Use this area when recording data such as high-speed playback data that cannot reproduce all f-track data or data that does not require a low error rate due to triple error correction. Thus, the track area can be efficiently used. Also, in this case, the t5 symbol after the data E is used for the data W, but f pieces of data J are
It goes without saying that the area can be used as the above-mentioned data H by making the area larger than each word H and freely taking the address. FIG. 13 shows the data structure of the track at this time. Here, 85 is the data W which is not subjected to the first error correction coding. In this figure, the first half of the first data recording area of the track is the data A2 recording area 8
3 shows the data structure when the latter half of the first data recording area of the track is the data E2 recording area.
It goes without saying that the data W can be recorded by making t1 larger than m × n1 / f when the first half of the track is the data A1 recording area and the second half is the data E2 recording area. The recording order of the data W, the data A, and the data E may be the data W later or the data W first. Alternatively, the data W may be recorded first, and then the data A and the data E may be recorded, and then the data W ′ may be further recorded.

In the present embodiment, the data A is converted into the first half of the data I and the data E is converted into the second half of the data I to record the data A in the first half of the f track and the data E in the second half of the f track. However, it goes without saying that the data E can be recorded in the first half and the data A in the second half by changing the conversion method, or the data A and the data E can be freely mixed or divided and recorded.

In this embodiment, the first data recording area is first recorded on the track and then the second data recording area is recorded on the track, but the order may be reversed. Further, although one continuous first data recording area is arranged on the track, it goes without saying that the present invention can be realized even if there are other areas or gaps between them.

Further, in the present embodiment, one continuous second data recording area is arranged on the track, but it is needless to say that the present invention can be realized even if there are other areas or gaps between them. Absent. The present invention can be implemented even if there are other areas or gaps between the first data recording area and the second data recording area of the track.

If f is set to 10 or 12, the circuit can be shared with the digital VTR. Also,
If n1 is set to 135 or 138, it can be shared with the circuit for recording the video signal of the digital VTR.
A value of 7 can be shared with a circuit for recording a video signal and an audio signal of a digital VTR, and a value of 155 and values before and after it can be used to record a video signal and an audio signal of the digital VTR and a gap between them and before and after. It can be shared with the circuit.

It is needless to say that this embodiment is one embodiment of the present invention and can be realized by other configurations or software such as a computer.

Another embodiment of the digital data recording method of the present invention will be described below with reference to the drawings.

FIG. 14 is a block diagram of a recording / reproducing apparatus to which the second embodiment of the digital data recording method of the present invention can be applied. Here, 90 is a formatter, 91 is a first memory, 92 is a first error correction coding circuit, and 93 is a second memory.
Error correction coding circuit, 15 a recording circuit, 16 a recording head, 94 an address control circuit, 18 a magnetic tape, 1
9 is a reproducing head, 20 is a reproducing circuit, 95 is a second error correcting circuit, 96 is a memory, 97 is a first error correcting circuit, 9
Reference numeral 8 is a deformatter, and 99 is an address control circuit.

At the time of recording data, the input data is stored in the first memory 91 as the data A by the formatter 90 for every (m × k1) data. Then, the data A is input from the first memory 91 to the first error correction coding circuit 92. The first error correction coding circuit 92 performs the first error correction coding on the data A and outputs the data E to the first memory 91. After that, the data A and the data E in the first memory 91 are divided into f to form data J, which are sequentially output to the second error correction circuit 93. The second error correction circuit 93 configures the input data J into blocks, performs second error correction coding, generates and adds a parity, and outputs the parity to the recording circuit 15. In the recording circuit 15, an ID and a sync pattern are added to the block and the parity to form a sync block, modulation is performed, and the data is output to the recording head 16 to output the magnetic tape 1.
Record at 8. At this time, the address control circuit 94 changes the first
The first memory 91 is controlled to store or output the data input / output to / from the memory 91 at a predetermined address.

When reproducing data, the data recorded on the magnetic tape 18 by the reproducing head 19 is reproduced by the reproducing circuit 20.
Output to. The reproducing circuit 10 demodulates while detecting the sync block and outputs it to the second error correction circuit 95. The second error correction circuit 95 corrects the block error and outputs the data J to the second memory 96. Then, the data A and the data E are reconstructed from the f data J, and the data A is error-corrected by the first error correction circuit 97 using the data E. After that, the corrected data A in the second memory 96 is output to the deformatter 98 and is output as data. At this time, the address control circuit 99 changes the second
The second memory 96 is controlled so that the data input / output to / from the memory 96 is stored or output at a predetermined address.

At this time, the input data is recorded on the f track of the magnetic tape as follows. First, the input bit stream is divided into (m × k1) symbol data A as shown in FIG. Here, 31 is the input bit stream, and 32 is the data A. The bit stream 31 is sequentially set as data A for each (m × k1) symbol. The formatter 90 sets the symbols of one data A to be a (0), a (1), ..., A (p0), ..., A (m × k1-1) in the input order. The data A is formed and output to the first memory 91.

Next, as shown in FIG. 3, the data A of (m × k1) symbols is divided into a group G having k1 m symbols. Here, 32 is data A and 34 is group G.
Divide k1 groups into G (0), G (1), ..., G (p
1), ..., G (k1-1). The m symbols of group G (p1) are symbol g (p1,0), g (p1,1), ..., g (p1, p
2), ..., G (p1, m-1), the division between the symbol of g (p1, p2) and a (p0) is p0 = p1 × m + p2. This can be realized by grouping the symbols a in order of m symbols each.

Next, as shown in FIG. 4, m words D are formed from k1 groups G. Here, 36 is the word D. m words D in order D (0), D (1), ...,
Let D (p3), ..., D (m-1). The word D is composed of k1 symbols, and the symbols of the word D (p3) are d (p3,
0), d (p3,1), ..., d (p3, p4), ..., d (p3, k1-1). The symbol d (p3, p4) is one of the symbols of the group G (p4), and the symbol d (p of the m word D is used.
A word D is constructed from the group G so that the symbols g (p1, p2) of the group G of (3, p4) and k1 groups G are mapped one-to-one. For example, this is the symbol d (p3, p4) and the symbol g (p
This can be achieved by configuring (1, p2) such that p1 = p4 and p2 = p3.

Next, as shown in FIG.
The first error correction coding is performed by the 1, k1, n1-k1 + 1) code. Here, 38 is the word E and 39 is the word H.
(n1, k1, n1-k1 + 1) code makes one word D first
The parity generated by the error correction coding of is defined as word E. If the word E (p3) is generated by performing the first error correction coding on the word D (p3),
The number of symbols in each word E is (n1-k1),
The (n1-k1) symbols belonging to the word E (p3) are sequentially represented by e (p3,
0), e (p3,1), ..., e (p3, p5), ..., e (p3, n1-k1-1)
And And the word D and the word E are connected and the word H
And The m number of words H are H (0), H (1), ..., H (p
3), ..., H (m-1), and word H (p3) is word D (p3)
And a word E (p3) generated from the word D (p3). The symbol of the word H (p3) is h (p3,0), h (p3,1),
.., h (p3, p6), ..., h (p3, n1-1), the relationship with the symbol d (p3, p4) is p6 = p4, with the symbol e (p3, p5) Let the relationship be p6 = p5 + k1.

Next, as shown in FIG. 6, m words H are converted into (m
Xn1) The data I having the symbols is formed, and the data I is further divided into f to form f data J. Where 41
Is data I and 42 is data J. Word I is m × n1
I (0), i
(1), ..., i (p7), ..., i (m × n1-1). The relationship between the symbol h (p3, p6) and the symbol i (p7) is p7 = m × p6 + p3
And In addition, f pieces of data J are sequentially set to J (0), J (1), ...
,, J (p8), ..., J (f-1), and the symbols of the data J (p8) are j (p8,0), j (p8,1), ..., j (p8, p9), ...,
j (p8, t1-1). Here, t1 is the number of symbols of the data J recorded in one track, and t1 = m × n1 / f. The relationship between the symbol i (p7) and the symbol j (p8, p9) is p7 = t1 × p8 + p9
And The data J (p8) configured in this way is recorded in the data recording area of the (p8 + 1) th track of f tracks.
As will be described later, the sync blocks are configured and recorded sequentially.

As described above, the address control circuit 94 configures the data A recorded in the first memory 91 as the word D and outputs it to the first error correction coding circuit 92 by the first address control circuit 94. It controls the address of the memory 91 and outputs the data of the first memory 91 to the first error correction coding circuit 92.

Further, the first error correction coding circuit 92 is
The parity generated by performing the error correction coding is output as the data E to the first memory 91. After that, the address control circuit 17 stores the data A and the data E recorded in the first memory 91 into the second error correction circuit 93 as the f number of data J and outputs them to the second error correction circuit 93. It controls the address and outputs the data in the first memory 91 to the second error correction coding circuit 93.

The data J (p8) is composed of sync blocks as shown in FIG. Here, 60 is a sync block, 61
Is a word Y generated from the data J (p8), 62 is a sync pattern, 63 is an address, and 64 is a parity generated from the word Y. First, the data J (p8) is divided into Ns symbols in order to form k2 words Y. A parity word generated by performing the second error correction coding on this word Y is added after the word Y. Also, a sync pattern 62 and an address 63 are added to the head to form a sync block 60. After that, the data is sequentially recorded in the data recording area of the (p8 + 1) th track. The address 62 indicates the address of the sync block 60, and the sync pattern 62 is a specific bit pattern that is a mark when detecting the sync block 60.

FIG. 15 shows a track pattern diagram. Here, 70 is a magnetic tape, 71 is a track, 72 is a tracking information area, 86 is a data recording area, 75 is an auxiliary information recording area, 76 is a gap, and 77 is a sync block. The track 71 is an area formed by recording of one scan of the head. The tracking information area 72 is an area for recording information for checking the position of the head on the tape during recording or reproduction. In addition, the data recording area 8
Reference numeral 6 is an area for recording the data J. The auxiliary information recording area 75 is an area for recording information for searching and the like. The gap 76 is an area for absorbing a recording position error when rewriting a part of the track of the tape. FIG. 16 shows the structure of the data recorded on the f tracks thus structured. Here, 80 is the data A1
A recording area 81 is a data E1 recording area. The f data recording areas 86 are composed of a data A1 recording area 80 and a data E1 recording area. With the above-described configuration, the data A is stored in the first half of the f data recording areas 86.
It becomes possible to record the data E in the latter half.

As described above, the first correction performed between tracks is performed outside the inner correction code used in the digital VTR.
By using the correction code of, it is possible to secure a sufficient error rate in the device that records digital data,
And input data is recorded on the track in that order,
In addition, it is possible to distinguish the input data and the generated parity on the track. Further, by constructing a code word for error correction performed between tracks from a plurality of symbols on one track, it is possible to configure a recording / reproducing apparatus having a shorter correction unit and a smaller circuit scale than in the past.

Another method of forming the data A into another data J'will be described. The group G at this time is referred to as a group G ′. Data A symbols a (0), a (1), ..., a (p0),
..., a (m × k1-1), k1 groups G '(0),
G '(1), ..., G' (p1), ..., G '(p1, k1-1), and the symbols of the group G' (p1) are g '(p1,0), g '(p1,1),
..., g '(p1, p2), ..., g' (p1, m-1). At this time, the relationship between the symbol a (p0) and the symbol g '(p1, p2) is p1.
= (P0 mod t1) / Ns, p2 = | p0 / t1 | × Ns + (p0 mod Ns)
And

Next, m words D'are constructed from k1 groups G '. m word D'in order D '(0), D' (1),
..., D '(p3), ..., D' (m-1). Word D'is k
It consists of one symbol, and the symbols of the word D '(p3) are d' (p3,0), d '(p3,1), ..., d' (p3, p4), ..., d in order. '
(p3, k1-1). The symbol d '(p3, p4) is the group G' (p
It is one of the symbols 4), and is the symbol d ′ (p3, p4) of m word D ′ and the symbol g ′ of k1 group G ′.
The word D'is constructed from the group G'so that (p1, p2) maps one-to-one. For example, this is the symbol d '(p3, p
4) and the symbol g ′ (p1, p2) can be realized by configuring p1 = p4, p2 = p3.

Next, (n1, k1, n1-k1 +) is added to the m number of words D '.
1) The first error correction coding is performed by the code. (n1, k1, n1
The parity generated by performing the first error correction coding on one word D ′ by the −k1 + 1) code is a word E ′. If the word E '(p3) is generated by performing the first error correction coding on the word D' (p3), the number of symbols of each word E'is (n1-k1),
The (n1-k1) symbols belonging to the word E '(p3) are sequentially represented by e' (p
3,0), e '(p3,1), ..., e' (p3, p5), ..., e '(p3, n1-
k1-1). Then, the word D'and the word E'are connected to form a word H '. m words H'are H '(0), H'in order
(1), ..., H '(p3), ..., H' (m-1), and word H '
(p3) consists of word D '(p3) and word E' (p3) generated from word D '(p3). The symbols of the word H '(p3) are h' (p3,0), h '(p3,1), ..., h' (p3, p6), ..., h '
When (p3, n1-1), the relation with symbol d '(p3, p4) is p
6 = p4, and the relation with the symbol e '(p3, p5) is p6 = p5 + k1.

Next, m words H'are formed into data I'having (m × n1) symbols, and the data I'is divided into f parts to form f data J '. Word I'is (m × n1)
I '(0),
i ′ (1), ..., i ′ (p7), ..., i ′ (m × n1-1).
The relation between the symbol h '(p3, p6) and the symbol i' (p7) is p7 =
| P6 / Ns | × t1 + p6 mod Ns + p3 × Ns. In addition, f pieces of data J'are sequentially J '(0), J' (1), ..., J '(p8), ...
,, J '(f-1), and the symbols of the data J' (p8) are sequentially j '
(p8,0), j '(p8,1), ..., j' (p8, p9), ..., j '(p8, t
1-1). Here, t1 is the number of symbols of the data J ′ recorded on one track, and t1 = m × n1 / f. The relationship between the symbol i '(p7) and the symbol j' (p8, p9) is p7 = p8 x t1 + p
Set to 9.

Then, the data J'is subjected to the second error correction coding similarly to the data J and recorded on the tape as a sync block. FIG. 17 shows the structure of the data recorded on the f tracks thus structured. here,
Reference numeral 82 is a data A2 recording area, and 83 is a data E2 recording area. The f data recording area 86 is the data A1 recording area 8
2 and a data E1 recording area 83. In the configuration method described above, the data A is recorded in the first half of the f data recording areas 86, and the data E is recorded in the latter half of the f data recording areas 86. Data A is recorded in the first half of 86 and data E is recorded in the latter half. This method is convenient because, for example, when recording constant data for each track, the amount of data and parity for each track is constant.

In the present embodiment, the input bit stream 31 is divided into (m × k1) symbols to form the data A, but any input is subjected to signal processing such as data compression, encryption, blocking, or the like. Add meaningless data,
By using (m × k1) symbol data, it is possible to record and reproduce arbitrary data.

In this embodiment, the symbol g (p1, p2)
And the relationship between d (p3, p2) is p1 ＝ p4, p2 ＝ p3, p2 ＝ (p3
+ P4) The data may be circulated within the group as mod m. It may also be visited by any small group within the group, or the symbol may be g
If there is a one-to-one correspondence between d and d, the present invention can be configured without contradiction.

Although n1 is a natural number in this embodiment,
By setting n1 to t1 / Ns, which is the number of sync blocks for one track in the first recording area, the same number of code words can be used even if the track configuration is changed. This is true even when the track configuration changes and the recordable capacity changes, for example, when only the video signal recording area is used as the data recording area or when both the video signal recording area and the audio signal recording area are used as the data recording area. The number of code words does not change, and the structure of the recording / reproducing circuit can be simplified.

Further, in the present embodiment, t1 = m × n1 / f is set. However, by setting t1 = m × n1 / f + t5 (t5 is a natural number), the data J is not limited to the word H, but to the portion of t5. It is possible to record the data W of This area is used, for example, when recording data such as high-speed playback data that cannot reproduce all f-track data or data that does not require a low error rate due to triple error correction. By doing so, it is possible to efficiently use the track area. Further, in this case, the t5 symbol after the data E is used for the data W, but the f data J is made a region larger than the m words H and its address is freely set, so that the above-mentioned data H can be obtained. Needless to say, it can be used as

In the present embodiment, the data A is converted into the first half of the data I, and the data E is converted into the second half, so that the data A is recorded in the first half of the f track and the data E is recorded in the second half. However, the data E can be recorded in the first half and the data A in the second half by changing the conversion method, or the data A and the data E can be freely mixed or divided and recorded.

By setting f to 10 or 12, the circuit can be shared with the digital VTR.
Also, by setting n1 to 149, it can be shared with the circuit for recording the video signal of the digital VTR.
And the values before and after that, the digital V
It can be shared with a circuit for recording TR video signals and audio signals and gaps between and before and after the signals.

It is needless to say that this embodiment is one embodiment of the present invention, and can be realized by another configuration or software such as a computer.

Further, although one continuous data recording area is arranged in the track in this embodiment, it is needless to say that the present invention can be realized even if there are other areas or gaps between them.

[0071]

As described above, according to the digital data recording method of the present invention, the input data is rearranged into a predetermined word and error correction coding is performed, thereby improving the error correction capability and reducing the code word to 1 By constructing a plurality of symbols from a book track, the correction unit can be reduced to reduce the circuit scale, and a method of recording on the tape in the order of input can be obtained. It has the following effect.

[Brief description of drawings]

FIG. 1 is a block diagram of an apparatus to which a first embodiment of a digital data recording method of the present invention can be applied.

FIG. 2 is a data conversion diagram in the digital data recording method according to the first embodiment of the present invention.

FIG. 3 is a data conversion diagram in the digital data recording method according to the first embodiment of the present invention.

FIG. 4 is a data conversion diagram in the digital data recording method according to the first embodiment of the present invention.

FIG. 5 is a data conversion diagram in the digital data recording method according to the first embodiment of the present invention.

FIG. 6 is a data conversion diagram in the digital data recording method according to the first embodiment of the present invention.

FIG. 7 is a data conversion diagram in the digital data recording method according to the first embodiment of the present invention.

FIG. 8 is a data conversion diagram in the digital data recording method according to the first embodiment of the present invention.

FIG. 9 is a data conversion diagram in the digital data recording method according to the first embodiment of the present invention.

FIG. 10 is a track pattern diagram in the digital data recording method according to the first embodiment of the present invention.

FIG. 11 is a data layout diagram of tracks in the digital data recording method according to the first embodiment of the present invention.

FIG. 12 is a data layout diagram of tracks in the digital data recording method according to the first embodiment of the present invention.

FIG. 13 is a data layout diagram of tracks in the digital data recording method according to the first embodiment of the present invention.

FIG. 14 is a block diagram of an apparatus to which a second embodiment of the digital data recording method of the present invention can be applied.

FIG. 15 is a track pattern diagram in the digital data recording method according to the second embodiment of the present invention.

FIG. 16 is a data layout diagram of tracks in the digital data recording method according to the second embodiment of the present invention.

FIG. 17 is a data layout diagram of tracks in the digital data recording method according to the second embodiment of the present invention.

FIG. 18 is a track pattern diagram formed by a conventional digital VTR.

FIG. 19 is a block diagram of a conventional digital VTR.

FIG. 20 is a data layout diagram of a track formed by a conventional digital VTR.

[Explanation of symbols]

 10 formatter 11 first memory 12 first error correction coding circuit 13 second error correction coding circuit 14 third error correction coding circuit 15 recording circuit 16 recording head 17 first address control circuit 18 magnetic tape Reference numeral 19 reproduction head 20 reproduction circuit 21 third error correction circuit 22 second error correction circuit 23 second memory 24 first error correction circuit 25 deformatter 26 second address control circuit

Claims (20)

[Claims] 1. The data A of (m × k1) symbols to be input is m
The data is divided into m k1 symbol words D, and the first error correction coding is performed on each of the words D (n1-k1).
Add the parity word E of the symbol into word H,
The data I, which is a combination of the m words H, is divided into f pieces of data J, and the second error correction coding is performed on each piece of the data J to generate the parity V. The word Y is divided into k2 words Y, each word Y is subjected to third error correction coding and predetermined recording signal processing, and recorded in the first data recording area of the track, and the parity V is (n2 -K2) It is divided into a number of words Z, and each of the words Z is subjected to the third error correction coding and the predetermined recording signal processing and recorded in the second data recording area of the track. Digital data recording method. 2. A first data recording area is divided into a data A1 recording area and a data E1 recording area for each track, data A is assigned to the data A1 recording area of the f track, and the data E1 recording area of the f track is assigned. 2. The digital data recording method according to claim 1, wherein m parity words E are assigned to each. 3. A first data recording area of the f track is a data A2 recording area of a first half (f × k1 / n1) track and a data E2 recording area of a second half (f × (n1-k1) / n1) track. Divide and assign the data A to the data A2 recording area,
2. The digital data recording method according to claim 1, wherein m parity words E are assigned to the data E2 recording area. 4. The digital data recording method according to claim 1, 2 or 3, wherein n1 = k2. 5. A k1 order in which data J and data V are recorded.
5. The word H is configured so that the x-th word H is composed of a set of x-th symbols in the block G when divided into the blocks G. The digital data recording method described in. 6. A k1 recording order for recording data J and data V
When divided into blocks G, the word H is formed such that the x-th word H consists of a set of data that is circulated in the block G by the number determined by each of the x-th to the blocks G of the block G. The digital data recording method according to any one of claims 1 to 4, wherein: 7. A k1 recording order of data J and data V
When divided into blocks G, the x-th word H is a set of data which is circulated in the word Y or the word Z by the number defined by the x-th word Y or the word Z of the block G, respectively. 5. The digital data recording method according to claim 1, wherein the word H is configured so that 8. The word H is formed so that when the data J and the data V are divided into k1 blocks G in a predetermined order, the xth word H is composed of a set of xth symbols of the block G. The digital data recording method according to any one of claims 1 to 4, wherein: 9. When the data J and the data V are divided into k1 blocks G in a predetermined order, the xth word H is the number determined by each of the xth to the block G of the block G. The digital data recording method according to any one of claims 1 to 4, wherein the word H is configured so as to be composed of a set of data that has circulated in the block G. 10. When the data J and the data V are divided into k1 blocks G in a predetermined order, the xth word H is defined by the xth to the word Y or the word Z of the block G, respectively. The digital data recording method according to any one of claims 1 to 4, wherein the word H is constituted so as to be composed of a set of data which is circulated in the word Y or the word Z by a number. 11. Data A of input (m × k1) symbols
Into m words k of k1 symbols, and the first error correction coding is performed on each word D (n1-k
1) A parity word E of a symbol is added to form a word H, and the data I, which is a collection of m pieces of the word H, is divided into f
Record the data J into f data J, divide the data J into k2 words Y, perform second error correction coding and predetermined recording signal processing on each word Y, and record in the data recording area of the track. A method for recording digital data, characterized by: 12. A data recording area is provided with data A for each track.
The recording medium is divided into one recording area and data E1 recording area, data A is allocated to the data A1 recording area of f track, and m parity words E are allocated to the data E1 recording area of f track. 11. The digital data recording method described in 11. 13. The first half of the data recording area of f tracks (f ×
Data A2 recording area of k1 / n1) track and (f × (n
1-k1) / n1) tracks are divided into data E2 recording areas,
12. The digital data recording method according to claim 11, wherein data A is allocated to the data A2 recording area and m parity words E are allocated to the data E2 recording area. 14. The method according to claim 1, wherein n1 = k2.
14. The digital data recording method according to claim 1 or claim 12 or claim 13. 15. A recording order of data J and data V
12. The word H is configured such that, when divided into k1 blocks G, the xth word H consists of a set of xth symbols of the block G.
15. The digital data recording method according to any one of claims 14 to 14. 16. The order of recording data J and data V
When divided into k1 blocks G, the word H of the x-th word H is made up of a set of data that has been circulated in the block G by the number determined by each of the x-th to the block G of the block G. The digital data recording method according to any one of claims 11 to 14, characterized in that: 17. The order of recording data J and data V
When the word H is divided into k1 blocks G, the word H of the x-th word is composed of a set of data which has been circulated in the word Y by the number determined by each of the x-th word of the block G and the word Y. 15. The digital data recording method according to claim 11, wherein the digital data recording method is configured. 18. When the data J and the data V are divided into k1 blocks G in a certain predetermined order, the word H is formed so that the xth word H is composed of a set of xth symbols of the block G. Claim 1 characterized by the above.
The digital data recording method according to any one of claims 1 to 14. 19. When the data J and the data V are divided into k1 blocks G in a predetermined order, the x-th word H is the number determined by each of the x-th to the block G of the block G. 15. The digital data recording method according to claim 11, wherein the word H is configured so as to be composed of a set of data that has circulated in the block G. 20. When the data J and the data V are divided into k1 blocks G in a predetermined order, the x-th word H is the number determined by each of the x-th to the word Y of the block G. 15. The digital data recording method according to claim 11, wherein the word H is configured so as to be composed of a set of data which is circulated within the word Y.