JP2533702B2 - Digital signal recording and transmission method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for recording / reproducing a digital signal, and more particularly to recording a digital signal suitable for use in a recording / reproducing apparatus for performing after-recording by overwriting. It relates to a transmission method. [0002] A conventional digital signal recording / reproducing apparatus is
As described in Japanese Patent Laid-Open No. 58-187039, a method is adopted in which input data is interleaved by delay in block units to record / reproduce. This is because a device such as a digital audio tape recorder performs high-density recording, and as a result burst errors increase, but these are converted into random errors, the effect of error detection and correction codes is increased, and error correction becomes impossible. Even in the case of, the objective is to perform approximate interpolation with the correct average value data of both the data so that the data before and after the data do not become an error at the same time. As described above, in the case of an audio signal or a video signal, even if error data is interpolated by an average value, a signal output after being D / A converted does not cause any trouble auditorily or visually. However, in a digital signal recording / reproducing apparatus such as a floppy disk used as a data recorder, even if there is a 1-bit error in data, it is a fatal defect. Of course, the method of converting data such as average value interpolation cannot be used.
Therefore, in a data recorder or the like, in order to absolutely reduce the number of errors, it is common to reduce the recording density to reduce the error rate. As an example of such a conventional technique, Japanese Patent Application Laid-Open No. 59-59
A description will be given of a case where digital data is recorded instead of an image by using an electronic camera (still camera or video floppy) system for recording still image information on a dedicated floppy disk as described in No. 84305. FIG. 2 shows a recording format for recording data in an electronic camera. In the figure, (a) shows a frame structure, one frame is composed of 128 blocks, 21 corresponds to a head contact start position, and a burst signal or the like is recorded as a margin. The ID section is an area to which a control signal other than the input signal is added. (B) shows the structure of one block, Sync is a synchronization signal,
BA is block address and subcode, CRC is B
It is a parity code for detecting an error in the A section. PCMda
The ta area divides the input data into 32 samples (1 sample is 8 bits for a total of 256 bits), and C ₁ and C ₂ are the first for performing error detection and correction of PCM data.
In the area for recording the second code, for example, a Reed-Solomon code or the like is generated and recorded. 22 is a magnetic sheet called a video floppy disk.
A method of recording by dividing into 4 sectors as shown in 3-26 is adopted. FIG. 3 is a memory map by conventional interleaving. In the figure, BLOCK corresponds to the one-block configuration shown in FIG. 2, S is an area for storing a predetermined redundant code such as a subcode, D is a storage area for input PCM data, and C ₁ and C ₂ are This is an area for recording a redundant parity code based on the first and second error detection and correction codes. In the conventional interleave, the same delay is given to each input data in time series order and the data is stored at the positions shown by the arrow B in FIG. Further, the second code C ₂ is generated from the data located at the arrow B and is stored in the position of the arrow Q due to the same delay. Further, the first code C ₁ is generated from the PCM data located at the arrow A and the code C _2, and is stored in the same block as the arrow A as indicated by the arrow P. Here, the sync signal of each block to the code C ₁ are read and recorded in the order of arrows A and P and in the order of block numbers. Therefore, the input time-series data and the code C ₂ are subjected to delayed interleaving for each block as indicated by arrows B and Q, and C ₁ is generated and recorded in one block. become. The interleaved recording method according to the above conventional technique has two problems. The first is that erroneous detection and correction of errors due to the unerased data after overwriting by overwriting occurs. Secondly, there is a mismatch with the memory capacity or deterioration of the correction capability due to generation of a correction code by interleaving with a constant delay within a predetermined memory area. Hereinafter, this problem will be described in detail. FIG. 4 is a diagram for explaining the first problem. In FIG. 4, a and b are blocks in each frame signal and their block numbers. Here, (a) shows a positional relationship in which a signal is recorded in a normal state, and the signal is recorded at a position T sandwiched by a TAC ₁ pulse generated according to the rotation of the magnetic sheet. Also, consider a case in which atter recording is performed by overwriting from the top of the recording as shown in (a), and the TAC ₂ pulse deviates from the originally recorded position T as shown in (b) of the figure. . At this time, the signal after after-recording is as shown in FIG. 7C, and the portion indicated by E corresponds to the end of the after-recording signal (b), so that it is assumed that the old block data a ₁₂₅ and a ₁₂₆ have become erroneous. . At this time, a ₁₂₇ and a ₁₂₈ are old data, but if the check is performed by the C ₁ code generated and recorded in the block completion type, no error occurs. Further, at the time of reproduction, since data detection is performed in a region of R, which has a margin before and after the originally recorded region T, like the pulse RP of FIG. Once done, the data is in the T region, b ₃ ,
b _4, ..., 128 of _{b 128, a 125, a 126} , a 127, a 128
The individual will be treated as newly recorded data. As a result, when a ₁₂₅ and a ₁₂₆ are erroneous, b _{3 to} b ₁₂₈ and a ₁₂₇ , which are not determined to be erroneous,
The error data a ₁₂₅ and a ₁₂₆ are corrected by each data a ₁₂₈ , resulting in erroneous correction. Therefore, the conventional device requires a circuit and a device for recording no signal for a certain period of time as an after-recording margin as shown by the hatched portion in FIG. 4D when recording is completed. Next, the second problem will be described. In the digital recording device, the error correction code C _{1 that} is completed in block units as described above is added, but in order to obtain a more effective correction capability, the second error correction is performed by the crossed oblique series. The code C ₂ is often added. In this case, by increasing the delay between adjacent data, the effect of improving the correction capability for bursty errors can be obtained. However, the larger the delay, the larger the required memory capacity. Here, when the C ₂ code is completed in a frame composed of a fixed number of blocks, the memory capacity is fixed, so
If a larger delay is given within this area, the maximum effect can be exhibited. However, when the distance d between adjacent data is increased with a constant delay as in the conventional case, for example, when one frame is composed of 128 blocks and the C ₂ code is generated from 36 samples, the maximum value of 128/36 or less is obtained. The integer is 3, and the distance d between adjacent data is 3.
It becomes a block. However, if d is kept constant at 3, then 3
6 × 3 = 108 blocks, which means that the blocks cannot be efficiently distributed over the maximum 128 blocks, and the correction capability for burst errors will be weakened accordingly. The object of the present invention is to solve the above first problem,
A digital signal that does not require a method, circuit, or device that adds an after-recording margin by detecting even if a block that has disappeared after over-recording by overwriting occurs and preventing erroneous detection or correction of data. It is to provide a method of recording and transmitting. In order to solve the above-mentioned first problem, the input digital data group is divided into a plurality of blocks, and the first and second data series are respectively different.
Error correcting code, the first error correcting code generates a plurality of redundant parity codes from a data group arranged in the same block, and at least one of the plurality of redundant parity codes is generated. Is achieved by means of recording by arranging in a block different from the above. According to the present invention, the redundant parity code of the first error correction code generated from the data group in any one block is recorded in a block different from the above block. As a result, even if one block remains after the after-recording by overwriting, an error can always be detected by the error detection by the first error correction code during reproduction. By recording the data block for generating the first redundant parity code and the block in which the redundant parity code is arranged at a maximum n blocks apart, the first error correction code is completed in n blocks. Therefore, even if the n-1 block length remains unerased, it can always be detected as an error, and erroneous detection and correction of the code can be suppressed. An embodiment of the present invention will be described below with reference to FIG. 1A is a memory map for error detection / correction code generation or interleaving, and FIG. 1B is an enlarged view of a part thereof, which is shown in correspondence with the block configuration of FIG. 2B. The time-series digital data input here are in the order shown by the arrow A'on the black circle W ₁ ~ on the memory map.
Assuming that the data will be sequentially stored at the position indicated by W ₃₂ ,
C ₂ code q ₀ to q ₃ in the order of arrow B 'of 32 data position shown in FIG open circle D ₁ to D ₃₂ is generated and stored in the position shown. Here, the storage locations of the data D _{1 to} D ₃₂ where the C ₂ code is generated, and the generated C ₂ code q ₀ to
The storage position of q ₃ has a non-linear form such that the delay block distances d between adjacent data are alternately d = 3 and d = 4. Further, the data for generating the C ₁ codes P _{0 to} P ₃ are 37 black circles W _{0 to} W ₃₂ and C ₂ codes Q _{0 to} Q _{3 in} the figure, which are generated in the order of the arrow A ′ and are shown in (b). Shown P
It is stored in the position of _{0 to} P ₃ , that is, in the delayed position such that the relationship of d ′ = 1 is established. The order of reading the data thus stored for recording on the magnetic sheet is the order of arrow A'in the figure. That is, as shown in the nth block in FIG. 1B, Sync, W ₀ , S,
The order is P, W _{1 to} W ₃₂ , Q _{0 to} Q ₃ , P ₀ , P ₁ ′, P ₂ ′, P ₃ ′. The result is that the input time series data is read out and recorded in the input order without interleaving. Also, for the C ₂ code, d = 3, d
= 4 non-linear interleaving is performed, and 4 symbols of C ₁
For the codes P _{0 to} P ₃ , scrambled so that the distance between adjacent blocks is d ′ = 1 so that the minimum delay block distance d for C ₂ code generation is d = 3 or less. It is recorded, and the C ₁ code is completed in 4 blocks. When recording by such a method, the above-mentioned problems can be solved without providing an after-recording margin. Next, the situation will be described with reference to FIG. 5, the same reference numerals as those in FIG. 4 represent the same contents having the same meaning. Here, after-recording is performed with the TAC ₂ pulse shifted, and when the remaining blocks a _{125 to} a ₁₂₆ are generated (however, a
₁₂₅ and a ₁₂₆ are error blocks.) When the deviation of the TAC ₂ pulse is detected and the C ₁ code is checked in the T ′ area, for example, the data W _{0 to} W ₃₂ in the b ₁₂₆ block,
In the C ₁ check by the data of Q _{0 to} Q ₃ and P ₄ , P ₅ , P ₆ , and P ₇ of FIG. 7D, if all the data are correct, it is judged as correct data. But TAC ₂
If a circuit and a device for detecting and correcting the pulse shift amount are not provided, the C ₁ check is performed assuming that the TAC ₂ is not shifted, and therefore the error detection by the C ₁ is performed using the data in the T ″ area. For example, the data W _{0 to} W ₃₂ and Q _{0 to} Q ₃ and P ₈ ′, P ₉ ′ in the block a ₁₂₇ ,
In the check by P ₁₀ ″ and P ₁₁ ″, W _{0 to} W ₃₂ and Q _{0 to} Q
₃ and P ₈ ', P ₉ ' are the old data that have disappeared and are
Since P ₁₀ ″ and P ₁₁ ′ are new data overwritten by after-recording, an error will naturally be detected in the C ₁ check. Similarly, it is judged that an a ₁₂₈ block is also an error. _{In the 2} areas, all the error data are judged, so that the error detection and the error correction cannot occur, and the E ₂ area which is an error block is continuously detected, and the deviation from the T area is detected. It is possible to make a check using the data of the T area that has been corrected correctly. [0015] Fig. 6 shows another embodiment according to the present invention. illustrates a. here, the C ₂ code q ₀ to q ₃ delay block distance d = the 8 and the interleaved data and D ₁₇ to D ₃₂ of D ₁ to D ₁₆ for C ₂ product d = a 3 to nonlinear generation order. Also, adjacent C ₂ code _{q 0, q 1, q 2} , delay block distance between q ₃ is d
= 8, the distance between the delay blocks of the four adjacent C ₁ codes p ₀ , p ₁ , p ₂ and p ₃ is d ′ = 2.
It can be said that In this embodiment, since the C ₁ code is completed in 7 blocks, it has the same effect as that of the device having the circuit configuration in which the after recording margin is 6 blocks. FIG. 7 shows another embodiment according to the present invention.
The same reference numerals as those in FIG. 1 represent the same contents having the same meaning. The time-series digital data input here are black circles W _{1 to} W ₃₂ on the memory map in the order shown by arrow A ′.
Assuming that the data are sequentially stored at the positions indicated by, the data at the positions indicated by black circles W _{0 to} W ₃₂ in the figure and the 37 assumed C ₂ code data Q _{0 to} Q ₃ are indicated by arrow A '. The C ₁ codes P _{0 to} P ₃ are generated in order, and are stored in the positions shown by black circles. The C ₂ code is a new C ₂ code generated from 37 in the order of the arrow B ′ at the position shown by the white circle in the figure, that is, D _{1 to} D ₁₆ , D _{17 to} D ₃₂ and C ₁ codes P _{0 to} P _3. Then, it is stored in the positions of white circles q _{0 to} q ₃ in the figure. Here, the data D _{1 to} D ₁₆ and D _{17 to} D ₃₂ for generating the C ₂ code.
The delay block distance between adjacent data is d = 3, and P _{0 to} P ₃ are d = 4 and generated q _{0 to} q _3.
Data is also set to d = 4. Further, in the data stored in this way, for the C ₂ codes Q _{0 to} Q ₃ and the C ₁ codes P _{0 to} P ₃ , q _{0 to} q ₃ and p of FIG.
_{As shown in 0 to} p ₃ , the delay block distance d ′ = 1 is scrambled and stored, and the order of reading for recording on the magnetic sheet is, for example, the nth block in FIG. Sync, S, P, W _{1 to} W ₃₂ , Q ₀ , Q
_{The order is 1} , Q ₂ , Q ₃ , P ₀ , P ₁ , P ₂ , P ₃ . As a result, the input PCM data is output in time series without interleaving, and the C ₁ and C ₂ codes are subjected to nonlinear interleaving. Next, an embodiment of the digital signal processing circuit of the digital signal recording / reproducing apparatus for implementing the present invention will be described with reference to FIGS. 8 and 9. FIG. 8 is a block diagram of a circuit constituting a recording system. 1 is an A / D converter, 2 is a subcode input interface, 3 is a block address and ID code generation circuit, 4 is a parity generation circuit, 5 is a memory, 6 is a memory address control circuit, 7 is C ₂
A code generation circuit, 8 is a C ₁ code generation circuit, 9 is a timing clock generation circuit, and 10 is a modulation circuit. Here, when an analog signal is input from the input terminal A and a sub-signal is input from the input terminal B, the analog signal is converted into a digital signal by the A / D converter 1 and the data forming one block is collected every block. Address and I
The D code is generated by the block address / ID code generation circuit 3. Further, the parity generation circuit 4 generates a parity such as a CRC code from the generated block address and ID code. The digital signal output from the A / D converter is stored in the memory 5 in time series,
The data in the memory is read out, the C ₂ code and the C ₁ code are generated by the C ₂ code generation circuit 7 and the C ₁ code generation circuit 8, and stored in the memory 5. At this time, the data reading order for C ₂ code and C ₁ code generation, or
The address when storing the generated code in the memory 5 is
For example, the address control circuit 6 in the order shown in the examples of FIGS. 1, 6 and 7 is controlled to read data from the memory 5, and a modulation circuit 10 adds a synchronization signal and digital modulation is performed. Apply and output terminal O
The data is recorded on a recording medium such as a magnetic floppy disk. The timing clock generation circuit 9
Is a circuit for generating a timing clock required in each circuit. FIG. 9 is a block diagram of a circuit constituting a reproduction system of the same apparatus. 11 is a data strobe circuit, 12 is a sync signal detection protection circuit, 13 is a demodulation circuit, 14 is a parity check circuit, 15 is a memory, 16 Is a memory address control circuit, 17 is a C ₁ code decoding circuit, 18 is a C ₂ code decoding circuit, 19 is a timing clock generation circuit, 20
Is a D / A converter. In the same figure, the signal reproduced from the signal recorded on the recording medium is inputted to the input terminal IN, and the data strobe circuit 11 discriminates "1" or "0" of each signal and discriminates the interval thereof. The recording modulation waveform of the rectangular wave of is shaped. The sync signal detection protection circuit 12 detects the sync signal pattern from the rectangular wave pattern, and the demodulation circuit 13 digitally demodulates the output of the data strobe circuit 11 by frame synchronization to obtain the original digital signal. Next, the parity check circuit 14 detects the code error of the block address and the ID code, and the demodulated digital data absorbs the jitter component and the like and stores it in the memory 15. Further, the data stored in the memory 15 is read out, the C ₁ code is decoded by the C ₁ decoding circuit 17, the error is detected, and the C ₂ code is decoded by the C ₂ decoding circuit 18 to detect the error. Memory 1 with correction
The error data stored in 5 is corrected and replaced, and the D / A converter 20 converts the error data into the original analog signal and outputs the analog signal from the output terminal OUT. The timing clock generation circuit generates and supplies the timing or clock required by each circuit. An operation of the address control circuit of the memory for realizing interleaving according to the present invention shown in FIG. 8 and an embodiment of the circuit will be described below with reference to FIGS. 10 and 11. FIG. 10 is a memory map corresponding to the method of FIG. 1 showing an embodiment of the present invention, and FIG. 11 is an address control circuit for generating this memory address. The numbers in the frame of FIG. 10 indicate the addresses for storing each data, and in this embodiment, the PCM data, ID, subcode, C ₁ and C ₂ once stored in the memory are recorded on the floppy disk. For this reason, this is an example in which an address for reading data from a memory is designed to be generated by counting up from 0 to 1 bit. The PCM data input here is controlled to be in units of one frame (32 bytes × 128 blocks), and the addresses to be stored are the addresses 3, 4, 5, ..., 34, 46, in FIG.
47, ..., 77, 89, ..., 120, ..., 5495 so that the PCM data area is sequentially filled.
ROM 67 for generating PCM data write address of 1,
At 68, the address is generated. Here ADR. ROM2
Outputs 32 address data of 3, 4, 5, ..., 34, and OFFSET. The ROM 2 outputs the data of 0, 43, 86, 129, ... As the offset amount each time the block changes, and adds it by the adder 75 to obtain P
The address shown in the CMdata area is generated. The counter 6 that specifies the ROM address
Reference numerals 4 and 62 are counters for dividing 32 and 128, which respectively count the number of data and the block number. After all the data for one frame is stored in the PCMdata area, the ID is generated and the address 0, 1,
2, 43, 44, 45, 86, ..., 5461, 546
Sequentially stored in 2, 5463. This operation is performed by the frequency division counter 63 of FIG. 11 from the ID, parity write address generation ROM 68 to 0, 1, 2, 43, 4, 4.
Are read out from the offset ROM 67 for generating ID and parity write address and added by the block number counter CNT ₁₂₈ . Next, the arrow B'in FIG. 1 is used to generate the C ₂ code.
In the order shown by, that is, addresses 3,134,30 in FIG.
32 memory addresses in the order of 7, ... By the C ₂ generation data read address and C ₂ data write address generation ROM 72 and the C ₂ generation data read address and C ₂ data write address generation offset ROM 71. An address is generated, the data is read out, four C ₂ codes Q ₀ , Q ₁ , Q ₂ and Q ₃ are generated, and then the predetermined addresses shown in FIG. 1 are generated and stored by the ROMs 71 and 72. . Finally, a C ₁ code is generated using the block address, PCM data and C ₂ code stored in the above procedure. That is, the 41 frequency division counter 66 and the block number counter 62 are used to generate the C ₁ generation data read address and the C ₁ data write address generation ROM 7
3, 74 are driven, and both ROMs are added by the adder 75 to obtain predetermined addresses 0, 3, 4, 5, ..., 37, 3
8 is generated, each data is read out, four C ₁ codes P ₀ ,
Generates an address 39, 40, 41, 42 by P _1, P _2, P ₃ further ROM73,74 and the adder 62 to generate is stored in this location. 1 including redundant code
This means that all the frame data has been filled up, and at this time, the 5504 frequency division counter 61 sets 0, 1, 2, ..., 5
The interleave of the present invention shown in FIG. 1 can be realized by reading the data from the memory using the count value up to 504 as it is as an address and recording the data on the floppy disk. In FIG. 11, the MPX outputs the specified address at the timing of performing each operation described above.
This is a 5-input 1-output multiplexer switched by the ct signal, and the Select signal and the clocks SCK _{0 to} SCK ₄ necessary for performing each operation are generated by the timing clock generation circuit 9 shown in FIG. The address generation circuit realized in FIG. 11 can also be realized by one large-capacity ROM, for example. FIG. 12 is a circuit diagram showing a counter 77, a large capacity ROM or PLA 79.
A circuit having a decoder function such as 5 is a memory. Here, the ROM 79 is designed to sequentially output the operation and address data described with reference to FIGS. 10 and 11, and the counter 77 first outputs an address (13 bits × 32 words × 128 Block =) for storing PCM data.
53.248 kbit), and then an address for storing the ID (13 bit × 3 word × 128 Block = 4.
992 kbit), each data reading for C ₂ generation and storage address (13 bit) of the generated C ₂ code
× (32 + 4) word × 128Block = 66.5
6kbit), C ₁ C ₁ code of the storage of address out and generates read the data for the generation (13-bit
× (37 + 4) word × 128Block = 68.2
Since 24 kbit) is output, the capacity may be 24.128 kbytes or less. The ROM 79 generates a predetermined address to generate PCM data, ID, C ₂ , C ₁
By storing the code in the memory and storing all the one-frame data including the redundant code, the address for reading the data to be recorded on the disk is output by the counter 78 and switched by the multiplexer 80 to switch the interleave of the present invention. And an address control circuit of a memory for realizing the above. According to the present invention, digital data input in time series is not interleaved but only error detection and correction codes are scrambled.
The redundant parity code of the first error correction code generated from the data group in the block is recorded in a block different from the above block. As a result, even if one block remains after the after-recording by overwriting,
The error detection by the first error correction code can always be detected as an error during reproduction. By recording the data block for generating the first redundant parity code and the block in which the redundant parity code is arranged at a maximum of n blocks apart from each other, the first error correction code becomes n blocks.
The block is completed, and even if the n-1 block length remains unerased, it can be detected as an error without fail, and there is an effect of suppressing erroneous detection and correction of the code. Therefore, there is an effect that a circuit and a device for adding an after-recording margin of n-1 block length for recording are not required and higher density recording is possible.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a memory map diagram of each data showing an embodiment of a recording method according to the present invention. FIG. 2 is a magnetic sheet format diagram showing a data recording method of an electronic camera. FIG. 3 is a memory map diagram showing interleaving of respective data, which is a conventional recording method. FIG. 4 is a conceptual diagram showing problems that occur in a conventional recording method. FIG. 5 is a conceptual diagram showing the effect of the present invention. FIG. 6 is a data memory map diagram showing another embodiment of the recording method according to the present invention. FIG. 7 is a memory memory map diagram showing another embodiment of the recording method according to the present invention. FIG. 8 is a block diagram of a recording system circuit of a recording / reproducing apparatus that realizes a recording method according to the present invention. FIG. 9 is a block diagram of a reproducing system circuit of a recording / reproducing apparatus that realizes a recording method according to the present invention. FIG. 10 is a data memory map diagram showing another embodiment of the recording method according to the present invention. FIG. 11 is a block diagram showing an embodiment of an address control circuit of a memory that realizes a recording method according to the present invention. FIG. 12 is a block diagram showing another embodiment of the address control circuit of the memory for realizing the recording method according to the present invention. [Description of Codes] W _{0 to} W ₃₂ ... C ₁ code generation PCM data, p _{0 to} p ₃ ... C ₁ redundant code, A '... C ₁ code generation order, D _{1 to} D ₃₂ ... C ₂ code generation PCM data, q ₀ to q ₃ ... C ₂ redundancy code, B '... C ₂ code generation sequence, d ... interblock delay distance by interleaving, 1 ... a / D converter, 2 ... input interface circuit of the subcode, 3 ... block address and ID code generating circuit, 4 ... parity generating circuit, 5 ... memory, the address control circuit 6 ... memory, 7 ... C ₂ code generation circuit, 8 ... C ₁ code generation circuit, 9 ... timing clock generation circuit, 10 ... Modulation circuit, 11 ... Data strobe circuit, 12 ... Synchronous signal detection protection circuit, 13 ... Demodulation circuit, 14 ... Parity check circuit, 15 ... Memory, 16 ... Memory address control times 17 ... C ₁ code decoding circuit, 18 ... C ₂ code decoding circuit, 19 ... Timing clock generation circuit, 20 ... D / A converter.

Claims (1)

(57) [Claims] 1. Configure block with multiple several digital data and redundant code, constitute one frame the block in a plurality units
The digital data composed of the digital data
By the digital data group and the redundant code added to it,
The digital signal that constitutes the error detection and correction code.
In the digital signal recording method of transmitting recording transmitted digital data group is recorded in the same block, less the
Also, at least one is assigned to a block different from the same block.
A plurality of first redundant codes placed in one block
Performs error detection and correction of recorded digital data groups.
The first error detection and correction code for
It is recorded in different blocks crossing the lock
Digital data group and second redundant code added to it
And the data recorded in the different blocks.
Second error detection for error correction of digital data group
A digital signal recording and transmitting method characterized by recording and transmitting a digital signal constituting an output correction code .