JPH07175633A - Digital data arithmetic unit - Google Patents

Abstract

PURPOSE:To reduce circuit scale and to improve arithmetic processing speed in a digital data arithmetic unit. CONSTITUTION:This digital data arithmetic unit is provided with an M bit adder 13 for dividing one piece of digital input data 2 into high-order N-M bit data 11 and low-order M bit data 12 and individually adding one or plural pieces of additive data B36 to the low-order bits 12 when the input data 2 are N-bit 1, the additive data B 36 are M-bit 15 and the condition of N>M is established. Then, an N-M bit data selector 16 is provided to select two inputs corresponding to a Carry 14 signal, the high-order bit data 11 and the output of an adder 17 for adding '1' to the high-order bit data 11 are connected to the selector 16, and output data 6 are provided by the outputs from the selector 16 and the adder 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data arithmetic unit of electronic measuring instrument technology, in which several pieces of data having a smaller number of bits are individually added to multi-bit digital data, and correspondingly, The present invention relates to an arithmetic unit that can obtain each output.

[0002]

2. Description of the Related Art In a conventional digital data arithmetic unit, a block diagram of a system of an arithmetic unit for obtaining each output by individually adding several data having a smaller number of bits to multi-bit digital data Is shown in FIGS. 6 and 7.

First, in FIG. 6, N bit 1 digital input data A2 and M bit (M <N) 15 data B1.
, B2 ・ 4 ・ ・ ・ ・ BK ・ 5 are individually added by the N-bit adder 35 to obtain A + B1 ・ 7, A + B2 ・ 8, ... A + B
This is a method of obtaining the output data 6 of K · 9. In this system, the adder needs N bits 1 even if the number of bits of the M bits 15 of the addition data B36 is smaller than the number of N bits 1 of the input data A2 to be added. Further, as many adders as the number of pieces of addition data are required. Therefore, there is a drawback that the circuit scale to be configured becomes large.

Next, FIG. 7 shows a system in which the N-bit adder 35 is shared by all output data 6. Even in this method, the input data A2 is N bit 1 and the addition data B36, B1, B2, B3 of M bits 15 (M <N) are added by the N bit adder 35, but the N bit adder 35 is shared. However, they are sequentially processed. Although the increase in the circuit scale can be suppressed by performing the sequential processing, even if the addition data B36 is M bits 15 (M <N), the operation is repeated with the N bit adder 35 being N bits 1 as it is. . The calculation processing time increases by the number of pieces of added data. Therefore, this method has a drawback that the processing speed becomes slow.

[0005]

When the input data A is N bits and the addition data is M bits (M <N), the conventional digital data arithmetic unit uses an N bits adder. Since the number of pieces of data to be added must be set, the circuit scale becomes large, and even if the N-bit adder is shared and time-sequential sequential processing is used, the increase in circuit scale can be suppressed. However, there is a problem that the calculation processing time increases by the number of added data times.

Therefore, in the present invention, even if the input data and the addition data have different numbers of bits, the input data
Even when the relationship between the N bits of A and the M bits of addition data is significantly different from M << N, the purpose was to realize a method that can reduce the circuit scale and improve the processing speed.

[0007]

To achieve the above object, in the digital data arithmetic unit of the present invention, N-bit input data A is added to M-bit addition data B1, B2,
... When BK is added individually, the configuration is as described below. (See Figure 1) That is, input data A
Is N bits and the addition data B is M bits, the input data A is divided into upper N−M bits and lower M bits. For the M-bit data, which is the lower bit, the addition data B1, B2, ...
And carry out output of the carry bit (= Carry) and the M bit, which are one-digit carry bits, respectively.
Then, the Carry signal is used as a selection signal of an individually prepared N-M bit data selector.

Further, the upper N-M bit data of the input data A becomes one of the N-M bit data selectors after being output from an adder provided for adding +1 to the data. Will be input. In addition, it is directly input to one of the N-M bit data selectors.
When Carry occurs in the addition by the adder of the lower M bits, the upper N-M bit data and the lower M bit data for which +1 addition has been performed are selected, and processing of carrying one digit is performed. Therefore, finally, by using CLK, the upper NM bit data and the lower M bit data are collected for each addition data by the register, and the N bit output data A + B1, A + B2, ... A + BK It was realized by adopting the following configuration.

[0009]

In the prior art, even if the number of bits of the added data is significantly different from that of the input data, the arithmetic operation is performed as it is by the adder having a capacity equal to or more than the number of bits of the input data. Is N bits, the addition data is M bits, and M <N or M << N, especially if the lower N bits are divided into upper N−M bits and lower M bits.
M-bit data is processed by a small-scale circuit with only M-bits, the Carry output signal is obtained, and a +1 adder is provided for the upper N-M bits to minimize the required amount. It became possible to operate with only bits.

[0010]

【Example】

(Embodiment) FIG. 1 shows a block diagram of a digital data calculator according to an embodiment of the present invention. (1) Input data A2 of N bit 1 and lower M bit data
12 B1, 3, B2, 4, ... BK, 5 are individually added, and output data 6A + B1, 7, A + B2, 8, A + B
It is a digital data calculator for obtaining K · 9. (2) Input data 2 consists of upper N-M bit data 11 and lower M
It is divided into bit data 12. Using the M-bit adder 13 for the lower bit data, B1, 3, B2, 4, ...
..BK.5 is added, and Carry14 (one-digit carry bit) and M-bit output are obtained. (3) Each Carry 14 signal serves as a selection signal for the N-M bit data selector 16 prepared separately. Also, input data A
The upper 2 N-M bit data 11 is the output of the +1 adder 18 that adds +1 to the data, and is one input of the N-M bit data selector 16. Also, as it is, N
Also serves as the other input of the M-bit data selector 16. (4) When Carry 14 occurs in the addition of the lower M-bit data 12, the higher N-M bit data 11 in which +1 is added
Is selected, and the carry processing is performed. (5) Then, the upper N−M bit data and the lower M bit data are put together for each output, and the output data 6 of N bit 1 is A + B1 · 7, A + B2 · 8, ... A + BK ·
It becomes 9.

(Second Embodiment) FIG. 2 is a block diagram of the arithmetic unit according to another embodiment of the present invention. (1) A circuit for obtaining output data 6 obtained by adding +1, +2, +3 to the input data A2. (2) In FIG. 2, the 2-bit +1, +2, +3 adder 22 is a part for performing +1, +2, +3 addition of the lower 2 bits. (3) Upper N-2 bit 18 data and N-2 data adder 19
Thus, both of the data obtained by the +1 addition are input to the N-2 bit selector 20. The selector 20 selects the upper N-2 bit data which has been added by +1 with respect to the output portion where the carry is generated as a result of the addition processing of the lower 2 bits. As a result, the output data 6 is A + 1 · 23, A + 2
・ 24 and A + 3 ・ 25.

(Embodiment 3) FIG. 3 is also a block diagram of the arithmetic unit according to another embodiment of the present invention. (1) The input data A · 2 has N bits and is divided into the upper NM bits 11 and the lower M bits 12 as in the first embodiment. (2) Addition data B36 that is B1, 3, B2, 4, ... B
K · 5 is M bit 15 and M bit adder 13
Entered in. (3) Hereinafter, as in the first embodiment, when Carry 14 occurs due to the addition of the lower M bit data 12, the upper N-M bit data 11 to which +1 is added is selected and the carry process is performed. Done. (4) The feature of this embodiment is that each output data 6 can be obtained by sharing the M-bit adder 13 and the NM bit data selector 16 and sequentially performing the arithmetic processing.

(Embodiment 4) FIG. 4 shows a block diagram of a digital data calculator according to another embodiment of the present invention. In this embodiment, not only addition but also subtraction is possible. (1) Similar to the first to third embodiments, in addition to the addition unit 17 for adding +1 to the upper N−M bits 11, a subtraction unit, that is,
A −1 addition unit 31 is provided. (2) Also, the M-bit adder 13 provided in the same manner as in the above embodiment
In addition, a 4: 1 multiplexer 27 is provided. (3) The M-bit addition data (B) 28 includes the sign bit 29 for +1 bit, which is the S bit of the multiplexer 27.
Input to 1. (4) The signal when Carry14 occurs is the M-bit adder 13
Is input to S0 of the multiplexer 27. (5) As shown in the combination table 30, there are four types (A, B, C, D) depending on the presence or absence of addition carry and whether the subtraction result is positive or negative.
A combination of (6) Then, by selecting the N-M bit data by the 4: 1 multiplexer 27, the added data of the lower M bits
(B) A negative value can be used for 28. That is, the input data (A) 10 can be subtracted.

+1 adder 17 which is one of the features of the present invention
The (one for adding only) and the -1 adder 31 (for subtracting only one) are for performing the carry-up processing of the lower bit adder.
Besides, it can be realized by the counter 33 and the memory 34. (See Figure 5 for details)

[0015]

Since the present invention is constructed as described above, it has the following effects. (1) When the input data is N bits and the addition data is M bits, it can be realized by the +1 addition part of the upper N−M bit data and K adders of the lower M bits, so the circuit scale can be reduced, and The processing speed was improved. (2) In particular, in the method shown in the second embodiment, only one N-2 bit adder and several gates are required, and although an N-2 bit selector is required, the circuit scale of the adder is significantly reduced. It was possible to reduce the size of the arithmetic unit as a whole. (3) Further, in the system shown in the fourth embodiment, the circuit scale is reduced and the processing speed is reduced by providing a subtraction circuit of -1 for the upper N-M bit data and further using a 4: 1 multiplexer or the like. It became possible to subtract while improving.

[Brief description of drawings]

FIG. 1 is a block diagram of a digital data calculator according to a first embodiment of the present invention.

FIG. 2 shows a block diagram of a digital data calculator according to a second embodiment of the present invention.

FIG. 3 shows a block diagram of a digital data calculator according to a third embodiment of the present invention.

FIG. 4 shows a block diagram of a digital data calculator according to a fourth embodiment of the present invention.

FIG. 5 is a +1 addition unit and − which are one of the features of the present invention.
The conceptual diagram for demonstrating that the system of a 1 addition part can be implement | achieved by a counter and memory other than an adder is shown.

FIG. 6 is a block diagram of a conventional digital data arithmetic unit having an N-bit adder and provided for each output data.

FIG. 7 shows a block diagram of a digital data arithmetic unit according to a conventional technique, in which all output data share an N-bit adder.

[Explanation of symbols]

 1 N bit 2 Input data A 3 B1 4 B2 5 BK 6 Output data 7 A + B1 8 A + B2 9 A + BK 10 Input data (A) 11 Upper N−M bit data 12 Lower M bit data 13 M bit adder 14 Carry 15 M bit 16 N−M bit data selector 17 +1 adder 18 Upper N−2 bit 19 N−2 bit adder 20 N−2 bit selector 21 2 bit adder 22 Lower 2nd bit data 23 A + 1 24 A + 2 25 A + 3 27 4: 1 Multiplexer 28 Addition data (B) 29 Sign bit 30 Combination table 31 -1 Adder 32 Adder 33 Counter 34 Memory 35 N-bit adder 36 Addition data B

Claims (2)

[Claims] 1. A digital data calculator in electronic measurement technology, wherein digital input data A (2) is N bits (1), addition data B (36) is M bits (15), and N> M. In case, N bit (1) input data A
(2) is divided into upper NM bit data (11) and lower M bit data (12), and lower M bit data (12)
M-bit (15) data B1 that is addition data B (36)
(3), B2 (4), ... Add BK (5) individually
An M-bit adder (13) is provided, and the M-bit adder (1
Select the input by the carry (14) signal from 3),
A means for providing an NM bit data selector (16) capable of outputting and for adding +1 to the higher NM bit data (11) at one input of the NM bit data selector (16). A +1 adder (17) is provided and its output is
Connected to the bit data selector (16), the output of the upper NM bit data (11) from the NM bit data selector (16) and the M bit adder (1) of the lower M bit data (12)
The output from 3) is taken as A + B1 as upper NM bit data (11) and lower M bit data (12), respectively.
(7), A + B2 (8), ... A + BK (9) are output as data (6). 2. The structure according to claim 1, further comprising:
The other input of the N-M bit data selector (16) is provided with a -1 addition unit (31) which is a means for adding -1 to the upper N-M bit data (11), subtracts the result, and outputs the result. The relevant N
-A digital data calculator that is connected to an M-bit data selector (16).