KR102182299B1 - Device and Method for Performing Shift Operation - Google Patents

Abstract

Disclosed are a shift operation device capable of simultaneously shifting a plurality of data having various lengths in parallel by using one shifter to reduce a hardware area and power consumption required for shifting the plurality of data, and an operation method thereof. According to one aspect of the present invention, the shift operation device capable of performing a shift operation on at least two pieces of input data each including a plurality of bits comprises: a mixer part that alternately arranges the bits of the at least two pieces of input data to output mixed data; an offset generation part that generates a shift offset value obtained by multiplying the shift amount of the at least two pieces of input data by the number of the at least two pieces of input data; a shift part that performs a shift operation on the mixed data by using the offset value to generate shifted data; and a splitter part that separates bits of the shifted data to generate at least two pieces of output data corresponding to the at least two pieces of input data.

Description

Device and Method for Performing Shift Operation TECHNICAL FIELD

The present embodiment relates to a shift module for shifting a plurality of data including a plurality of bits in parallel using one shifter, and a method of operation thereof.

The content described in this section merely provides background information on the present invention and does not constitute prior art.

In general, the processor may simultaneously process a plurality of data having various lengths in order to increase the data throughput per unit time. For example, a 32-bit processor can process one 32-bit data or four 8-bit data simultaneously.

Such a processor may include a shifter inside the processor to shift the data. The shifter inside the processor shifts data, but the maximum length of data that can be shifted is set. Also, unlike a processor, a shifter generally cannot simultaneously process a plurality of data having a length shorter than the maximum length that can be shifted.

In order to solve this problem, a conventional processor includes several shifters having different maximum lengths of shiftable data, so that a plurality of data having various lengths can be processed in parallel.

1 is a diagram illustrating a structure of a processor including a conventional shifter capable of shifting a plurality of data.

Referring to FIG. 1, a memory 100 and a processor 110 are illustrated, and data to be shifted is stored in the memory 100. The processor 110 includes a controller 112, a register file 114, an ALU 116, and an arithmetic logic unit, and a shifter 118.

The register file 114 of the processor 110 receives data from the memory 100 and stores it in a register. Data stored in the register file 114 may have various lengths. For example, one 32-bit data, two 16-bit data, or four 8-bit data may be stored in the register file 114.

The controller 112 may control an operation of moving data stored in the register file 114 to the ALU 116 or the shifter 118 according to a specific program command. The ALU 116 or the shifter 118 may perform a specific operation on the data received from the register file 114 and may store the operation result data in the register file 114. In this case, when the number of data is plural, the processor 110 may perform a specific operation on each data using a plurality of ALUs 116 or a plurality of shifters 118 and then store them in the register file 114. .

As described above, since the conventional processor includes a plurality of shifters, there is a problem in that the hardware area of the conventional processor is required to increase as the plurality of shifters are included. Since the conventional processor generally has a small number of data to be computed in parallel, the problem of increasing the hardware area and power consumption of the conventional processor, even if several shifters are included, has not been highlighted. However, processors used for neural networks, artificial intelligence, and deep learning increase exponentially in the number of data to be processed simultaneously. If shifters are included, there is a problem in that the hardware area and power consumption of the processor also increase exponentially.

In addition, when data is shifted using a plurality of shifters, a path through which data is transmitted between the plurality of shifters is lengthened, so that a logical depth representing the operation speed of the shifters increases. For this reason, the operation speed of the shifter becomes slow.

Accordingly, there is a need to implement a shifter capable of simultaneously shifting a plurality of data having various lengths in parallel with only one shifter.

Embodiments of the present invention provide a shift calculating device capable of simultaneously shifting a plurality of data having various lengths in parallel and in parallel using one shifter, and an operating method thereof, thereby providing a hardware area required to shift a plurality of data. And to reduce power consumption.

Other embodiments of the present invention aim to reduce a logical depth inside a shifter by shifting a plurality of data in parallel using one shifter.

According to an aspect of the present invention, in a shift operation apparatus capable of performing a shift operation on at least two input data each including a plurality of bits, the bits of the at least two input data are alternately arranged and mixed. A mixer for outputting data; An offset generator for generating a shift offset value obtained by multiplying the shift amount of the at least two input data by the number of the at least two input data; A shift unit for generating shifted data by performing a shift operation on the mixed data using the offset value; And a splitter unit that separates each bit of the shifted data and generates at least two output data corresponding to the at least two input data.

According to another aspect of the present embodiment, in a method of operating a shift operation device capable of performing a shift operation on at least two input data each including a plurality of bits, each bit of the at least two input data is alternately arranged. Generating mixed data; Generating a shift offset value obtained by multiplying the shift amount of the at least two input data by the number of the at least two input data; Generating shifted data by performing a shift operation on the mixed data using the offset value; And generating at least two output data corresponding to the at least two input data by separating each bit of the shifted data.

As described above, according to the present embodiment, by simultaneously shifting a plurality of data having various lengths in parallel using one shifter, the hardware area and power consumption required to shift the plurality of data in parallel are minimized. can do.

In addition, according to the present embodiment, by shifting a plurality of data in parallel using one shifter, there is an effect of reducing a logical depth inside the shifter.

1 is a diagram illustrating a structure of a processor including a conventional shifter capable of shifting a plurality of data.
2A, 2B, 2C, 2D, and 2E are diagrams illustrating various shift calculation methods of a conventional shifter.
3A and 3B are diagrams illustrating a shift device for shifting a plurality of data using two or more shifters.
4 and FIG. 4 are diagrams for explaining a structure and operation method of a funnel shifter capable of supporting various shift operations.
5 is a diagram illustrating a structure of an internal shifter of a funnel shifter capable of supporting various shift operations.
6A, 6B, and 7 are diagrams showing structures of a right shifter and a left shifter.
8A, 8B, and 8C are diagrams illustrating a configuration of a shift computing device according to an embodiment of the present invention and data used for shift calculation.
9A, 9B, 9C, 9D, 9E, and 9F are diagrams each illustrating an operation process of ASR, LSR, ROR, LSL, and ROL of a shift calculating apparatus according to an embodiment of the present invention.
10 is a flow chart illustrating a method of operating a shift calculating device according to an embodiment of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail through exemplary drawings. In adding reference numerals to elements of each drawing, it should be noted that the same elements are assigned the same numerals as possible even if they are indicated on different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the subject matter of the present invention, a detailed description thereof will be omitted.

In addition, in describing the constituent elements of the present invention, terms such as first, second, A, B, (a), (b) may be used. These terms are only used to distinguish the component from other components, and the nature, order, or order of the component is not limited by the term. Throughout the specification, when a part'includes' or'includes' a certain element, it means that other elements may be further included rather than excluding other elements unless otherwise stated. . In addition, terms such as'~ unit' and'module' described in the specification mean a unit that processes at least one function or operation, which may be implemented by hardware or software or a combination of hardware and software.

2A, 2B, 2C, 2D, and 2E are diagrams illustrating various shift calculation methods of a conventional shifter.

Shift opoeration is one of the bit processing instructions of computer registers, which means shifting the contents of each bit of a number or sign expressed in binary notation to the left or right. In general, the shift operation is used in a processor and a digital signal processor.

The shift operation is mainly classified into five operations in consideration of the shift direction and processing of shifted bit values. The five operations mean ASR (arithmetical shift right), LSR (logical shift right), ROR (rotate right), LSL (logical shift left), and ROL (rotate left).

Hereinafter, a process of shifting two pieces of data having a length of 16 bits and a bit value of an arbitrary binary number will be described, but the number of data, data length, and bit value are only examples, and are not limited thereto. The length of the data may be 8 bits, 16 bits, or 32 bits, and the bit value may be different from the example shown in the drawing. Further, the following data is described as being data using 2's complement, but this is only an example, and is not limited thereto, and 1's complement may be used.

In addition, in the following, A[n] is the nth bit of A data, A[m:n] is the bits from the mth bit to the nth bit of A data, and x{y} is the value y It means data with x bits.

Referring to FIG. 2A, LSR-shifted data by 2 to the right in 16-bit length data is illustrated. LSR is a shift method that shifts data to the right and adds a bit with a value of 0 as much as the shift amount to the upper bit position. org_value is data of 16 bits length before shift. shifted_value is data in which org_value is shifted by 2 to the right, and bits with a value of 0 are arranged in the upper bit position of the shifted data by the number corresponding to the shift amount of 2 (shifted_value[15:14] = 2{0} ).

Referring to FIG. 2B, data in which data of 16-bit length is ASR shifted to the right by 2 is illustrated. ASR is a shift method in which data is shifted to the right and the most significant bit of the data before shift is added to the upper bit position by the shift amount. The shifted_value is data in which org_value is shifted by 2 to the right, and org_value[15], which is the most significant bit of the data before shift, is arranged in the upper bit position of the shifted data by the number corresponding to the shift amount 2. Here, when org_value is expressed in two's complement, the most significant bit is a sign bit indicating a sign (shifted_value[15:14] = 2{org_value[15]}).

Referring to FIG. 2C, ROR-shifted data by 2 to the right in 16-bit length data is illustrated. ROR is a shift method of shifting the lower bit corresponding to the shift amount of data to the upper bit position. shifted_value is data obtained by shifting org_value by 2 to the right, and shifting org_value[1:0], the lower bits of the data before shift, by the number corresponding to the shift amount of 2 to the upper bit position of the shifted data (shifted_value[15). :14] = org_value[1:0]).

Referring to FIG. 2D, LSL shifted data by 2 to the left from 16-bit length data is illustrated. LSR is a shift method that shifts data to the left and adds a bit with a value of 0 as much as the shift amount to the lower bit position. shifted_value is data in which org_value is shifted by 2 to the left, and bits with a value of 0 are arranged in the lower bit position of the shifted data by the number corresponding to the shift amount of 2 (shifted_value[1:0] = 2{0} ).

Referring to FIG. 2E, ROL-shifted data by 2 to the left in 16-bit length data is illustrated. ROL is a shift method in which an upper bit corresponding to a shift amount of data is moved to a lower bit position. shifted_value is data obtained by shifting org_value by 2 to the left, and shifting org_value[15:14], the upper bits of the data before the shift, by the number corresponding to the shift amount of 2 to the lower bit position of the shifted data (shifted_value[1 :0] = org_value[15:14]).

3A and 3B are diagrams illustrating a shift device for shifting a plurality of data using two or more shifters.

3A, a first shift device 300 includes a 16-bit shifter 302 capable of shifting 16-bit data, an 8-bit shifter 304 capable of shifting 8-bit data, and two 8-bit data. It includes a concatenate 306 capable of concatenating and outputting 16-bit data.

When IN[15:0] is one 16-bit data, the first shift device 300 transfers IN[15:0] to the 16-bit shifter 302, and the 16-bit shifter 302 is IN[15 It is possible to output OUT[15:0] that has performed a shift operation on :0].

When IN[15:0] is the data connected with two 8-bit data (IN[7:0] = Data_A[7:0], IN[15:8] = Data_B[7:0]), the first The shift device 300 separates IN[15:0] into two 8-bit data. One 8-bit data may be shifted by the 16-bit shifter 302, and the other 8-bit data may be shifted by the 8-bit shifter 304. In this case, 8-bit data to be input to the 16-bit shifter 302 needs to be converted into 16-bit data through a sign-extension or zero-extension process. Two 8-bit data shifted by the 16-bit shifter 302 and the 8-bit shifter 304 are connected at the connection part 306 and output as OUT[15:0].

Referring to FIG. 3B, the second shift device 310 may include a left shifter 312 and a right shifter 314. The left shifter 312 and the right shifter 314 may include two 8-bit shifters therein to shift IN[15:0]. The left shifter 312 may perform an LSL or ROL operation, and the right shifter 314 may perform an LSR, ASR, or ROR operation.

When IN[15:0] is data to which two 8-bit data are connected, the second shift device 310 separates IN[15:0] into two 8-bit data, and then divides IN[15:0] into two 8-bit data. Data is transmitted to the left shifter 312 and the right shifter 314. That is, the left shifter 312 and the right shifter 314 receive data of a total length of 16-bit. Two 8-bit shifters located inside the left shifter 312 receive two 8-bit data, respectively, and perform a shift operation. The left shifter 312 may connect and output two 8-bit data output from two 8-bit shifters. The right shifter 314 operates on the same principle as the left shifter 312. The second shift device 310 may perform a shift operation on two 8-bit data in parallel through the above process.

When IN[15:0] is one 16-bit data, the second shift device 310 separates IN[15:0] into two 8-bit data, and then parallelizes each 8-bit data. You can perform the shift operation as an alternative. At this time, the second shift device 310 has a longer logical depth due to a path for transferring data between two 8-bit shifters, and only one of the left shifter 312 or the right shifter 314 operates during a shift operation. Therefore, its utilization is low compared to the number of shifters.

4 and are diagrams for explaining a structure and an operating method of a funnel shifter capable of supporting various shift operations.

4, a funnel shifter 400 and a mux control signal table are illustrated. The funnel shifter 400 may include an internal shifter 410, and when the number of input data is m and the length of the input data is n-bits, the internal shifter 410 is at most 2×m×n bits. Shift operation can be performed by receiving data. The funnel shifter 400 may perform ASR, LSR, ROR, LSL, and ROL operations using the internal shifter 410.

In addition, the funnel shifter 400 may include a multiplexer capable of differently inputting upper n-bits and lower n-bits to the internal shifter 410, respectively. In addition, the funnel shifter 400 may include a mux capable of transmitting a shift offset value to the internal shifter 410 using a shift amount. The funnel shifter 400 may include a subtractor in addition to mux to generate an offset value suitable for a shift operation.

Hereinafter, 16{0} refers to 16-bit data having a value of 0, and 16{IN[15]} refers to 16-bit data having a value of IN[15]. The internal shifter 410 may receive any one of 16{0}, 16{IN[15]}, or IN[15:0] at the upper bit position, and 16{0} or IN[15] at the lower bit position. :0] can be entered. In addition, the internal shifter 410 may receive an offset value in the form of binary data. The offset value makes the maximum length of the input data the maximum. In Fig. 4, since the maximum length of IN[15:0] is 16 bits, the maximum offset value is 16 in decimal and 1-1-1-1 (4 bits) in binary.

Hereinafter, the ASR operation process will be described. LSR, ROR, LSL and ROL work on the same principle.

The internal shifter 410 receives 16{IN[15]} at the upper bit position and IN[15:0] at the lower bit position. The internal shifter 410 receives a total of 32-bit data, and may select and output 16-bit data from 32-bit data. Here, the selected 16-bit data is 16-bit data at a position separated from the least significant bit (LSB) of 32-bit data to the left by an offset value (sh). As a result, the selected 16-bit data is data in which IN[15:0] is shifted to the right by a shift amount, and sign bits are arranged at an upper bit position corresponding to the shift amount. That is, the selected 16-bit data sh_out[15:0] is sh_out[15-sh:0]=IN[15:sh], and sh_out[15:15-sh+1]=IN[sh-1:0] Is data.

5 is a diagram illustrating a structure of an internal shifter of a funnel shifter capable of supporting various shift operations.

Referring to FIG. 5, the structure of the internal shifter 410 and the control process of mux are shown. The internal shifter 410 receives input[31:0] having twice the length of IN[15:0]. sh_amt[3:0] is a value representing the shift amount in 4-bit binary, and sh_amt[3] is the most significant bit of sh_amt[3:0]. The mux at the top receives input[31:8] and input[22:0] as inputs, outputs input[31:8] when sh_amt[3] is 1, and outputs sh_amt[3] If it is 0, input[22:0] is output. You can control 4 mux with the same operation method as above. In FIG. 5, since the value of the shift amount sh_amt[3:0] is 0, the finally output data mux_L0_out[15:0] is data having the same value as IN[15:0].

6A, 6B, and 7 are diagrams showing structures of the right shifter and the left shifter.

6A and 6B, the internal structure of the right shifter 314 illustrated in FIG. 3B is shown. The number of muxes and logical depth used in the right shifter 314 will be described later in Table 1.

Referring to FIG. 7, the internal structure of the left shifter 312 illustrated in FIG. 3B is shown. The number of muxes and logical depths used in the left shifter 312 will be described later in Table 1.

8A, 8B, and 8C are diagrams illustrating a configuration of a shift computing device according to an embodiment of the present invention and data used for shift calculation.

Referring to FIG. 8A, a shift calculating apparatus according to an embodiment of the present invention may include a mixer unit 810, an offset generator 820, a shift unit 830, and a splitter unit 840. The shift operation apparatus according to an embodiment of the present invention may shift at least two input data including a plurality of bits in parallel. In addition, the shift calculating apparatus according to another embodiment of the present invention may shift input data using only the shift unit 830 when shifting one input data. Additionally, the shift computing device according to another embodiment of the present invention may operate within the processor 110 illustrated in FIG. 1.

The mixer unit 810 may mix input data input to the shift calculating device. When the number of input data is two or more, the mixer unit 810 may mix the input data by alternately arranging the bits of the two or more input data. Here, in the alternating arrangement, bits having the same bit index among the bits of the input data are arranged adjacently, but arranged in an ascending order and an alternating order of the bit index. The ascending order of the bit index means the order from LSB to MSB.

Referring to FIG. 8B, mixed data having a 16-bit length by alternately arranging two 8-bit data by the mixer unit 810 according to an embodiment of the present invention is illustrated.

The offset generator 820 may generate a shift offset value of mixed data by using a shift amount of input data. The offset generator 820 may also include a subtractor in addition to mux to generate an offset value suitable for a left shift operation.

The offset value generated by the offset generator 820 may be expressed as either a decimal number or a binary number. On the other hand, when the number of bits of the mixed data is 2 to the power of n (reverse power), the maximum bit length of the offset value expressed in binary is n-bits.

The offset generator 820 according to an embodiment of the present invention may generate a value obtained by multiplying the shift amount of input data by the number of input data as an offset value.

In addition, the offset generator 820 according to another embodiment of the present invention may generate a value obtained by subtracting a value obtained by multiplying the number of input data by the shift amount of input data from the number of bits of mixed data as an offset value.

In addition, according to an embodiment of the present invention, when the number of input data is 2 to the power of n (n is a non-negative integer), and the shift amount is expressed as binary data, the offset value is a value obtained by left shifting the shift amount by n. Can be In this case, the offset generator 820 may generate an offset value using a hard-wired structure without separately adding hardware for implementing a logical structure such as a mux.

The shift unit 830 may receive mixed data by the mixer unit 810, shift the mixed data by an offset value, and output the shifted data. The shift unit 830 may perform at least one of ASR, LSR, ROR, LSL, and ROL on the mixed data.

The maximum length of data that can be shifted by the splitter unit 830 is the sum of the number of bits of input data. That is, the maximum length of the shiftable data of the shift unit 830 is a value obtained by multiplying the number of bits of input data by the number of input data.

The shift unit 830 according to an embodiment of the present invention includes a shifter capable of shifting only in one direction. The shift unit 830 according to an embodiment of the present invention may include a funnel shifter, and an operation method thereof will be described later in FIGS. 9A to 9F.

The splitter unit 840 is a component capable of receiving shifted data by the shift unit 830 and outputting the shifted data by separating the shifted data by the number of input data, contrary to the operation of the mixer unit 810. That is, the splitter unit 840 may generate output data corresponding to the number of input data by separating each bit of the shifted data.

For example, when the input data is two 8-bit data, the mixed data is 16-bit data in which the input data is alternately arranged, and the splitter unit 840 converts the mixed data to bits having an even bit index and Two 8-bit data can be output by separating them into odd bits.

Referring to FIG. 8B, the splitter unit 840 according to an embodiment of the present invention separates mixed data having a 16-bit length, and the separated two 8-bit data are illustrated.

Hereinafter, a data processing process of the mixer unit 810 and the splitter unit 840 according to an embodiment of the present invention will be described with a relational expression.

The number of input data is N, and the number of bits of each input data is L, which is D_n[L-1:0] (where D_n is the nth input data, n=0, 1, ..., N-1) When expressed as, the data IN received by the mixer unit 810 satisfies Equation 1.

When the output of the mixer unit 810 is Mout, the input of the splitter unit 840 is shifted_Mout, and the output of the splitter unit 840 is Sout,'m mod N'denotes the remainder of m divided by N, Mout Satisfies Equation 2, and Sout satisfies Equation 3.

9A, 9B, 9C, 9D, 9E, and 9F are diagrams each illustrating an operation process of ASR, LSR, ROR, LSL, and ROL of a shift calculating apparatus according to an embodiment of the present invention.

Referring to FIG. 9A, two 8-bit data to be shifted by a shift operation apparatus according to an embodiment of the present invention are illustrated.

Assuming that the two data A and B are expressed in two's complement, A represents 25 and B represents -56. 16-bit data is data that connects two data by placing A at the lower bit position and B at the upper bit position. Hereinafter, the input data will be described as A and B data, but this is only an example and is not limited thereto, and the number of data, number of bits, or bit value may vary. In addition, it will be described as shifting the A and B data by 2-bit, respectively.

The operation process of the shift operation apparatus according to the embodiment of the present invention described below can be performed by storing the code including the operation process in a memory, and executing the code stored in the memory by a processor located outside the shift operation apparatus. have.

Referring to FIG. 9B, an operation of performing an arithmetical shift right (ASR) operation by a shift calculating apparatus according to an embodiment of the present invention is illustrated.

The mixer unit 810 receives IN[15:0] which is 16-bit data by connecting A and B data. The mixer unit 810 outputs the mixed data M[15:0] by using Equation 2. M[15:0] is an alternate arrangement of A and B data, and is 16-bit data arranged in ascending order of bit index in LSB.

The shift unit 830 according to an embodiment of the present invention shifts the mixed data M[15:0] to the right by 4 (shifter_ouput[11:0]=M[15:4], Data in which the sign bits (most significant bits) of A and B data are arranged at the bit position, respectively, can be output (shifter_output[15:12]=4{M[15], M[14]}).

When the shift unit 830 according to an embodiment of the present invention is a funnel shifter, the shift unit 830 receives data having a length twice the length of the mixed data. Referring to FIG. 8C, the shift unit 830 receives the mixed data M[15:0] as a lower bit position, and 16-bit data in which M[15] and M[14] are repeatedly arranged at the upper bit position. Is entered. Here, M[15] and M[14] are the sign bit of B data and the sign bit of A data, respectively. The shift unit 830 selects and outputs 16-bit data based on a bit at a position separated from the least significant bit by an offset value from the 32-bit data. Here, the offset value is 4, which is a value obtained by multiplying 2, which is the shift amount, by 2, which is the number of input data. As a result, the shift unit 830 may right-shift the mixed data M[15:0] by 4, and then output data obtained by repetitively arranging the sign bits of A and B at the upper bit position by the offset value.

The splitter unit 840 receives the data output from the shift unit 830, separates it, and outputs the same number of data as the number of input data. That is, the splitter unit 840 may output two 8-bit data by using Equation 3.

As a result, if input data IN[15:0] and output data OUT[15:0] are compared, OUT[7:0], the lower 8-bit of output data, is the data obtained by ASR operation by 2, and output OUT[15:8], the upper 8-bit of data, is the data obtained by ASR operation of B data by 2. As described above, the shift calculating apparatus according to an embodiment of the present invention can shift at least two pieces of data in parallel.

9A and 9C, an operation of performing a logical shift right (LSR) operation by a shift calculating apparatus according to an embodiment of the present invention is illustrated.

Hereinafter, the operations of the mixer unit 810 and the splitter unit 840 are the same as those described in FIG. 9B, and thus will be omitted.

The shift unit 830 according to an embodiment of the present invention shifts the mixed data M[15:0] to the right by 4 (shifter_ouput[11:0]=M[15:4], Data in which bits with a value of 0 are arranged at the bit position can be output (shifter_output[15:12]=4{0}).

When the shift unit 830 according to an embodiment of the present invention is a funnel shifter, the shift unit 830 receives data having a length twice the length of the mixed data. Referring to FIG. 8C, the shift unit 830 receives mixed data M[15:0] as a lower bit position and 16-bit data having all 0 values at an upper bit position. The shift unit 830 selects and outputs 16-bit data based on a bit at a position separated from the least significant bit by an offset value from the 32-bit data. Here, the offset value is 4, which is a value obtained by multiplying 2, which is the shift amount, by 2, which is the number of input data. As a result, the shift unit 830 may right-shift the mixed data M[15:0] by 4, and then output data in which 4-bits having a value of 0 are arranged at the upper bit position.

If input data IN[15:0] and output data OUT[15:0] are compared, OUT[7:0], the lower 8-bit of output data, is the data obtained by LSR operation of A data by 2, and The upper 8-bit OUT[15:8] is the data obtained by LSR operation of B data by 2.

9A and 9D, an operation of performing a rotate shift right (ROR) operation by a shift operation apparatus according to an embodiment of the present invention is illustrated.

The shift unit 830 according to an embodiment of the present invention shifts the mixed data M[15:0] to the right by 4 (shifter_ouput[11:0]=M[15:4], Data obtained by arranging the lower bits of the data mixed at the bit position can be output (shifter_output[15:12]=M[3:0]).

When the shift unit 830 according to an embodiment of the present invention is a funnel shifter, the shift unit 830 receives data having a length twice the length of the mixed data. Referring to FIG. 8C, the shift unit 830 receives mixed data M[15:0] to the lower bit position and the upper bit position. The shift unit 830 selects and outputs 16-bit data based on a bit at a position separated from the least significant bit by an offset value from the 32-bit data. Here, the offset value is 4, which is a value obtained by multiplying 2, which is the shift amount, by 2, which is the number of input data. As a result, the shift unit 830 may right-shift the mixed data M[15:0] by 4, and then output data obtained by shifting the lower 4-bit of the mixed data to the upper bit position.

If input data IN[15:0] and output data OUT[15:0] are compared, OUT[7:0], the lower 8-bit of output data, is the data obtained by RORing A data by 2, and The upper 8-bit OUT[15:8] is the data obtained by ROR operation of B data by 2.

9A and 9E, an operation of performing a logical shift left (LSL) operation by a shift operation apparatus according to an embodiment of the present invention is illustrated.

The shift unit 830 according to an embodiment of the present invention shifts the mixed data M[15:0] to the left by 4 (shifter_ouput[15:4]=M[11:0], Data obtained by arranging bits with a value of 0 at the bit position can be output (shifter_output[3:0]=4{0}).

When the shift unit 830 according to an embodiment of the present invention is a funnel shifter, the shift unit 830 receives data having a length twice the length of the mixed data. Referring to FIG. 8C, the shift unit 830 receives mixed data M[15:0] as an upper bit position and 16-bit data having all 0 values at the lower bit position. The shift unit 830 selects and outputs 16-bit data based on a bit at a position separated from the least significant bit by an offset value from the 32-bit data. Here, the offset value is a value obtained by subtracting 4, which is a value obtained by multiplying the shift amount 2 by 2, which is the number of input data, from 16, which is the number of bits of mixed data. As a result, after shifting the mixed data M[15:0] to the left by 4, the shift unit 830 may output data in which 4-bits having a value of 0 are arranged at a lower bit position.

If input data IN[15:0] and output data OUT[15:0] are compared, OUT[7:0], the lower 8-bit of output data, is the data obtained by LSL operation of A data by 2, and The upper 8-bit OUT[15:8] is the data obtained by LSL operation of B data by 2.

9A and 9F, an operation of performing a rotate shift left (ROL) operation by a shift operation apparatus according to an embodiment of the present invention is illustrated.

The shift unit 830 according to an embodiment of the present invention shifts the mixed data M[15:0] to the left by 4 (shifter_ouput[15:4]=M[11:0], Data obtained by arranging the lower bits of the mixed data at the bit position can be output (shifter_output[3:0]=M[15:12]).

When the shift unit 830 according to an embodiment of the present invention is a funnel shifter, the shift unit 830 receives data having a length twice the length of the mixed data. Referring to FIG. 8C, the shift unit 830 receives mixed data M[15:0] to the lower bit position and the upper bit position. The shift unit 830 selects and outputs 16-bit data based on a bit at a position separated from the least significant bit by an offset value from the 32-bit data. Here, the offset value is a value obtained by subtracting 4, which is a value obtained by multiplying the shift amount 2 by 2, which is the number of input data, from 16, which is the number of bits of mixed data. As a result, the shift unit 830 may shift the mixed data M[15:0] to the left by 4, and then output data obtained by shifting the lower 4-bit of the mixed data to the lower bit position.

If input data IN[15:0] and output data OUT[15:0] are compared, OUT[7:0], the lower 8-bit of output data, is the data obtained by ROL operation of A data by 2. The upper 8-bit OUT[15:8] is the data obtained by ROL operation of B data by 2.

Table 1 is a table comparing the number of muxes and logical depths used in the funnel shifter and the shift calculating apparatus according to an embodiment of the present invention.

Area (# of 2-to-1 mux) logical depth pre-mux shifter-mux post-mux offset total 1 data funnel shifter 16bit 48
(16×2+16) 75
(23+19+17+16) 0 4 127 6 8bit 24
(8×2+8) 27
(8+9+10) 0 3 54 5 2 data known shifter Figure 3a 16 181
(127+54) 16 0 213
(100%) 8
(1+6+1) Fig. 3b 0 203
(96+111) 16 0 219
(102.82%) 11
(10+1) present invention 96
(16×4+16×2) 75
(23+19+17+16) 16 8
(4+4) 195
(91.55%) 8
(3+4+1)

Referring to Tables 1 and 4, the number of muxes of a funnel shifter required to shift one piece of data can be calculated. Here, one mux may receive two bits and output one bit. Looking at the pre-mux item of the funnel shifter, the funnel shifter 400 may input 16-bit data to the upper bit position and the lower bit position of the internal shifter 410. Two 2-to-1 muxes per bit are used to input either 16{0}, 16{IN[15]}, or IN[15:0] to the upper bit position. To input 16-bit data in the upper bit position, 16×2=32 muxes are used. 16 muxes are used to input 16-bit data by selecting 16{0} or IN[15:0] in the lower bit position. Therefore, a total of 48 pre-mux are used.

Further, referring to the shifter-mux item and FIG. 5, the number of muxes required for the internal shifter 410 to select 16-bit data, which is data shifted by an offset value from 32-bit data as described in FIG. 5, is There are 75. That is, 23 muxes required to output 23 bits in the first step, 19 muxes required to output 19 bits in the second step, 17 muxes required to output 17 bits in the third step, and This is the sum of 16 muxes needed to output 16 bits in the fourth step.

Referring to the offset item and FIG. 4, four muxes are used to input the offset value expressed as 4-bit data to the internal shifter.

Referring to the logical depth item, logical depth 1 in the input step of inputting two 16-bit data to the internal shifter in the 16-bit funnel shifter, and logical depth 1 in the step of entering the offset value in the internal shifter. In the step of shifting 16-bit data, logical depth 4 is added, so that the logical depth of the 16-bit funnel shifter is 6.

Referring to Table 1 and FIG. 3A, the first shift device 300 selects 16-bit data obtained by performing IN[15:0] and sign/zero extension to the 16-bit shifter 302. -mux is used. In addition, since the number of internal muxes used in the 16-bit shifter 302 and the 8-bit shifter 304 are 127 and 54, respectively, a total of 181 shifter-muxes are used. In addition, 16 post-muxes are used to select and output one of 16-bit data, which is the output data of the 16-bit shifter 302 and 16-bit data, which is the output data of the connector 306. The first shift device 300 uses a total of 213 muxes, which is 100%, and compares the number of muxes of other shifters. Also, the logical depth of the first shift device 300 is 8.

Referring to Tables 1, 3B, 6A, and 6B, the second shift device 310 uses a total of 219 muxes, and requires 102.82% of the number and area of the muxes compared to the first shift device 300. do. The logical depth of the second shift device 310 is 11.

Referring to Table 1 and FIG. 8A, the shift calculating apparatus according to an embodiment of the present invention includes 16{0}, 16{IN[15]}, and M[15:0] at the upper bit positions of the shift unit 830. Or, to input any one of 16{M[15], M[14]}, that is, to select 2 out of 4 data and then to select 1 out of 2 data, a total of 16×3=48 2 -to-1 mux is used. Likewise, 16×2=32 muxes are used to input data in the lower bit position. Therefore, the shift calculation unit requires a total of 96 pre-muxes.

Referring to the shifter-mux item, the shift calculating apparatus according to an embodiment of the present invention uses a total of 75 shifter-mux, and either output data of the shift unit 830 and output data of the splitter unit 840 Use 16 post-mux to select.

The shift operation apparatus according to the embodiment of the present invention uses a total of 195 2-to-1 muxes to shift two 8-bit data in parallel. That is, the shift calculation device may be implemented using only 91.55% of the number of mux used in the conventional first shifter device 300. This is a result of comparison when two input data are shifted, and the shift calculating apparatus according to an embodiment of the present invention can shift data in parallel with only a smaller ratio of mux as the number of input data increases.

In addition, the total logical depth of the shift computing device according to the embodiment of the present invention is 8. This is a sum of logical depth 1 in the input step of the shift unit 830, logical depth 2 in the offset step, 4 logical depth in the internal step of the shift unit 830, and logical depth 1 in the post-mux step. This is the same value as the logical depth of the conventional first shift device 300, and the shift calculation device according to the embodiment of the present invention has the same calculation speed as the conventional shifter, but has less hardware area and less power consumption. Means that you can shift multiple data. This is a result of comparison when two pieces of data are shifted in parallel, and as the number of input data increases, the shift calculating apparatus according to an exemplary embodiment of the present invention may have a faster operation speed than the conventional shifter.

10 is a flow chart illustrating a method of operating a shift calculating device according to an embodiment of the present invention.

First, the shift calculating apparatus according to an embodiment of the present invention collects information on the number of input data and the number of bits (S1000).

The shift calculator may set the maximum length of data that can be shifted by the shift unit 830 in consideration of the number of collected input data and the number of bits, and then implement the shift unit 830 through a logical structure ( S1002). When the number of input data is m and the length of the input data is n-bits, the shift unit 830 according to an embodiment of the present invention may receive data of up to 2×m×n bits and perform a shift operation.

The shift calculating apparatus implements the mixer unit 810 and the splitter unit 840 in consideration of the number of collected input data and the number of bits (S1004). The mixer 810 may set a value obtained by multiplying the number of input data by the number of bits to be a maximum bit length that can be mixed. In addition, the splitter unit 840 may set a value obtained by multiplying the number of input data by the number of each bit as a maximum bit length that can be separated.

The shift calculating apparatus implements an offset generator 820 that generates an offset value using the number of collected input data and each shift amount of the input data (S1006). The offset value generated by the offset generator 820 may vary according to ASR, LSR, ROR, LSL, or ROL operations.

In order to perform an ASR, LSR, ROR, LSL, or ROL operation, the shift calculating apparatus may generate a data table and an input mux structure for input data and offset values of the shift unit 830 (S1008). That is, the shift unit 830 may perform a shift operation by receiving different data and an offset value for each operation with reference to the data table of FIG. 8C.

The shift calculating apparatus may generate a signal for controlling an input mux structure so that the shift unit 830 can receive data according to the data table, and control the mux (S1010).

The shift unit 830 may receive the data mixed by the mixer unit 810 through a mux, perform a shift operation, and then transmit the shifted data to the splitter unit 840 (S1012).

The splitter unit 840 separates the shifted data received from the shift unit 830, but may separate and output as many input data as the number of input data based on an operation principle opposite to that of the mixer unit 810 (S1014). That is, the splitter unit 840 may alternately separate and output the shifted data by the number of input data.

In FIG. 10, steps S1000 to S1014 are described as sequentially executing, but this is merely illustrative of the technical idea of an embodiment of the present invention. In other words, if one of ordinary skill in the technical field to which an embodiment of the present invention belongs, execute it by changing the order shown in FIG. 6 without departing from the essential characteristics of an embodiment of the present invention, or one of the processes S1000 to S1014. Since the above processes are executed in parallel, various modifications and variations may be applied, and thus FIG. 10 is not limited to a time series order.

Meanwhile, the processes shown in FIG. 10 can be implemented as computer-readable codes on a computer-readable recording medium. The computer-readable recording medium includes all types of recording devices that store data that can be read by a computer system. That is, the computer-readable recording medium includes storage media such as magnetic storage media (eg, ROM, floppy disk, hard disk, etc.) and optical reading media (eg, CD-ROM, DVD, etc.). In addition, the computer-readable recording medium can be distributed over a computer system connected through a network to store and execute computer-readable codes in a distributed manner.

The above description is merely illustrative of the technical idea of the present embodiment, and those of ordinary skill in the technical field to which the present embodiment belongs will be able to make various modifications and variations without departing from the essential characteristics of the present embodiment. Accordingly, the present exemplary embodiments are not intended to limit the technical idea of the present exemplary embodiment, but are illustrative, and the scope of the technical idea of the present exemplary embodiment is not limited by these exemplary embodiments. The scope of protection of this embodiment should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present embodiment.

100: memory 110: processor
300: first shift device 310: second shift device
400: funnel shifter 810: mixer unit
820: offset generation unit 830: shift unit
840: splitter unit

Claims (16)

In the shift operation apparatus capable of performing a shift operation on at least two input data each including a plurality of bits,
A mixer for outputting mixed data by alternately arranging each bit of the at least two input data;
An offset generator generating a shift offset value that is a value obtained by multiplying a shift amount of the at least two input data by the number of the at least two input data;
A shift unit for generating shifted data by performing a shift operation on the mixed data using the offset value; And
Splitter unit for generating at least two output data corresponding to the at least two input data by separating each bit of the shifted data
Shift calculation device comprising a. The method of claim 1,
The alternating arrangement,
A shift operation device for arranging bits of the input data with the same bit index adjacently, but in an ascending and alternating order of the bit index. The method of claim 1,
The offset value is,
When the number of the input data is 2 to the power of n (n is a non-negative integer), and when the shift amount is expressed as binary data, the shift amount is left-shifted by n. The method of claim 1,
The shifted data is data obtained by shifting the mixed data to the right by the offset value and alternately arranging the MSBs of the input data at a higher bit position corresponding to the offset value. The method of claim 1,
The shifted data is data obtained by right-shifting mixed data by the offset value and arranging bits having a value of 0 at an upper bit position corresponding to the offset value. The method of claim 1,
The shifted data is data obtained by moving lower bits corresponding to the offset value in the mixed data to an upper bit position. The method of claim 1,
The shifted data is data obtained by shifting mixed data to the left by the offset value and arranging bits having a value of 0 at a lower bit position corresponding to the offset value. The method of claim 1,
The shifted data is data obtained by moving upper bits corresponding to the offset value in the mixed data to a lower bit position. In the operating method of a shift operation device capable of performing a shift operation on at least two input data each including a plurality of bits,
Generating mixed data by alternately arranging each bit of the at least two input data;
Generating a shift offset value obtained by multiplying the shift amount of the at least two input data by the number of the at least two input data;
Generating shifted data by performing a shift operation on the mixed data using the offset value; And
The process of generating at least two output data corresponding to the at least two input data by separating each bit of the shifted data
Operating method of the shift calculating device comprising a. The method of claim 9,
The alternating arrangement,
A method of operating a shift operation apparatus, wherein bits having the same bit index among the bits of the input data are arranged adjacently, and arranged in ascending and alternating order of the bit index. The method of claim 9,
The offset value is,
When the number of the input data is 2 to the power of n (n is a non-negative integer) and the shift amount is expressed as binary data, the shift amount is left-shifted by n. The method of claim 9,
The shifted data is data obtained by right shifting the mixed data by the offset value and alternately arranging each most significant bit of the input data at a higher bit position corresponding to the offset value. The method of claim 9,
The shifted data is data obtained by right shifting the mixed data by the offset value and arranging bits having a value of 0 at an upper bit position corresponding to the offset value. The method of claim 9,
The shifted data is data obtained by moving lower bits corresponding to the offset value in the mixed data to an upper bit position. The method of claim 9,
The shifted data is data obtained by shifting mixed data to the left by the offset value and arranging bits having a value of 0 at a lower bit position corresponding to the offset value. The method of claim 9,
The shifted data is data obtained by moving upper bits corresponding to the offset value in the mixed data to a lower bit position.

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