JPH0717119B2 - Template for IC drawing - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an IC used for pattern design of a semiconductor integrated circuit.
Regarding a drafting template.

[Conventional technology]

Conventionally, in pattern design at the desk top design stage of bipolar analog ICs, various components are symbolized and laid out, but with recent miniaturization of design standards, process complexity, and increase in the number of elements, The design period of pattern design is increasing, and design mistakes are increasing.

In order to solve these problems, an IC drawing template is designed for each process and used for pattern design of bipolar analog ICs. The size of the dedicated IC drafting template is 80mm x 160m due to easy handling.
Although it is about m, it is impossible to cover the symbolic figures of all the transistors used in the chip in this limited size.

In addition, after the drawings that have been designed on the desk have undergone various checks, they are digitized and the data is stored in the artwork processing system as a database.For square data such as bonding pads, a reference cross point is defined at the center. It has the advantage that it can be input with one digitization. In the conventional IC drawing template, a square figure was defined only by the L-shaped slits at the corners, so digitizing work was required twice or more.

Also, L representing an insulating layer region that defines the transistor region
Since the character-shaped slit was aligned with the center of the slit and the center of the line on the graph paper by visual inspection, the accuracy was lacking and it took time to align.

[Problems to be solved by the invention]

Since the conventional IC drawing template described above accommodates the symbol graphics of various components required for drawing in a limited size, it has only the symbol graphics of the reference size transistor. For square data, only the corner portion is provided, and the L-shaped slit defining the outer frame has no center indication. Therefore, it has a drawback that it cannot be used for designing transistors out of the standard size.
In addition, there is a disadvantage that digitizing requires time, inaccurate alignment, and is time-consuming.

[Means for solving problems]

The feature of the present invention resides in an IC drawing template in which a plurality of symbol graphics of components used for pattern design of a semiconductor integrated circuit are perforated on a transparent substrate, wherein the symbol graphics represent the outline of a transistor region. L-shaped slits, rectangular holes representing the electrode portions of the emitter, base and collector of the transistor, and one side of a quadrangle surrounded by the four L-shaped slits. It is an IC drawing template having at least one straight line which is parallel and is printed at a predetermined interval outside the quadrangle.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of the first embodiment of the first invention.

As shown in FIG. 1, a rectangular base B ₁ , a collector C ₁ and an emitter E ₁ which are formed on a transparent substrate 1 and are precisely formed at positions showing respective electrode portions of a collector C ₁ and an emitter E ₁ , respectively. Holes, four L-shaped slits 2 to 5 representing the center of the insulating layer defining the transistor region, and slits
A symbol figure composed of straight lines 6 and 7 printed in different colors in parallel with the side with a predetermined distance is included outside the side connecting the points 3 and 4.

The substrate 1 having a green color is effective for reducing eye fatigue even when used for a long time, and a thickness of 0.7 mm is appropriate in terms of strength and accuracy in drawing. . Diffuse reflection prevention processing is applied to the front surface, and printing is performed on the back surface to eliminate errors due to viewpoints.

Unlike the logic circuit diagram template, the accuracy of the IC drawing template is important for drawing. The IC drawing template of the present invention is designed so that the same drawing as the original drawing can be made when tracing the rectangular holes and slits formed in the substrate 1 with the thickness of the lead of a drawing pencil with a core diameter of 0.5 mm. . If the thickness of the substrate 1 is thick, there is an advantage that it is difficult to warp, but on the other hand, the tip of the payout pencil must be set upright and the accuracy becomes poor. mm is appropriate.

In FIG. 1, an emitter E ₁ , a base B ₁ , and a collector C ₁ show the metal-leading electrode portions of the respective electrodes, and the L-shaped slits 2-5 show the center of the insulating layer. By turning the substrate 1 over and using it, a transistor in which the positions of the electrode portions of the emitter E ₁ and the base B ₁ are reversed can be easily designed.

2 (a) to 2 (c) are plan views of a transistor for explaining a drawing procedure when a wiring is passed between a collector and a base using the embodiment of FIG. 1, respectively.

As shown in FIG. 2A, first, the lower slits 3 and 4, the emitter E ₁ and the base B ₁ are written on the paper 14. Then the second
As shown in FIG. 2B, the collector C ₁ and the slits 2 and 5 are written by overlapping the side connecting the slits 3 and 4 drawn on the paper 14 with the straight line 6.

As shown in FIG. 2 (c), one wire is written between the base B ₁ and the collector C ₁ . The wires are Al-widthed paths and the straight lines indicate the centerline of the wires. The intervals X ₁ and X ₂ between the sides formed by the slits 3 and 4 and the straight lines 6 and 7 are represented by the equations (1) and (2), respectively.

X ₁ = W−a (1) X ₂ = W + 2l−a (2) where a is the distance between the base B ₁ and the collector C ₁ , W is the wiring width, and 1 is the wiring distance.

When two wires are to be routed between the collector C ₁ and the base B ₁ , the straight line 7 printed in blue may be used instead of the straight line 6 printed in red in the above-mentioned entry method.

FIG. 3 is a plan view of the second embodiment of the first invention.

As shown in FIG. 3, a base B ₂ , a collector C _2, and an emitter E ₂ for an NPN type transistor formed on a substrate 1
Of the rectangular holes accurately formed at the positions indicating the respective electrode parts, the four slits 2a to 5a representing the center of the insulating layer defining the transistor region, and the side connecting the slits 2a and 3a. It includes a symbol figure composed of a red straight line 8 printed on the outer side in parallel with the side at a predetermined interval.

The straight line 8 is used to form a transistor in which the collector E ₂ , the base B ₂ , and the emitter E ₂ are long in the lateral direction from the standard size transistor. For example, when the size of the collector C ₂ is 2 μm × 6 μm, 2 μm × 10 μm It is used when a transistor having a collector size of

FIGS. 4 (a) and 4 (b) are plan views of a transistor for explaining a drawing procedure for designing a laterally long transistor using the embodiment of FIG. 3, respectively.

As shown in FIG. 4 (a), slits 2a, 3a, an emitter E ₂ and a collector C ₂ except the right side of the symbol graphic of FIG. 3 are written on the paper 14. Next, as shown in FIG. 4 (b), by writing the slits 4a and 5a, the base B ₂ and the collector C ₂ by aligning the side connecting the slits 2a and 3a and the straight line 8, It overlaps with the collector written from and becomes one collector, and a transistor long in the lateral direction can be drawn.

It should be noted that another straight line may be provided on the left side of the straight line 8 to draw various transistors having different lateral lengths.

Next, FIG. 5 is a plan view of another embodiment of the first invention.

As shown in FIG. 5, for the lateral type transistor formed on the substrate 1, rectangular holes showing the electrode portions of the emitter E ₃ and base B ₃ and slit-like holes showing the electrode portion of the collector C ₃ and the transistor are formed. Four L-shaped slits 2b to 5b representing the center of the insulating layer that defines the area, and the slit 2
It includes a symbol figure composed of two straight lines 9 and 10 which are printed in parallel to the side connecting the b and 3b at a predetermined interval.

FIGS. 6 (a) and 6 (b) are plan views of the lateral transistor for explaining the drawing procedure in the case of designing the lateral transistor of the double size in the lateral direction by using the embodiment of FIG.

As shown in FIG. 6 (a), the slits 2b and 3b, the emitter E ₃ , the base B ₃ and the collector are formed by using the symbolic figure of FIG.
Draw C ₃ on paper 14. Next, as shown in FIG. 6 (b), the straight line 9 is aligned with the left ends of the base B ₃ and the collector C ₃ , and the slits 4b and 5b are again formed by using the symbol figure of FIG.
And drawing the base B ₃ , emitter E ₃ and collector C ₃
A lateral transistor having a double emitter size can be formed.

By repeating the above procedure, a lateral transistor having an emitter size that is an integral multiple can be formed.

FIG. 7 is an equivalent circuit diagram of the lateral transistor shown in FIG.

Next, FIGS. 8 (a) and 8 (b) are plan views of the lateral transistor for explaining the drawing procedure in the case of designing the lateral transistor having the common base by using the embodiment shown in FIG.

As shown in FIG. 8 (a), the slits 2b and 3b, the emitter E ₃ , and the base B ₃ are formed on the paper 14 by using the symbolic figure of FIG.
And draw collector C ₃ . Next, as shown in FIG. 8 (b), the straight line 10 is aligned with the left end of the emitter E ₃ and again the slits 4b, 5b and the emitter E are formed by using the symbol figure shown in FIG.
Draw ₃ , base B ₃ and collector C ₃ .

As a result, a lateral transistor having a common base and electrically independent emitter and collector can be designed.

FIG. 9 is an equivalent circuit diagram of the lateral transistor having the common base shown in FIG.

A lateral transistor having three or more emitters and collectors can also be formed by repeating the above procedure.

A lateral transistor having a common base is often used in a current mirror circuit and the like, and if the emitter, the base and the collector are designed to be included in the same insulating layer region, the lateral transistor greatly contributes to the reduction of the chip size.

The above straight lines 6 to 10 are various design criteria, for example, insulating base spacing, base-collector contact diffusion region spacing,
The electrode spacing, the base width of the lateral transistor, the collector width and the locos width are all set.
In desktop design, the location and size of the transistors and the location of the electrodes are important, and no other internal cell information is needed.

The above-mentioned reference transistor and the artwork data of various transistors created from the reference transistor are registered in the database of various artwork systems, and the designer just digitizes based on the drawing designed by the IC drawing template. With this, even block or chip artwork can be processed.

FIG. 10 is a plan view of an example of a symbol graphic of a bonding pad.

As shown in FIG. 10, symbolic symbols represent bonding pads, and L-shaped slits 3c, 4c, 5c showing corners of the bonding pads formed on the substrate 1,
And a x-shaped slit 13 representing the center.

Since the bonding pad is square and does not wait for its orientation, the cell position can be represented only by the coordinates of the center, and the cell can be input with a single digitization.

However, at the desk design stage, the chip cannot be designed unless the size of the bonding pad is known, so the slits 3c, 4c, 5c represent the size and the x-shaped slit 13 represents the bonding pad coordinate.

At the time of digitizing, the cursor is aligned with the x-shaped slit 13 and input is performed only once, so that it is possible to reduce input mistakes and the operator's burden. In the case of this example, the L-shaped slit on the upper left is omitted, but it is omitted because there is another cell in the upper left part. Even if it is symbolized as shown in FIG. 10, the layout information is practically used. Is enough as

FIG. 11 is a plan view of a modified example of the L-shaped slit.

As shown in FIG. 11, an L-shaped slit 3d representing the center of the lower left insulating layer of the transistor formed on the substrate 1
And straight lines 11 and 12 respectively printed on the outside of the L-shape on the extension of the center lines of the two sides forming the L-shape of the slit 3d.

The slit 3d has a taper angle so that the lead of a pay-out pencil having a lead diameter of 0.5 mm can be fitted exactly.

When the layout is designed, the slits 3d are aligned with the squares of the graph paper to arrange the transistors. However, by overlapping the straight lines 11 and 12 with the squares of the graph paper, the alignment can be performed accurately and quickly.

〔The invention's effect〕

As described above, according to the present invention, symbol diagrams of various components used in IC pattern design can be written accurately and quickly, and various types of straight lines for guide lines that are not directly expressed as symbol graphics can be used. Since it is possible to draw the transistor of, it is possible to realize an extremely compact IC drawing template, improve the efficiency of pattern design, and reduce design mistakes.

[Brief description of drawings]

FIG. 1 is a plan view of the first embodiment of the present invention, and FIGS. 2A to 2C are diagrams showing the case where wiring is provided between the collector and the base using the embodiment of FIG. 1, respectively. A plan view of a transistor for explaining a drawing procedure, FIG. 3 is a plan view of a second embodiment of the first invention, and FIGS. 4 (a) and 4 (b) are respectively embodiments of FIG. FIG. 5 is a plan view of a transistor for explaining a drawing procedure in the case where a laterally long transistor is designed by using FIG. 5, FIG. 5 is a plan view of another embodiment of the first invention, FIGS. b) is a plan view of a lateral transistor for explaining a drawing procedure when laterally sized lateral transistors are designed by using the embodiment of FIG. 5, respectively, and FIG. 7 is a lateral view of FIG. The equivalent circuit diagram of the transistor is shown in FIGS. 8 (a) and 8 (b), respectively. 10 is a plan view of a lateral transistor for explaining a drawing procedure when a lateral transistor having a common base is designed by using FIG. 9, FIG. 9 is an equivalent circuit diagram of the lateral transistor having a common base shown in FIG. 8, and FIG. 10 is a bonding diagram. FIG. 11 is a plan view of a symbol graphic of the pad, and FIG. 11 is a plan view of a modified example of the L-shaped slit. 1 ... Substrate, 2-5, 2a-5a, 2b-5b, 3c-5c, 3d ... L-shaped slit, 6-12 ... Straight line, 13 ... X-shaped slit,
14 ...... _{paper, B 1, B 2, B} 3 ...... _{base, C 1, C 2, C} 3 ...... _{collector, E 1, E 2, E} 3 ...... emitter.

Claims (1)

[Claims] 1. An IC drawing template in which a plurality of types of symbol graphics of components used for pattern design of a semiconductor integrated circuit are perforated on a transparent substrate, wherein the symbol graphics include four contours representing a contour of a transistor region. The L-shaped slit, the rectangular holes representing the electrode portions of the emitter, base and collector of the transistor, and
An IC having at least one straight line parallel to any one side of a quadrangle formed by being surrounded by L-shaped slits and printed outside the quadrangle at a predetermined interval. Drafting template.