JPS6161900A - Template for ic drawing - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to an I.
Regarding C drawing templates.

[Conventional technology]

Pattern design for semiconductor integrated circuits (ICs), etc. is done by laying out various components on a desk based on a circuit diagram and wiring them. After completing the desk design, the pattern design drawings are digitized and written onto a magnetic disk, etc. This is accomplished by creating an artwork data that can be processed with a pattern generator or electronic exposure equipment.

At the theoretical design stage, various components such as transistors (Tr), diodes CDI), resistors, capacitors, etc., and functional blocks are symbolized and laid out, and these components are interconnected.

When laying out the overall IC diagram, the symbol diagram of the component is usually accurately laid out on a sheet of paper, enlarged about 200 times its actual size (for example, to 5 μm f: 1 mm). For example, when drawing an NPN) transistor as shown in Figure 1, the sizes of transistor 1 are a, b (
Contact portion electrodes 3.4. of the emitter (E), base (B), and collector (C) from the center line 2) of the element isolation layer and the reference cross point F (lower left corner of the center line of the element isolation layer 2). 5 must be accurately omitted on the drawing, paying attention to the position and size of the electrodes of each contact part.

This symbol diagram is drawn using a ruler or a plate with holes in simple shapes such as rectangles and circles, so as the number of components increases, the burden on the designer increases and also contributes to an increase in design time. ing. Specially due to the high integration of KICO, as the frequency of writing using graph paper (0.5mm) increases, the complexity of the drawings causes many errors, and corrections have to be made repeatedly. Therefore, there is a drawback that design errors are likely to occur.

[Problem that the invention seeks to solve]

The object of the present invention is to eliminate the above-mentioned drawbacks and to
& To provide an IC drawing template that allows accurate and quick drawing of symbol figures of components used in a meter.

[Means for solving problems]

The IC drawing template of the present invention is constructed by punching a plurality of symbol figures of components used in pattern design of semiconductor integrated circuits.

〔Example〕

Next, the present invention will be explained using examples and with reference to the drawings.

FIG. 2 μ is a plan view of an embodiment of the present invention.

In FIG. 2, a plate 10 made of a material that is easy to perforate and is inexpensive, such as Pukustick or mild steel plate, has the symbol shapes of transistors and diodes, which are often used in IC pattern design, accurately perforated.

For example, RTJI P N P ト'j ;/ し、x
, l (v-PNP) (7) In symbol figure 11, the positions and sizes of the electrodes of the emitter (E), base (B) and collector (C) contact parts are determined by the boundaries of the surrounding element isolation layers. By drawing the figure along the hole of the symbol figure 11, an accurate symbol figure of the PNP transistor can be drawn quickly and easily. be able to.

In addition to the normal type 12 symbol shapes for horizontal PNP transistors (L-PNP), there is also the multi-collector type 1.
3. A common base type 14 is provided, and a collector base sheet D115 and a collector base D116 are provided as diodes (Di), respectively, and NPN
) It can be used to draw accurate symbol shapes in the same way as the transistor symbol shapes.

Figure $3 is a plan view of another embodiment of the present invention.

The symbol figures in FIG.
A hole is provided in the plate 10 as in the case shown in the figure.

The resistance symbol figure 21 has its width W (μm), for example.
By writing in the numbers indicating the width W, it is possible to omit the symbol figure having the desired width W.

In particular, the shape of the folded portion is effective in improving drawing efficiency.

In addition, the waveform diagram 212 is convenient for writing a resistance diagram abbreviated in cases where the wiring and the resistance diagram overlap, and the density of the waveform can also be related to the width W of the resistance diagram.

Symbol figures 22 of resistance contacts include square ones, rectangular ones, and ones with scratch-shaped borders 22.
a is useful. The boundary line shouldering 222 is effective when the electrode of the contact portion is located inside the PN junction of the resistive contact portion, such as in a resistive contact portion for preventing electrostatic discharge damage.

Further, by arranging the resistor contacts from the center line of the insulation according to design standards, the layout and checking of the resistors can be easily performed.

The reference line figure 23 is useful, for example, when drawing or checking the center line part of a resistor using the center line of the element isolation layer as a reference. It is desirable to form lines by writing reference interval values.

The diagonal wiring 24 is useful for reducing the complexity of drawing multiple lines while being aware of the diagonal wiring spacing.

Although a symbol diagram of a flip-flop is shown as F-B1ock25, it is desirable to include symbol diagrams of power supplies, oscillators, etc., which are often used in pattern design, and this contributes to efficiency in drawing.

It is a good idea to write simple names around these symbol shapes to prevent misuse.

In the above embodiment, the case where the symbol figures of each component, which are relatively often used in IC pattern design, are drilled into the plate has been described, but the present invention is not limited to the illustrated symbol figures. matching pattern,
Of course, a figure such as a TEG band may be provided. Further, the symbol figures shown in FIGS. 2 and 3 may be perforated on one plate, and furthermore, a plurality of ICs may be formed according to design standards. ! ! It is also possible to prepare a template for Q. In this case, it is convenient to write the reference value as well as the name on the symbol figure to avoid misuse.

In the above explanation, the symbol figure is for a bipolar IC, but it can be similarly applied to a MOS LSI.

〔Effect of the invention〕

As explained in detail above, according to the present invention, it is possible to obtain an IC drawing template that can accurately and quickly draw symbol diagrams of various components used in IC pattern/design, thereby improving the efficiency of pattern design. It has a big effect.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining the symbol figure of a transistor in pattern design, FIG. 2 is a plan view of one embodiment of the present invention, and FIG. 3 is a plan view of another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Transistor, 2...Center line of element isolation layer, 3...Emitter contact part electrode, 4...Base: I contact part tL 5・
...Collector contact part electrode, 10...
...Plate, 11... Symbol diagram of vertical ff1 PNP transistor, 12.13° 14... Horizontal PNP) Symbol diagram of transistor, 15.16...
... Diode symbol diagram, 21... Resistor symbol diagram, 22... Resistor contact part symbol diagram, 23... Reference line symbol diagram, 2
4... Symbol diagram of diagonal wiring, 25...
- Symbol diagram of function blocks. Rod 1 time 3 times

Claims (5)

[Claims] (1) An IC drawing template characterized in that a plurality of symbol figures of components used for pattern design of semiconductor integrated circuits are punched. (2) The IC drawing template according to claim 1, wherein the name of the symbol is written on the periphery of the symbol. (3) The shapes of the emitter, base, and collector electrodes of various bipolar transistors, the anode and cathode electrodes of diodes, and the mutual arrangement of the electrodes are accurately opened on the template according to the design drawing magnification. The template according to claim 1, wherein L-shaped slits defining insulation centers of the insulating layers constituting the transistors and diodes are arranged at two or more locations at least in opposing corners. . (4) The shape of the resistive contact electrode portion or the shape of the resistive contact electrode portion and the resistive contact portion having an L-shaped slit indicating the contact portion diffusion region are arranged close to the resistive contact and meeting the design criteria. The template according to claim 1, which comprises a straight slit indicating the insulation center of a certain insulation layer. (5) The shape of the electrodes of each terminal for input/output, clock, power supply, etc. of various functional blocks used in semiconductor integrated circuits and the mutual arrangement of the electrodes are windowed on the template according to the design drawing magnification. 2. The template according to claim 1, wherein L-shaped slits defining the size of the functional block are provided at two or more locations at least at opposing corner portions.