JPH07169956A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor memory device which causes no access delay after it is put in an active state and is capable of very accurately controlling a word line in potential restraining a leakage current. CONSTITUTION:Row decoders RDCA1 to RDCAm and RDCB1 to RDCBm are driven by a second step-up voltage VWL2 higher a first step-up voltage VWL1 when a chip is actuated from a standby state. Therefore, a chip causes no access delay it is put in an active state. As pre-decoders PDC1 to PDCn which supply a potential to a word line are driven by the first step-up voltage VWL1 stabilized after the chip is put in an active state, the word line can be very accurately controlled in potential.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device such as a non-volatile memory, and more particularly to a semiconductor memory device which drives a word line by a potential generated by a booster circuit in a semiconductor chip.

[0002]

2. Description of the Related Art Non-volatile semiconductor memory such as EPRO
M (Erasable Programmable ROM), EEPROM (Elect
rically Erasable Programmable ROM), Flash EE
In the PROM, the cell transistor has a two-layer gate structure having a floating gate that is in an electrically floating state and a control gate that is provided above the floating gate and is a normal gate electrode. When data is stored in this cell transistor, the amount of charge in the floating gate is changed to change the threshold value of the cell transistor.

Here, a general EP operating with a 5V power source
The operation of the ROM will be described as an example. The threshold value of the memory cell storing "1" data is about 2V, and "0"
The threshold value of the memory cell storing data is set to 5V or higher.
The word line as the gate of the cell transistor is set to 0V when it is not selected, and is set to 5V of the power supply potential when it is selected. Therefore, in the case of a memory cell storing "0" data, the transistor is in an off state, and thus no current flows even if it is selected. On the other hand, in the case of a memory cell storing data “1”, when selected, the transistor is turned on, and a current flows. The sense amplifier determines the read data by detecting this amount of current.

FIG. 6 shows the relationship between the threshold voltage distribution of the memory cells in the nonvolatile semiconductor memory chip and the word line potential. In the case of the EPROM, the memory cell MC1 storing the data "1" is in an energy stable state because the electric charges are uniformly discharged from the floating gate by the irradiation of ultraviolet rays. Therefore, the distribution of the threshold Vth has very small variation. The range indicated by A1 in the figure is a margin for "1" data. That is, when the threshold value Vth becomes high and the difference from the word line selection level V _WL becomes small, the current decreases and it becomes difficult to discriminate "1" data, so that the access time is delayed.

On the other hand, the range indicated by B1 in the figure is a margin for "0" data. When the threshold value Vth is lowered to, for example, about 0.5 V and the difference from the word line non-selection level is reduced, the subthreshold current increases. Although this current is very small in each cell, it is affected when the total number of unselected cells connected to the same data line increases. Therefore, the read margin of "0" data may be reduced. Therefore, the difference between the selected level and the non-selected level of the word line, that is, the relationship between the magnitude of the power supply voltage and the magnitude of the cell distribution width affects the data detection margin.

Further, in the cell storing "0" data, hot electrons are injected into the floating gate. The hot electrons are injected into the floating gate by applying a high electric field. Therefore, due to various causes, the threshold distribution becomes wider than that of the cell storing "1" data. In FIG. 6, the range indicated by C is a margin for "0" data as in the case of range B1, but since a margin for "1" data is not necessary, the distribution range may be set to a sufficiently high threshold value.
It can be said that the cell storing "0" data has loose restrictions.

Next, consider the case of a flash EEPROM. The data write operation is similar to that of the EPROM. In the data erasing operation, by applying a high potential to the oxide film, a tunnel current is generated and electrons are emitted from the floating gate. Therefore, as in the case of writing data, the threshold distribution of the cells storing “1” data is EPROM as shown in FIG. 7 due to various factors such as the film thickness of the oxide film, the impurity concentration, and the processed shape.
Spreads compared to. Therefore, the margins indicated by A2 and B2 are significantly reduced as compared with the EPROM.

On the other hand, this kind of flash EEPROM
In order to reduce device miniaturization and current consumption, the power supply voltage is becoming lower. In other words, the current mainstream 5.0
There is a tendency to reduce the power supply from V to 3.3V or lower. However, in the case of the flash EEPROM, the lowering of the power supply voltage leads to the lowering of the word line selection level, so that the margins of the ranges A2 and B2 shown in FIG. 7 may be further reduced or may be lost.
Therefore, in order to secure the above-mentioned margin, the flash EEPROM corresponding to the lowering of the power supply voltage requires the word line boosting method for boosting the level of the word line in the read mode to a level higher than the external power supply.

[0009]

FIG. 8 shows an example of a word line drive circuit already proposed. Predecoders PDC1 to PDCn and row decoder RDC
A1 to RDCAM and RDCB1 to RDCBm are power supplies Vcc
Driven by the higher word line level power supply V _WL . The predecoders PDC1 to PDCn output predecode signals P1 to Pn according to the address signal Add. The row decoders RDCA1 to RDCAm output the selection signals SEL and / SEL having a level higher than the power supply Vcc according to the address signal Add. Row decoder RDCB1
~ RDCBm outputs the predecode signals P1 to Pn according to the selection signals SEL and / SEL to word lines WL1 to WL.
output to n. The predecoders PDC1 to PDCn are arranged in a so-called peripheral circuit located around the integrated circuit chip, and the row decoders RDCA and RDCB are arranged near the memory cell array.

By the way, as shown in FIG. 8, an unillustrated N-type well region or source of a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) is charged to a boosted word line level power supply V _WL . There is a need. As described above, the row decoders RDCA1 to RDCAm,
RDCB1 to RDCBm exist corresponding to the number of word lines, and their layout occupies a large area along the memory cell array. Of these, the area of the N-type well region occupies about half the area of the circuit portion composed of CMOS in the peripheral circuit. Therefore, the parasitic capacitance of the well region is
It is estimated to have a large capacity on the order of nF. In order to boost the large capacity in a time that does not affect the reading of data, it is necessary to boost the large capacity before the word line is selected after the chip becomes active. Assuming that the time required for this boosting is 10 ns and that the 3.3 V power supply voltage is boosted to 5.0 V within this time, 1 nF will be boosted by 1.7 V in 10 ns.
The charging current is (1 nF × 1.7 V) / 10 ns = 170 mA. Therefore, this charging current becomes much larger than the operating current and cannot be realized. Therefore, in order not to delay access after the chip becomes active, charging of the well region is started at the same time when power is turned on, and the well region is set to the boosted potential before the chip becomes active, that is, in the standby state. It is necessary to charge it.

On the other hand, the potential of the word line needs to be accurately boosted. That is, when the boosted word line potential is low, the current flowing through the selected cell transistor decreases, and the access speed decreases. On the contrary, when the boosted potential is high, there occurs a problem that the data retention characteristic is deteriorated by the electric field stress due to the gate potential.

9 and 10 show an example of controlling the boosted voltage with high accuracy. In FIG. 9, the output terminal of the booster circuit 11 is connected to a predetermined potential (not shown) via the diode 12. The diode 12 clips the output voltage of the booster circuit 11 so that the boosted voltage V _WL does not rise above a predetermined voltage.

In FIG. 10, the output terminal of the booster circuit 11 is connected to the gate and drain of the transistor 13. The source of the transistor 13 is connected to a predetermined potential (not shown) via the resistor 14, and is also connected to the non-inverting input terminal of the differential amplifier 15. The reference voltage Vref is supplied to the inverting input terminal of the differential amplifier 15, and the output terminal is connected to the control signal input terminal of the booster circuit 11. The differential amplifier 15 detects the output voltage of the booster circuit 11 detected by the transistor 13 and the resistor 14 and the reference voltage Vre.
f is compared, and if the output voltage is higher than the reference voltage Vref, the operation of the booster circuit 11 is stopped.

The circuits shown in FIGS. 9 and 10 can control the boosted voltage with high precision. However, all of these circuits have a leak path and the boosted potential decreases. For this reason, it is necessary to continue boosting at least to compensate for it, and current is consumed during this period.

On the other hand, as described above, since the access is not delayed after the chip becomes active, the current consumption during standby must be suppressed to nA order when the boosted voltage is generated during standby. However, it is difficult to accurately control the boosted voltage with such a current.

As described above, when boosting the word line, the boosted voltage is controlled with high accuracy, and the access is not delayed after the chip is in the active state. Therefore, boosting from the standby state is incompatible. Occurs.

The present invention has been made to solve the above problems, and an object of the present invention is to prevent access delay from occurring after a chip is in an active state.
Moreover, it is intended to provide a semiconductor memory device capable of controlling the potential of the word line with high accuracy.

[0018]

According to the present invention, there is provided a selecting means for selecting a word line according to an address signal, a supplying means for supplying a potential to the word line selected by the selecting means, and First voltage generating means for generating a stabilized first voltage for driving the supply means, and a second voltage higher than the first voltage for driving the selecting means
And a second voltage generating means for generating the voltage.

[0019]

That is, since the second voltage generating means generates the second potential from the standby state, the large capacity load can be quickly charged with the second potential after the chip becomes active. Therefore, access delay does not occur. Moreover, since the first voltage generating means generates the stabilized first voltage in the active state, the potential of the word line can be controlled with high accuracy.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention, and the same parts as those in FIG. 8 are designated by the same reference numerals. The predecoders PDC1 to PDCn include NAND circuits ND1 and ND1, respectively.
It is composed of a level converter LC1 including an inverter circuit IV1 and an inverter circuit IV2. The address signal Add is supplied to the input terminal of the NAND circuit ND1, and the output terminal of the NAND circuit ND1 is supplied to the level converter LC.
1 and the other input terminal of the level converter LC1 via the inverter circuit IV1. The output end of the level converter LC1 is connected to the input end of the inverter circuit IV2, and this inverter circuit I
The predecode signal P1 is output from the output terminal of V2.
A power supply voltage V is applied to each source of the PMOS transistors forming the level converter LC1 and the inverter circuit IV2.
The first boosted voltage V _{WL1 obtained} by boosting cc is supplied.
Level converter LC1 is supplied to the inverter circuit IV2 converts the power supply voltage Vcc level of the signal output from the NAND circuit ND1 to a first boosted voltage V _WL1, inverter circuit IV2 is in accordance with the output signal of the level converter LC1 And outputs the first boosted voltage V _WL1 . Therefore, the levels of the predecode signals P1 to Pn output from these predecoders PDC1 to PDCn are the first boosted voltage V _WL1 .

The row decoders RDCA1 to RDCA
m is a NAND circuit ND2 and an inverter circuit IV, respectively
Level converter LC2 including 3 and inverter circuit IV
4 and IV5. NAND circuit ND2
Of the NAND circuit ND2 is connected to one input terminal of the level converter LC2 and is connected to the other input terminal of the level converter LC2 via the inverter circuit IV3. Has been done.
The output terminal of the level converter LC2 is connected to the input terminal of the inverter circuit IV4, and the output terminal of the inverter circuit IV4 is connected to the input terminal of the inverter circuit IV5. The selection signal SEL is output from the output terminal of the inverter circuit IV5.
1 is output, and the selection signal / SEL1 is output from the input end. The source of each of the PMOS transistors constituting the level converter LC2 and the inverter circuits IV4 and IV5 has a second boosted voltage V obtained by boosting the power supply voltage Vcc.
_WL2 is being supplied. This second boosted voltage V _WL2
Is set higher than the first boosted voltage V _WL1 . The level converter LC2 outputs the power supply voltage Vcc level signal output from the NAND circuit ND2 to the second boosted voltage _VWL2.
Are supplied to the inverter circuit IV4, and the inverter circuits IV4 and IV5 respectively output the second boosted voltage V _WL2 according to the output signal of the level converter LC2. Therefore, the selection signals SEL1 and / SEL1 to SEL1 output from the row decoders RDCA1 to RDCAM are selected.
The levels of m and / SELm become the second boosted voltage V _WL2 .

The row decoders RDCB1 to RDCBm are
Transfer gates TG1 to TGn and N, respectively
It is composed of channel MOS transistors (hereinafter referred to as NMOS transistors) T1 to Tn. One ends of the current paths of the transfer gates TG1 to TGn are connected to the output terminals of the predecoders PDC1 to PDCn, respectively, and the other ends of the current paths are the transistors T1.
To Tn are connected to a predetermined potential.
N constituting the transfer gates TG1 to TGn
Each gate of the MOS transistor has the inverter circuit I
The transfer gate TG1 is connected to the output terminal of V5.
The gates of the PMOS transistors forming the transistors TGn to TGn and the gates of the NMOS transistors T1 to Tn are connected to the input terminal of the inverter circuit IV5. The second boosted voltage V _WL2 is supplied to each back gate (N-type well region) of these PMOS transistors. The connection points of the transfer gates TG1 to TGn and the NMOS transistors T1 to Tn forming the row decoders RDCB1 to RDCBm are word lines WL1 to W1.
Each of them is connected to Ln × m. The transfer gates TG1 to TGn have the predecoders PDC1 to PDC.
The predecode signals P1 to Pn output from DCn are transferred. Therefore, the level of each word line WL1 to WLn × m becomes the first boosted voltage V _WL1 .

FIG. 2 shows a booster circuit 21 for generating the second boosted voltage V _WL2 . The booster circuit 21 includes an oscillating unit OSC and a boosting unit BT. The oscillator unit OSC includes an inverter circuit 21a and a NAND circuit 21.
b, inverter circuits 21c to 21f. The boost control signal CS is supplied to the input terminal of the inverter circuit 21a. The output terminal of the inverter circuit 21a is connected to one input terminal of the NAND circuit 21b. The output terminal of the NAND circuit 21b is connected through the inverter circuits 21c to 21f connected in series to the NAND circuit 21b.
Is connected to the other input end of.

The booster BT includes NMOS transistors 21g to 21i and a capacitor 21 whose threshold voltage is set to 0V.
j and 21k. The current paths of the transistors 21g to 21i are connected in series, and the drain and gate of the transistor 21g are connected to the power supply Vcc. The drain and gate of the transistor 21h are connected to the output terminal of the inverter circuit 21c via the capacitor 21j, and the transistor 2h
The drain and gate of 1i are connected to the output terminal of the inverter circuit 21d via the capacitor 21k.

In the above structure, the oscillating section OSC has a low level boosting control signal C at the input terminal of the inverter circuit 21a.
When S is supplied, oscillation starts. The booster BT boosts the power supply voltage Vcc in accordance with the oscillation operation of the oscillator OSC to generate the second boosted voltage _VWL2 .

The boost level control is set by changing the sizes of the NMOS transistors 21g to 21i and the capacitors 21j and 21k. 3 and 4 show
3 shows a circuit for generating a first boosted voltage V _WL1 . In FIGS. 3 and 4, the same parts as those in FIG. 2 are designated by the same reference numerals. In FIG. 3, the output terminal of the booster circuit 21 is connected to a predetermined potential (not shown) via a diode 22.
The diode 22 clips the output voltage of the booster circuit 21 so that the first boosted voltage V _WL1 does not rise above a predetermined voltage.

In FIG. 4, the output terminal of the booster circuit 21 is connected to the gate and drain of the transistor 32. The source of the transistor 23 is connected to a predetermined potential (not shown) via the resistor 24, and is also connected to the non-inverting input terminal of the differential amplifier 25. The inverting input terminal of the differential amplifier 25 is supplied with the reference voltage Vref, and the output terminal thereof is the inverter circuit 21a constituting the booster circuit 21.
Is connected to the input end of. The differential amplifier 25 compares the output voltage of the booster circuit 21 detected by the transistor 23 and the resistor 24 with the reference voltage Vref, and when the output voltage is higher than the reference voltage Vref, the high level booster control signal C.
S is generated and the operation of the booster circuit 21 is stopped.

FIG. 5 shows the operation of FIGS. 1 to 4. The booster circuit 21 shown in FIG. 2 generates the second boosted voltage V _WL2 when the semiconductor chip is in the standby state. Further, the booster circuit 21 shown in FIGS. 3 and 4 has the power supply voltage V after the chip enable signal / CE becomes active.
Boost cc, and further diode 22 and transistor 2
3. Stabilize the voltage boosted by using the differential amplifier 25 and output the first boosted voltage _VWL1 .

Here, the first and second boosted voltages V
The relationship between the potentials of _WL1 and V _WL2 will be described. When the second boosted voltage V _WL2 becomes lower than the first boosted voltage V _WL1 ,
PMOSs that form the transfer gates TG1 to TGn to which the selected predecode signals P1 to Pn are supplied
The potential of the well region of the transistor is the source potential (V
_It becomes lower than _WL1 ) and the PN junction is forward-biased, so that leakage current occurs. Further, when the gate potential of the transfer gates TG1 to TGn, that is, the signal SEL or / SEL including the second boosted voltage V _WL2 becomes lower than the source potential V _WL1 , PM which should be non-conductive.
Problems such as deterioration of the cut-off characteristic of the OS transistor occur.

On the contrary, when the second boosted voltage V _WL2 becomes higher than the first boosted voltage V _WL1 , the row decoder RDC
B1 to RDCBm transfer gates TG1 to TG
In the PMOS transistor forming n, the potential of the well region (V _WL2 ) becomes higher than the source potential (V _WL1 ), so that the back gate bias effect reduces the current driving capability. However, this effect becomes remarkable when the difference between the first boosted voltage V _WL1 and the second boosted voltage V _WL2 is large, and if the difference is small, the driving force decrease can be corrected by the transistor size. Is. Therefore, it does not matter if the second boosted voltage V _WL2 is higher than the first boosted voltage V _WL1 .

As described above, the first boosted voltage V _WL1 transferred to the word line needs to be supplied with a boosted potential accurately controlled to a desired potential, but the second boosted voltage V _WL2 is the first boosted voltage V _WL2 . it is sufficient so as not to be lower than the boosted voltage V _WL1, no precision such as the first boosted voltage V _WL1 is required.

Next, the first and second boosted voltages V _WL1 , V
Consider the load capacity of _WL2 . The second boosted voltage V _WL2 is applied to the row decoders RDCA1 to RDCAM, RDCB1 to RD.
The large load capacitance of the N well provided with CBm is driven. On the other hand, the first boosted voltage V _WL1 is applied to the N well and the P well which form the predecoders PDC1 to PDCn.
The source of the MOS transistor is charged. The predecoders PDC1 to PDCn are peripheral circuits, and in the case shown in FIG. 1, there are n predecoders, and the area of each N well is one of the row decoders RDCA1 to RDCAM and RDCB1 to RDCB.
It is extremely small compared to the area of m. Therefore, it can be said that the load capacitance of the first boosted voltage V _WL1 is significantly smaller than the load capacitance of the second boosted voltage V _WL2 .

From the above, it is necessary to improve the accuracy of the boost level.
Since the boosted voltage V _WL1 of drives a small load capacitance,
Even if boosting is started after the chip becomes active, boosting can be done in a time that does not affect access. Further, since boosting is started after the chip becomes active, there is no problem even if a leak current occurs. Therefore, the boosted voltage can be accurately controlled by the circuits shown in FIGS.

On the other hand, the second boosted voltage V _WL2 that drives a large load capacitance needs to be boosted from the standby state, but the boosted voltage is controlled with high accuracy like the first boosted voltage V _WL1. No need. Therefore, the boosted voltage can be generated by using the booster circuit as shown in FIG. Moreover, in the case of this circuit, since there is no leak path, no leak current is generated.

As described above, since the potential of the word line can be controlled with high accuracy, the margin for detecting the "1" data and the margin for detecting the "0" data are not impaired, and particularly the flash It is possible to reduce the voltage of the EEPROM. The present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the spirit of the invention.

[0036]

As described above in detail, according to the present invention, the access delay does not occur after the chip enters the active state, and the leak current is suppressed to control the potential of the word line with high accuracy. It is possible to provide a semiconductor memory device capable of performing the above.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a booster circuit applied to the present invention.

FIG. 3 is a circuit diagram showing an example of a booster circuit applied to the present invention.

FIG. 4 is a circuit diagram showing an example of a booster circuit applied to the present invention.

5 is a timing chart shown to explain the operation of FIG. 1. FIG.

FIG. 6 is a diagram for explaining a threshold distribution of EPROM.

FIG. 7 is a diagram shown for explaining a threshold distribution of a flash EEPROM.

FIG. 8 is a circuit configuration diagram showing an example of a word line drive circuit applied to a conventional semiconductor memory device.

FIG. 9 is a configuration diagram showing a conventional booster circuit.

FIG. 10 is a configuration diagram showing a conventional booster circuit.

[Explanation of symbols]

PDC1 to PDCn ... Predecoder, RDCA1 to RD
CAm, RDCB1 to RDCBm ... Row decoder, V
_WL1 ... First boosted voltage, V _WL2 ... Second boosted voltage, WL
1, WL2 to WLn ... Word line, 21 ... Booster circuit, OS
C ... Oscillator, BT ... Booster, / CE ... Chip enable signal.

Claims (3)

[Claims] 1. A selecting means for selecting a word line according to an address signal, a supplying means for supplying a potential to the word line selected by the selecting means, and a stabilizing means for driving the supplying means. A first voltage generating means for generating the generated first voltage, and a second voltage generating means for generating a second voltage higher than the first voltage for driving the selecting means. A semiconductor memory device characterized by: 2. The supply means is a predecoder having a small-capacity load for supplying a potential to a word line selected in response to an address signal, and the selection means is a large decoder selecting a word line in response to an address signal. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a row decoder having a capacitive load. 3. The first voltage generating means generates the first voltage in an active state, and the second voltage generating means generates the second voltage from a standby state. Item 2. The semiconductor memory device according to item 1.