JP4071572B2 - Voltage control circuit and semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention generally relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device including a voltage control circuit that controls a high voltage generated inside.
[Prior art]
In a nonvolatile semiconductor memory device, data is written by a program operation for injecting charges into the gate of the memory cell transistor, and data is erased by an erase operation for removing charge from the gate of the memory cell transistor. This program operation and erase operation are executed by applying a predetermined voltage corresponding to each operation to the gate, drain and source terminals of the memory cell transistor. In order to inject charges into the gate or to extract charges from the gate, generally a voltage higher than an external power supply voltage supplied from the outside of the nonvolatile semiconductor memory device is required. It is generated by boosting the external power supply voltage by an internal high voltage generation circuit.
[0002]
When the boosted voltage generated by the high voltage generation circuit consumes current along with the erase operation or program operation in the memory cell array circuit, the potential drops due to the influence of current consumption. Therefore, it is necessary to monitor the boosted voltage to check whether a predetermined potential is maintained at any time. A high voltage control circuit (high voltage regulator) is used for this purpose.
[0003]
Some high voltage control circuits use a capacitance dividing circuit for high voltage control. FIG. 1 is a circuit diagram showing an example of a high voltage control circuit including a capacitance dividing circuit.
[0004]
The high voltage control circuit of FIG. 1 includes a PMOS transistor 10, NMOS transistors 11 to 15, a P well capacitor 16, N well capacitors 17 and 18, and a comparison circuit 19. In FIG. 1, circuit elements surrounded by dotted circles are circuit elements for high voltage.
[0005]
In the circuit of FIG. 1, the boosted potential Vpp is capacitively divided to generate a divided potential Vdiv, and this potential Vdiv is input to the comparison circuit 19. The comparison circuit 19 operates when the enable signal ENB is asserted, and compares the input potential with the reference potential Vref. When the input potential is higher than the reference potential Vref, the output Vcomp becomes, for example, HIGH, and the boosted potential is too high, so that control is performed to lower the voltage by the discharge operation.
[0006]
The NMOS transistor 15 is used to adjust the ratio of the divided potential Vdiv to the boosted potential Vpp by changing the ratio of the P-well capacitor 16 and the N-well capacitors 17 and 18 according to the HIGH / LOW of the signal Vtrim. The Also, the NMOS transistors 12 and 14 are turned on when the OFF signal OFFN becomes HIGH before and after the voltage control operation starts, and initialize the charge accumulated in the capacitor to a specific threshold value (to VSS in the example of FIG. 1). belongs to.
[Problems to be solved by the invention]
The circuit of FIG. 1 is designed so that, for example, the divided potential Vdiv when the boosted potential Vpp is 3.6 V is close to 1.3 V, which is the sense target potential of the comparison circuit 19. In this case, when the boosted potential Vpp increases to 20V in the high voltage mode, the divided potential Vdiv increases to about 7V.
[0007]
Low voltage NMOS transistors are used for the NMOS transistor 15 of the capacitance dividing circuit and the Vdiv input gate of the comparison circuit 19. As the technology has evolved in recent years, the gate breakdown voltage of transistors has been lowered, and can only withstand, for example, about 3.6V. Therefore, gate breakdown occurs under the condition that the division potential Vdiv is about 7V.
[0008]
Although it is conceivable to use a high voltage transistor for these portions, problems such as an increase in threshold variation due to the process, a decrease in current capability, and an increase in area occur.
[0009]
In view of the above, an object of the present invention is to provide a voltage control circuit having a function of suppressing a voltage increase of a divided potential in a capacitance dividing circuit. It is another object of the present invention to provide a semiconductor memory device provided with such a voltage control circuit.
[Means for Solving the Problems]
A voltage control circuit according to the present invention includes a capacitance dividing circuit that generates a second potential at a second terminal by capacitively dividing a first potential received at a first terminal, the first terminal, and the second terminal. And an NMOS transistor provided with an upper limit on the second potential when the first potential rises by the action of the source potential always lower than the gate potential by a threshold value.
[0010]
In the voltage control circuit, an NMOS transistor is provided on the high voltage side of the divided potential (second potential). By applying an appropriate potential to the gate of the NMOS transistor, the target sense voltage of the comparison circuit that receives the divided potential is sufficiently passed, and the divided potential does not exceed the input gate breakdown voltage of the trim transistor or the comparison circuit. It becomes possible to control. Therefore, it is possible to perform an appropriate monitoring operation in the low voltage mode where the first potential is low, and to avoid destroying the circuit element in the high voltage mode where the second potential is high.
[0011]
A semiconductor memory device according to the present invention includes a memory cell array including nonvolatile memory cells, a decoder circuit that controls the memory cell array, a first potential based on an external potential, and the decoder circuit and the memory cell array. A high voltage generation circuit for supplying a first potential; and a voltage control circuit for controlling the first potential generated by the high voltage generation circuit, wherein the voltage control circuit receives the first voltage at a first terminal. A capacitor dividing circuit that generates a second potential at the second terminal by capacitively dividing the potential of the second potential, and the second potential as an input for controlling the first potential. A comparison circuit for comparing potentials, and an NMOS transistor provided between the first terminal and the second terminal and configured to set an upper limit on the second potential when the first potential rises It is characterized by.
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0012]
FIG. 2 is a block diagram showing a schematic configuration of the nonvolatile semiconductor memory device according to the present invention.
[0013]
The nonvolatile semiconductor memory device 20 of FIG. 5 includes a control circuit 21, a command register 22, an I / O control circuit 23, an address register 24, a status register 25, a memory cell array 26, a row address decoder 27, a row address buffer 28, and a column decoder. 29, a data register 30, a sense amplifier 31, a column address buffer 32, a high voltage generation circuit 33, a logic control 34, and a ready / busy register 35.
[0014]
The logic control 34 receives control signals such as chip enable / CE, command latch enable CLE, address latch enable ALE, write enable / WE, read enable / RE, write protect / WP, spare area enable / SE from the outside, and these A logic control signal is supplied to the control circuit 21 based on the control signal.
[0015]
The I / O control circuit 23 exchanges input / output signals I / O0 to I / O7 with the outside. The I / O control circuit 23 receives an address signal, a data signal, and a command signal from the outside, and supplies the address signal to the address register 24, the data signal to the data register 30, and the command signal to the command register 22. The address register 24 supplies the row address to the row address buffer 28 and supplies the column address to the column address buffer 32.
[0016]
The control circuit 21 receives a logic control signal from the logic control 34 and also receives a command from the command register 22, operates as a state machine based on these logic control signal and command, and controls each part of the nonvolatile semiconductor memory device 20. Control the behavior.
[0017]
The control circuit 21 controls the memory cell array 26, the row address decoder 27, the column decoder 29, and the like in order to read data from the address of the memory cell array 26 indicated by the address register 24. In addition, the control circuit 21 controls the memory cell array 26, the row address decoder 27, the column decoder 29, and the like in order to write data to the write address of the memory cell array 26. In addition, the control circuit 21 controls the memory cell array 26, the row address decoder 27, the column decoder 29 and the like in order to erase the designated area of the memory cell array 26 in a predetermined unit.
[0018]
The memory cell array 26 includes an array of memory cell transistors, word lines, bit lines, and the like, and stores data in each memory cell transistor. At the time of data reading, data from the memory cell specified by the activated word line is read to the bit line. At the time of programming or erasing, the word line and the bit line are set to appropriate potentials according to the respective operations, thereby executing the charge injection or charge extraction operation for the memory cells.
[0019]
The sense amplifier 31 operates under the control of the control circuit 21, and the data current supplied from the memory cell array 26 is compared with the reference current according to the designation by the row address decoder 27 and the column decoder 29, so that the data becomes 0. Or 1 is determined. The determination result is stored as read data in the data register 30 and is further supplied from the data register 30 to the I / O control circuit 23.
[0020]
Further, in the verify operation accompanying the program operation and the erase operation, the current of data supplied from the memory cell array 26 in accordance with the designation by the row address decoder 27 and the column decoder 29 is compared with the reference current for program verify and erase verify. Is done. In the program operation, write data is stored in the data register 30, and the status register 25 that executes charge injection to the memory cell by setting the word line and the bit line of the memory cell array 26 to appropriate potentials based on this data. Is a register for storing status information related to the operation of the nonvolatile semiconductor memory device 20, and reading the contents of the register from the outside via the I / O control circuit 23 makes it possible to determine whether the device is in a ready state or a write protection mode. Or whether a program / erase operation is in progress. The ready / busy register 35 stores a flag indicating whether the device is ready or busy, and in response to this, a ready / busy signal is output to the outside. The high voltage generation circuit 33 is a circuit that generates a high potential used for a program operation and an erase operation.
[0021]
FIG. 3 is a block diagram showing the configuration of the high voltage control system.
[0022]
In FIG. 3, a high voltage generation circuit 41, a voltage control circuit 42, and a voltage step-down circuit 43 constitute the high voltage generation circuit 33 in FIG. The boosted potential generated by the high voltage generation circuit 41 is supplied to the row address decoder 27, the memory cell array 26, and the like, and is also supplied to the voltage control circuit 42 and the voltage step-down circuit 43. The voltage control circuit 42 monitors the boosted potential supplied from the high voltage generation circuit 41 and controls the high voltage generation circuit 41 and the voltage step-down circuit 43 so that the boosted potential maintains a predetermined potential. For example, when the boosted potential is higher than a predetermined potential, the voltage step-down circuit 43 is operated to step down the boosted potential by a discharge operation.
[0023]
FIG. 4 is a circuit diagram showing a part of the configuration of the voltage control circuit 42 according to the first embodiment of the present invention.
[0024]
The voltage control circuit of FIG. 4 includes a PMOS transistor 50, NMOS transistors 51 to 55, a P well capacitor 56, N well capacitors 57 and 58, and a comparison circuit 59. In FIG. 4, circuit elements surrounded by dotted circles are high-voltage circuit elements.
[0025]
In the circuit of FIG. 4, the boosted potential Vpp is divided into capacitors to generate a divided potential Vdiv, and this potential Vdiv is input to the comparison circuit 59. The comparison circuit 59 operates when the enable signal ENB is asserted, and compares the input potential with the reference potential Vref. When the input potential is higher than the reference potential Vref, the output Vcomp becomes, for example, HIGH, and the boosted potential is too high, so that control is performed to lower the voltage by the discharge operation.
[0026]
The NMOS transistor 55 is used to adjust the ratio of the divided potential Vdiv to the boosted potential Vpp by changing the ratio of the P well capacitor 56 and the N well capacitors 57 and 58 in accordance with the HIGH / LOW of the signal Vtrim. The The NMOS transistors 52 and 54 are turned on when the OFF signal OFFN becomes HIGH before and after the start of the voltage control operation, and initialize the charge amount stored in the capacitor to a specific value (in the example of FIG. 4 to VSS). Is for.
[0027]
FIG. 5 is a circuit diagram showing an example of the configuration of the comparison circuit 59.
[0028]
The comparison circuit 59 in FIG. 5 includes PMOS transistors 61 to 63 and NMOS transistors 64 to 67. The NMOS transistor 64 is an input transistor that receives the divided potential Vdiv of FIG. In this configuration, when the divided potential Vdiv is higher than the reference potential Vref, the output potential Vcomp becomes HIGH by the differential amplification operation.
[0029]
Referring again to FIG. 4, the NMOS transistor 53 is a high breakdown voltage / low threshold transistor that is inserted between the P-well capacitor 56 of the capacitance dividing circuit and the output Vdiv and receives Vdd as a gate voltage. By setting the gate voltage Vdd to an appropriate value, the target sense voltage 1.3V of the comparison circuit 59 is sufficiently passed, and the trimming transistor 55 and the input gate breakdown voltage 3.6V of the comparison circuit 59 are divided by the divided potential Vdiv. Control so that does not exceed. For example, the gate voltage Vdd is set to a constant voltage of 2.5 V when the circuit is used.
[0030]
With this setting, when the boosted potential Vpp is 3.6 V in the low voltage mode, an appropriate sense potential can be supplied to the comparison circuit 59 to surely realize the monitoring function. Even when the boosted potential Vpp rises to 20 V in the high voltage mode, the divided potential Vdiv only rises to “Vdd−threshold”. Accordingly, the NMOS transistor 55 and the input transistor of the comparison circuit 59 are protected. Even when the NMOS transistor 53 is inserted, the amount of charge charged between the P-well capacitor 56 and the N-well capacitor 57 (and 58) does not change as compared with the non-inserted state. Even when the voltage drops to 3.6 V, the monitoring function can be accurately performed. Furthermore, for the N-well capacitor 57, a low-voltage capacitor formed of a thin film can be used, so that the area can be greatly reduced.
[0031]
As described above, in the present invention, the NMOS transistor 53 is provided on the high voltage side of the divided potential Vdiv, and an appropriate potential is applied to the gate thereof, so that the target sense voltage of the comparison circuit can be sufficiently passed, and trimming can be performed. It is possible to control the input gate breakdown voltage of the transistor or the comparison circuit so that the divided potential Vdiv does not exceed. Therefore, it is possible to perform an appropriate monitoring operation in the low voltage mode and to avoid the circuit element being destroyed in the high voltage mode.
[0032]
FIG. 6 is a circuit diagram showing a part of the configuration of the voltage control circuit 42 according to the second embodiment of the present invention. The configuration of the second embodiment is a voltage control circuit that detects and controls the potential PVPP (= 6 V) of the selected word line in the program mode of the NAND flash memory.
[0033]
The voltage control circuit of FIG. 6 includes NMOS transistors 71 to 74, a P well capacitor 75, N well capacitors 76 and 77, a comparison circuit 78, a level shifter 80, and NMOS transistors 81 and 82. In FIG. 6, the circuit element surrounded by a dotted circle is a circuit element for high voltage.
[0034]
In the circuit of FIG. 6, the boosted potential PVPP is capacitively divided to generate a divided potential Vdiv, and this potential Vdiv is input to the comparison circuit 78. The comparison circuit 78 operates when the enable signal ENB is asserted, and compares the input potential with the reference potential Vref. When the input potential is higher than the reference potential Vref, the output Vcomp becomes, for example, HIGH, and the boosted potential is too high, so that control is performed to lower the voltage by the discharge operation. The comparison circuit 78 may have the same circuit configuration as the comparison circuit 59 shown in FIG.
[0035]
The NMOS transistor 74 is used to adjust the ratio of the divided potential Vdiv to the boosted potential PVPP by changing the ratio of the P well capacitor 75 and the N well capacitors 76 and 77 in accordance with the HIGH / LOW of the signal Vtrim. The For example, when the boosted potential PVPP is 6V, the divided potential Vdiv is configured to be about 1.3V.
[0036]
The NMOS transistors 72 and 73 are turned on when the OFF signal OFFN becomes HIGH before and after the start of the voltage control operation, and initialize the charge amount accumulated in the capacitor to a specific value (here, VSS). is there.
[0037]
In the configuration of the second embodiment of FIG. 6, NMOS transistors 81 and 82 are inserted between the boosted potential PVPP for the selected word line and the high voltage P-well capacitor 75. The NMOS transistor 81 is a high breakdown voltage / low threshold transistor whose gate input is the unselected word line voltage EVPP, and the NMOS transistor 82 is a high breakdown voltage / low threshold transistor whose gate input is the output of the level shifter 80.
[0038]
FIG. 7 is a circuit diagram showing an example of the circuit configuration of the level shifter 80. The level shifter 80 in FIG. 7 includes PMOS transistors 91 and 92, NMOS transistors 93 to 96, and an inverter 97. When the PHSETUP signal becomes HIGH during the setup operation in the program mode, the NMOS transistor 95 becomes conductive, the PMOS transistor 92 becomes conductive, and the output signal ENDIV becomes HIGH (the same potential as PVPPPLUS). When the PHSETUP signal becomes LOW except during the setup operation, the NMOS transistor 96 becomes conductive, the PMOS transistor 91 becomes conductive, the PMOS transistor 92 becomes nonconductive, and the output signal ENDIV becomes LOW. In this way, the output signal ENDIV is obtained in which the signal level of the PHSETUP signal that indicates the setup operation period is increased to the same potential as PVPPPLUS.
[0039]
This output signal ENDIV is input to the gate of the NMOS transistor 81 in FIG. Here, PVPPPLUS is a potential obtained by adding a potential corresponding to the threshold of the transistor to the selected word line potential PVPP, and is a voltage applied as a gate voltage to a gate transistor for allowing the boosted potential PVPP to pass through in a conventional normal flash memory. It is.
[0040]
Referring again to the voltage control circuit of FIG. 6, during the setup of the program mode, the boosted potential PVPP for the selected word line is 6V, and the boosted potential EVPP for the unselected word lines is 6V. At this time, the NMOS transistor 82 has no difference between the boosted potential EVPP that is the gate potential and the boosted potential PVPP that is the drain potential, and the source potential is lower than the PVPP by the threshold value of the transistor. The original PVPP cannot be passed. On the other hand, the NMOS transistor 81 receives the signal ENDIV having the same signal PHSETUP indicating the setup operation as that of PVPPPLUS (about 9 V) at its gate, and transmits the boosted potential PVPP as it is to the P-well capacitor 75 as a voltage control target. I can do it.
[0041]
During the program operation (including during discharge), the boosted potential PVPP for the selected word line is 20V, and the boosted potential EVPP dedicated to the unselected word is 10V. At this time, PVPPPLUS becomes about 23 V, but the signal ENDIV having the same logic as the PHSETUP signal is turned off, so that the NMOS transistor 81 is not turned on and does not transmit the high voltage PVPP to the P-well capacitor 75. For NMOS transistor 82, since gate voltage EVPP is 10V, the potential transmitted to P well capacitor 75 does not exceed the potential obtained by subtracting the threshold value from 10V. Therefore, in this case, the divided potential Vdiv only rises to about 2.2 V, and each transistor connected to the divided potential Vdiv can be appropriately protected.
[0042]
As described above, in the second embodiment, it is possible to control the selected word line potential PVPP at the time of programming using the PVPP gate drive potential PVPPPLUS and the unselected word line potential EVPP. Since PVPPPLUS and EVPP are signals conventionally used in a normal configuration, it is not necessary to generate a new signal in order to suppress an increase in the divided potential. In the first embodiment, it is necessary to generate a potential of 2.5 V as the gate input signal Vdd of the NMOS transistor 53. However, in the second embodiment, such a special signal is not necessary.
[0043]
As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.
【The invention's effect】
In the present invention, an NMOS transistor is provided on the high voltage side of the divided potential, and an appropriate potential is applied to the gate thereof to sufficiently pass the target sense voltage of the comparison circuit, and the trim transistor and the input of the comparison circuit are input. It becomes possible to control the gate breakdown voltage so that the divided potential does not exceed it. Therefore, it is possible to perform an appropriate monitoring operation in the low voltage mode and to avoid the circuit element being destroyed in the high voltage mode.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an example of a conventional high voltage control circuit including a capacitance dividing circuit.
FIG. 2 is a block diagram showing a schematic configuration of a nonvolatile semiconductor memory device according to the present invention.
FIG. 3 is a block diagram showing a configuration of a high voltage control system.
FIG. 4 is a circuit diagram showing a part of the configuration of the voltage control circuit according to the first embodiment of the present invention;
FIG. 5 is a circuit diagram showing an example of a configuration of a comparison circuit.
FIG. 6 is a circuit diagram showing a part of the configuration of a voltage control circuit according to a second embodiment of the present invention;
FIG. 7 is a circuit diagram illustrating an example of a circuit configuration of a level shifter.
[Explanation of symbols]
20 Nonvolatile Semiconductor Memory Device 21 Control Circuit 22 Command Register 23 I / O Control Circuit 24 Address Register 25 Status Register 26 Memory Cell Array 27 Row Address Decoder 28 Row Address Buffer 29 Column Decoder 30 Data Register 31 Sense Amplifier 32 Column Address Buffer 33 High Voltage generation circuit 34 Logic control 35 Ready / busy register 35

Claims (10)

A capacitance dividing circuit that generates a second potential at the second terminal by capacitively dividing the first potential received at the first terminal;
An NMOS transistor provided between the first terminal and the second terminal and having an upper limit on the second potential when the first potential rises due to the action of the source potential always being lower than the gate potential by a threshold value A voltage control circuit comprising: The circuit further includes a circuit unit that can withstand the input of the second potential up to the input of the third potential, and the second potential does not exceed the third potential when the first potential rises. 2. The voltage control circuit according to claim 1, wherein the gate potential of the NMOS transistor is set. 3. The voltage control circuit according to claim 2, wherein the circuit unit is a comparison circuit that receives the second potential and compares the second potential with a reference potential. The capacitance dividing circuit includes a first capacitor provided on the high voltage side and a second capacitor provided on the low voltage side, and the NMOS transistor is provided between the first capacitor and the second terminal. The voltage control circuit according to claim 1, wherein: The capacitor dividing circuit includes a first capacitor provided on the high voltage side and a second capacitor provided on the low voltage side, and the NMOS transistor is provided between the first capacitor and the first terminal. The voltage control circuit according to claim 1, wherein: A memory cell array including non-volatile memory cells;
A decoder circuit for controlling the memory cell array;
A high voltage generation circuit that generates a first potential based on an external potential and supplies the first potential to the decoder circuit and the memory cell array;
A voltage control circuit for controlling the first potential generated by the high voltage generation circuit;
A capacitance dividing circuit for generating a second potential at the second terminal by capacitively dividing the first potential received at the first terminal;
A comparison circuit that takes the second potential as an input and compares the second potential with a reference potential for controlling the first potential;
A semiconductor memory device comprising an NMOS transistor provided between the first terminal and the second terminal and configured to set an upper limit on the second potential when the first potential rises. The comparison circuit is configured to withstand the input of a third potential, and the gate of the NMOS transistor is configured so that the second potential does not exceed the third potential when the first potential rises. 7. The semiconductor memory device according to claim 6, wherein a potential is set. The capacitance dividing circuit includes a first capacitor provided on the high voltage side and a second capacitor provided on the low voltage side, and the NMOS transistor is provided between the first capacitor and the second terminal. 7. The semiconductor memory device according to claim 6, wherein: The capacitor dividing circuit includes a first capacitor provided on the high voltage side and a second capacitor provided on the low voltage side, and the NMOS transistor is provided between the first capacitor and the first terminal. 7. The semiconductor memory device according to claim 6, wherein: 7. The semiconductor memory device according to claim 6, wherein the voltage control circuit further includes a circuit for controlling the first potential based on a comparison result of the comparison circuit.

Images