JPH07168867A - Layout wiring processing method - Google Patents

Abstract

PURPOSE:To provide a layout wiring processing method which can shorten the time needed for the wiring connection check in a verifying step of the after-process. CONSTITUTION:This processing method perform the interactive addition, deletion, etc., of wirings in accordance with the layout design of a semiconductor chip. Then the processing method includes a processing step 101 where a macrocell is placed and the wiring is processed on the semiconductor chip based on the logical information received from a prescribed basic information file 1, a wiring information file 2 and a connection information file 3, a processing step 102 where the screen display processing is carried out to show the received processing result of the step 101 on a prescribed display device, and a processing step 103 where the interactive wiring processing is carried out at least to add and delete the wirings and to display a cross section.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout / wiring processing method, and more particularly to a layout / wiring processing method used in a layout design floor plan process of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Generally, work such as placement of macro cells and wiring between macro cells in a layout design process is automatically performed. However, for wiring that cannot be automatically performed due to a limitation of the number of tracks, an interactive type By using the display device system, addition / deletion correction is performed manually. The macro cell referred to here corresponds to a logic which is made up of one or a plurality of transistors which have no wiring and which are individually arranged to have a function by wiring. , A process of connecting these macro cells by wiring. In order to display the macro cell and the wiring of the semiconductor chip on the display device, first, the background information, the wiring information and the connection information are read, and the wiring on the semiconductor chip is displayed as a drawing from the logical information. The work of interactive wiring processing by hand is performed after the above steps are completed.

FIG. 7 is a flow chart showing the interactive wiring processing procedure in the conventional layout wiring processing method. In FIG. 7, first, in step 701, one wiring to be subjected to wiring processing is selected and highlighted on the screen of the display device. Next, step 7
In 02, the next process to be performed is selected. In this case, for the case where the complete wiring is not performed, the additional processing of the wiring is first performed considering the wiring prohibited area, the wiring interval considering the resistance, the avoidance of the loop wiring, and the selection of the shortest distance. , Delete processing or sectional view display processing is selected. Then, in response to the selection result of step 702, wiring addition processing is performed in step 703.
In step 704, wiring deletion processing is executed.
Then, in step 705, it is determined whether or not any one of these wiring processes has been completed. If not completed, the process returns to step 702 to continue the subsequent processes, and if completed, In step 706, the changed wiring data is registered and the wiring process ends.

Generally, a wiring provided on a semiconductor chip has a plurality of hierarchies, and in order to avoid a short circuit with an adjacent wiring during a single wiring work for connecting macro cells, a resistance or the like is added. Considering this, in order to keep the wiring interval between the wirings constant or to avoid the wiring prohibited area, the wiring direction and the layer are repeatedly changed.

Conventionally, the structure on a semiconductor chip displayed on a display device is always displayed as a plan view seen from the upper surface direction (see FIG. 8). Or the difference is shown by changing the pattern. Here, let us consider a portion in the wiring where different layers are connected to each other. Wirings connected at points at which layers between different layers are changed (hereinafter referred to as layer change points, which are shown as layer change points 22 and 22-1 in FIG. 8) are called VIA. It has a role of connecting the layers, and only one layer exists in one layer. As shown in FIG.
The VIA 25 has a connection function between the two layers, corresponding to the lower layer 27. However, when changing layers in the middle of wiring, it is not always necessary to change only one layer, and there are cases where it is necessary to change two or more layers at a time. If two VIAs are generated, if one of the wirings has already generated VIA, how much VIA should be generated only from the top view and in what state VIA is generated. Judgment is extremely difficult. The VIA includes a VIA generated from a wiring and a VIA on a terminal in which a terminal on a macro cell is integrated with the VIA and the terminal itself is the VIA (see FIG. 9B). In FIG. 9B, VIA 25 indicates the VIA coming out of the wiring, and VIA 26 indicates the VIA on the terminal. In the case of the VIA on this terminal, the existence of the terminal itself is the VIA, and therefore it is not necessary to generate the VIA again. However, it is extremely difficult for the designer to understand at a glance that the VIA and the terminal are integrated.

Further, the designer repeats the processes such as the addition / deletion of the wirings many times, and grasps what kind of state the circuit of the corrected portion is at the present time. In order to do so, there is no way but to grasp the design person's expectation from the overlap of colors and patterns in the drawings. Therefore, it is unavoidable to rely on the verification connection check performed in a later process and the repeated wiring correction to determine whether or not the circuit and wiring are surely connected. , The time required for this has risen to the number of man-hours that can be achieved.

[0007]

In the above-described conventional layout and wiring processing method, when performing interactive wiring processing manually, if the conventional planar display method alone is used, the current wiring between different layers is used. There are drawbacks that it is difficult to grasp the connection status, and it is not possible to reliably add or delete wiring.

In addition, in the process of repeating the wiring process, the designer cannot confirm the complete wiring connection at the connecting portion. Since it is not possible to remove the error of (2), it is necessary to execute more checks a plurality of times and repeat the wiring correction, which results in an increase in design man-hours.

[0009]

A layout and wiring processing method according to the present invention is a layout and wiring processing method for interactively adding and deleting wirings in accordance with a layout design of a semiconductor chip. With reference to the logic information output from the wiring information file and the connection information file, the first processing step of performing macrocell placement and wiring processing on a semiconductor chip and the processing result of the first processing step are received, A second processing step for performing screen display processing for displaying the processing result on a predetermined display device, and a third processing for performing interactive wiring processing including at least wiring addition processing, deletion processing, and sectional view display processing. And a step.

As a processing procedure of the interactive wiring processing in the third processing step, a processing step of selecting a wiring to be the target of the interactive processing and highlighting it on a predetermined display device screen is selected. As a processing content for the wiring, a processing step for selecting any one of wiring processing of addition processing, deletion processing, and sectional view display processing, and wiring processing selected from the addition processing, deletion processing, and sectional view display processing. The processing step to be performed and whether or not the selected wiring process has been completed are determined. If the wiring process has not been completed, the wiring to be subjected to the interactive process is selected and a predetermined display device is displayed. Return to the process step that highlights on the screen,
When completed, the method may have a processing step of shifting to the next processing step, and a processing step of registering the changed wiring data through the series of processing steps. As the processing procedure in the display processing, a processing step of opening a subwindow on the display device to display the connection portion of the target wiring, and a connection portion to be displayed in the main window on the display device A processing step of designating a range, a processing step of clicking one point of a rectangle in the designated range with a mouse, a processing step of clicking a symmetrical point of one point of the rectangle with a mouse, and a Redraw of the opened subwindow. Then, a processing step for displaying a cross-sectional view of the connection portion within the specified range in the sub window Tsu and up, may be characterized by having a.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a flow chart showing a processing procedure in an embodiment of the present invention. First, in step 101, the background information, the wiring information, and the connection information are read from the background information file 1, the wiring information file 2, and the connection information file 3, respectively, and the macro cell arrangement on the semiconductor chip and the layout information are read from these information. Wiring processing is performed, and in step 102, processing for receiving the processing result of step 101 and displaying the processing result on a predetermined display device is performed. Next, in step 103, an interactive wiring process is performed, and the present invention relates to improvement of this interactive wiring process.

FIG. 2 is a flow chart showing the interactive wiring processing procedure in the embodiment of the present invention. In FIG. 2, first, in step 201, one wiring to be subjected to wiring processing is selected and highlighted on the screen of the display device. Next, in step 202, the process to be performed next is selected. In this case, targeting those where complete wiring has not been done, first the wiring prohibited area, the wiring interval considering the resistance, the avoidance of loop wiring,
In consideration of the selection of the shortest distance and the like, additional processing of wiring,
Either delete processing or sectional view display processing is selected. Then, in response to the selection result of step 202, step 2
In step 03, wiring is added, and step 204 is performed.
In step 205, a wiring deletion process is executed, and in step 205, a sectional view display process is executed. And step 206
Then, it is judged whether or not any one of these wiring processes is completed, and if it is not completed yet, step 20
After returning to step 2, the subsequent processing is continued, and when the processing is finished, in step 207, the changed wiring data is registered and the wiring processing is finished. As is clear from the comparison with the conventional processing procedure shown in FIG. 9, the characteristic feature of the present invention is that the cross-sectional view display processing in step 205 is added to the interactive wiring processing procedure. It is in. Note that FIG. 3 is a flow chart showing a processing procedure of the cross-sectional view display processing in one embodiment of the present invention.

Referring to the first embodiment of the main window 4 and the subwindow 12 in the LSI chip shown in FIGS. 4A and 4B, the processing procedure of the sectional view display processing of FIG. 3 will be described below. explain. First, in step 301, one wiring to be subjected to wiring processing is selected and highlighted on the display device screen. Next, in step 302, the sub-window 12 for displaying the connection part of the wiring is opened (FIG. 4A).
And (b)). In step 303, the display area 7 of the connection section to be displayed is specified in the main window 4 on the screen of the display device (see FIG. 4A). Next, in step 304, one point of the rectangle is clicked with the mouse in the range of the display area to be designated, and in step 305, the rectangular display area is designated by clicking the symmetrical point of the rectangle again (see FIG. Display area 7, sub-window 5 in a)
And macrocell 9). Next, in step 306, the sub-window 12 opened in step 302 is redrawn to display a cross-sectional view of the connection portion within the designated display area in the sub-window 12 shown in FIG. 4B. And
In step 307, R in step 306
Judge whether all the processing of edraw has ended,
If it has not ended yet, the process returns to step 303 to continue the subsequent processes, and if the process has ended, at step 308 the subwindow 1 concerned.
2 is closed and the cross-section display processing ends. In this case, by using Redraw in step 306, it becomes possible to display a cross-sectional view of the connection portion within the specified range in the sub window, and also regarding the result of operating the addition processing and the deletion processing in the main window, Each time the window is readraw, the result is displayed.

For example, the main window 4 in FIG. 4 (a)
It is assumed that the wiring 11 in is the second wiring layer. In FIGS. 4A and 4B, as far as the main window 4 is viewed, it can be seen that the VIAs 6 and 13 connecting different layers exist between the third layer and the second layer. But in fact, under this VIA, another V
Since the IA 14 exists, it is difficult to grasp at a glance whether or not the terminal is completely connected to the terminal. As a method of confirming this, the third layer wiring 11, the VIA 13
The only way is to delete all the second layer wirings 10 and confirm that the VIA 14 connecting the second layer wirings 10 from the terminal is generated. Here, by displaying a cross-sectional view on the sub-window 12 shown in FIG. 4B, there is a VIA connecting the second layer and the third layer under the third layer wiring 11, It is possible to easily confirm that the layers from to the third layer are completely connected. As described above, by reducing the number of operations of one wiring, the number of operations of the entire interactive process is also reduced as a result. Further, the contents of the wiring process performed at this stage are checked in a verification connection check performed in a later process, and if an error occurs at that time, it is necessary to repeat the interactive process again. However, in the present invention, since it is possible to confirm the connection by a single interactive process, it is possible to reduce the number of executions and the required time from the check to the rewiring execution.

Next, a second embodiment of the present invention will be described. In this embodiment, an example is shown in which wiring deletion processing and wiring addition processing are actually performed on the display device. In the example shown in FIG. 4A, FIG. 5A shows the main window 4 when the wiring deletion process is performed by the interactive process, and FIG.
FIG. 5C shows a cross-sectional view of the connection portion in the range designated by the display area 7 in the main window 4 of FIG. Figure 5
In (a), macrocells 9-1 and 9-2 are macrocells to be connected to the picked-up wiring for performing the interactive processing. To connect the wiring to the terminal 5-1, first, the VIA 18 and the macrocell are connected. 9
-1 and 9-2, and the third layer wiring 11 related to the terminals 5-1 and 5-2 are deleted. Next, the VIA 18 connecting the deleted third layer wiring 11 and second layer wiring 10 is deleted (see FIG. 5B). In this case, FIG.
By referring to the subwindow 12 shown in
It is clearly understood that the VIA 19 connecting the second and third layers, which has no meaning on the wiring, remains.
Next, it is necessary to extend the wiring from the VIA 18 to the terminal 5-2 in FIG. 5A. Here, a sub window is opened and the state of the display area 7 is referred to. As shown in FIG. 5C, the terminal H
01 exists at the first layer level, but is connected to the second layer level. This is because the terminal and the VIA are integrated, and the existence of the terminal itself causes the generation of the VIA. Therefore, this VIA is referred to as on-terminal VIA, as described above.

Here, from the VIA 18 to the terminal 5-2.
When extending the wiring to the 3rd layer, the third layer wiring 16 and the terminal 5
It is assumed that the second layer wiring 15 is present between the second line and the second line. In this case, since the crossing of the same layer causes a loop wiring, it must be avoided.
Then, in FIG. 8A, as VIA 18,
The VIA is continuously generated from the third layer to the second layer and from the second layer to the first layer, and the wiring is extended from the tip of the VIA to the terminal 5-2. However, the terminal H01 is
Since it is connected only in the second layer, the terminal 5-
The wiring extended to 2 cannot be connected to the terminal H01. Therefore, it is necessary to delete all the wires that have undergone the addition and deletion processing and return to the starting point. In this case, as shown in FIG. 5C, if it was understood from the beginning that the terminal 5-2 is connected only at the second layer level, the VIA 18 in FIG. Whether the third layer wiring is extended toward the terminal H01 and one VIA connecting the third layer-on-terminal VIA is generated on the terminal H01 (see 18 in FIG. 6B). Or in VIA 18 in FIG. 6A, change the layer to the upper layer,
Wiring can be performed up to the terminal H01 in the fourth layer, and VIA for connecting the fourth layer-third layer and the third layer-second layer can be continuously generated on the terminal.

By displaying the connecting portion in a sectional view as described above, it is possible to reliably perform the wiring connection processing at one time, and eliminate the repetitive wiring processing and the confusion in the design work. can do.

[0019]

As described above, according to the present invention, in order to perform the layout of the semiconductor chip, the connection information, the background information and the wiring information are input, and the layout and wiring processing is performed on the layout, When displaying the wiring processing result on the display device and performing the interactive wiring processing, by displaying the cross-sectional view of the connection part within the specified range, you can grasp the current wiring connection status accurately at a glance. Therefore, there is an effect that a complete interactive process can be executed and the process result can be obtained. In addition, by obtaining a complete processing result in this way, it is possible to reduce the number of verification executions and rewiring executions in subsequent steps, and to significantly reduce the design man-hours of the overall semiconductor chip layout. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a flowchart showing an interactive processing procedure in a layout wiring processing method.

FIG. 2 is a flowchart showing an interactive processing procedure in an embodiment of the present invention.

FIG. 3 is a flowchart showing a procedure for displaying a sectional view of a connecting portion in an embodiment of the present invention.

FIG. 4 is a diagram showing a main window and a subwindow on a display device according to an embodiment of the present invention.

FIG. 5 is a diagram showing a main window when a deletion process is performed in an embodiment of the present invention.

FIG. 6 is a diagram showing a main window when additional processing is performed in an embodiment of the present invention.

FIG. 7 is a flowchart showing an interactive processing procedure in a conventional example.

FIG. 8 is a diagram showing a screen on a display device in a conventional example.

FIG. 9 is a diagram showing a VIA for connecting a wiring layer and an interlayer.

[Explanation of symbols]

 1 Ground Information File 2 Battle Information File 3 Connection Information File 4 Main Window 5, 5-1, 5-2, 21, 21-1 Terminals 6, 13, 14, 18, 19 VIA 7 Display Area 8 Command 9, 9 -1, 9-2, 23 Macro cell 10, 15, 17 Second layer wiring 11, 16 Third layer wiring 12 Subwindow 20, 20-1 wiring 22, 22-1 Layer change point

Claims (3)

[Claims] 1. A layout wiring processing method for interactively adding and deleting wirings corresponding to a layout design of a semiconductor chip, and logical information output from a predetermined ground information file, wiring information file and connection information file. A first processing step of performing macrocell placement and wiring processing on a semiconductor chip and a processing result of the first processing step, and displaying the processing result on a predetermined display device. A layout and wiring process comprising: a second processing step of performing screen display processing; and a third processing step of performing interactive wiring processing including at least wiring addition processing, deletion processing, and sectional view display processing. Method. 2. As a processing procedure of the interactive wiring processing in the third processing step, a processing step of selecting a wiring to be the target of the interactive processing and highlighting it on a predetermined display device screen is selected. As a processing content for wiring, a processing step of selecting any one of wiring processing of addition processing, deletion processing, and sectional view display processing, and wiring processing selected from the addition processing, deletion processing, and sectional view display processing The processing step and whether or not the selected wiring process has been completed, and if the wiring process has not been completed, the wiring that is the target of the interactive process is selected and a predetermined display device screen is displayed. The process returns to the process step highlighted above, and when the process is completed, the process step of moving to the next process step and the series of processes described above are performed. Layout wiring processing method according to claim 1, characterized in that it comprises a processing step of registering the modified wiring data via the step. 3. As a processing procedure in the cross-sectional view display processing, a processing step of opening a subwindow on a display device to display a connection portion of a target wiring, and a main window on the display device, A processing step of designating a range of the connection portion to be displayed, a processing step of clicking one point of a rectangle in the designated range with a mouse, a processing step of clicking a symmetric point of the rectangle with the mouse 2. The layout and wiring processing method according to claim 1, further comprising the step of: redrawing the created sub-window and displaying a cross-sectional view of the connection portion within the specified range in the sub-window. .