JPH07168699A - Squaring circuit - Google Patents

Abstract

PURPOSE:To constitution the squaring circuit which performs squaring arithmetic without being made large in circuit scale so much. CONSTITUTION:A number 1 to be squared is divided into four codes X33, X24, X15, and X06 by a Booth encoding means 2 and outputted. One code consists of three bits, the 3rd bit shows the absolute value of the code, and when the value is 1, the code is minus. Further, the remaining two bits show the absolute value of the code and are assigned to a 2<1> bit and a 2<0> bit respectively. Those codes are inputted to a partial square product generating means 7 and a partial product generating means 8 respectively. The outputs of the partial square product generating means 7 and partial product generating means 8 are inputted to a partial square product and partial product adding means 19 and added until the addition results 2 and 21 of the two output signal addition results 1 and 20 are obtained. The addition results 2 and 21 of the addition results 1 and 20 are inputted to a two-input adding means 22, whose output is outputted as a square product 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a squaring circuit used for error detection in digital signal processing, for example.

[0002]

2. Description of the Related Art Conventionally, there has been a method of performing a square operation by giving the same number to a multiplier and a multiplicand in a 2-input multiplication circuit.

[0003]

However, when only the square operation is intended, the number of input signals may be one, but since the wiring of the multiplier and the multiplicand is required, the wiring is doubled. There is a problem that the circuit becomes redundant and the circuit scale becomes large because the same signal is input as necessary.

The present invention eliminates the above-mentioned problems, codes the multiplicand using the Booth algorithm, divides the multiplicand into a plurality of parts, generates partial square products and partial products, and adds the means. It is an object of the present invention to provide a squaring circuit that performs squaring operation in a smaller circuit by adding in.

[0005]

In the squaring circuit according to the first aspect of the present invention, in the Booth coding means, the multiplicand is 2
The code signal is converted according to the following Booth algorithm and
The multiplier is divided into M parts, which are input to the partial square product generating means and the partial product generating means, and the M partial square products obtained from the respective divided parts are multiplied by parts of different combinations. The partial square product / partial product adding means adds the obtained _M C ₂ partial products until two signals are obtained, and the outputs are added by the two-input adding means to obtain a square product. Is.

Further, in the squaring circuit according to a second aspect of the present invention, the output of the Booth encoding means is squared in the partial square product generating / adding means from the one with a lower digit and at the same time the shift cumulative addition is performed. In the partial product generating / adding means, the output of the Booth encoding means is used to multiply parts having different combinations from the one having a lower digit, and the partial products obtained are subjected to shift cumulative addition to obtain a sum of partial square products. The total sum of partial products is independently obtained, and the outputs of the respective means are added by the 2-input addition means to obtain a squared product.

[0007]

According to the squaring circuit according to the first aspect of the present invention, the multiplicand is coded by utilizing Booth coding, the multiplicand is divided into M parts, and M partial square products are obtained. By generating and adding _M C ₂ partial products, the number of bits required for addition can be suppressed, and the number of full adders / half adders can be reduced as compared with the case of a 2-input multiplier. As a result, it is possible to construct a squaring circuit that performs squaring without increasing the circuit scale so much.

According to the squaring circuit of the second aspect,
It is possible to further reduce the number of addition circuits by performing the partial square product and the shift cumulative addition of the partial products from the lower digit.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the squaring circuit of the present invention will be described by taking the case of 8 bits as an example.

8-bit two's complement representation of multiplicand P
Is expressed by a power of 2, it becomes (Equation 1).

[0011]

[Equation 1]

However, p _i takes a value of 1 or 0. When this P is expressed using the secondary Booth code, it becomes (Equation 2).

[0013]

[Equation 2]

However, X _i = -2P _{2i + 1} + P _2i + P _2i-1
−2 ≦ X _i ≦ 2 (0 ≦ i ≦ 3) When this X _i is used, P ² can be expressed by (Equation 3).

Further, this X _i is represented by a total of 3 bits, 1 bit representing a sign and 2 bits representing an absolute value.

[0016]

[Equation 3]

From (Equation 3), the square of X _i (partial square product)
It will be understood that the product (partial product) of X _i different from is obtained, and the product is shifted according to the power of 2 and added.

Since the partial square product X _i ² is a square, it can be generated with 2 bits representing the absolute value, ignoring the sign bit. X _i ² takes one of three values 0, 1, 4.

Partial product X _i X _j (0 ≦ i, j ≦ 3, i ≠ j)
Takes a sign that represents positive if the two sign bits have the same value, and represents negative if they differ. However, if either of the absolute value portions is 0, a positive sign is used. Further, the part representing the absolute value takes 1 out of the values of 0, 1, 2, 4.

The processing for the power of 2 in (Equation 3) is performed by left shift. That is, X ₁ ² is 12 bits and X ₁ X ₀ is 3 bits.

As a result of addition and subtraction of the partial square product and partial product described above, the square product of P can be obtained. Next, the square circuit according to the first aspect of the present invention will be described in detail with reference to the drawings with the case of 8 bits as the first embodiment.

FIG. 1 shows a block diagram of the squaring circuit of the first embodiment. The multiplicand 1 is divided by the Booth coding means 2 into four codes X ₃ 3, X ₂ 4, X ₁ 5, and X ₀ 6 and output. One code is composed of 3 bits, and the third bit represents the code, and when the value is 1, it represents a negative sign. In addition, the remaining 2 bits represent the absolute value of the code, each of which is 2
¹ bit is allocated to the 2 ⁰ bit.

That is, if the combination of 2 bits is (1,0), it is 2, if it is (0,1), it is 1, and if it is (0,0), it is 0.
Also, (1,1) is not used.

The four code names are the same as the symbols of (Equation 3). These codes are input to the partial square product generating means 7 and the partial product generating means 8, respectively.

The partial square product generating means 7 has the configuration shown in FIG. 2, and the partial square product generating means 7 corresponds to the four symbols 3 to 6 one by one.
Each of the partial square product circuits has a cross product circuit 101-104, and the partial square products X ₃ ² 9, X ₂ ² 10, X ₁ ²
11, X ₀ ² 12 is generated.

The partial square product circuit has the configuration shown in FIG.
Of the input Booth code 110, the second code 2 ¹ bit 11 is used without using the third code bit 111.
2 and 1 bit of the 2 ⁰ bit 113 is used.

[0027] 2 ¹ bit 112 buffer 114,2 ⁰ bit 113 is input to the buffer 116. 2 ¹ bit 112 2 ² next be square in the case of 1, the signal output from the buffer 114 constitutes the second bit part 2 product 118 as 2 ² bits 115. The 2 ⁰ bit 113 becomes 2 ⁰ if the square in the case of 1, the signal output from the buffer 116 constitutes the first bit portion 2 product 118 as 2 ⁰ bit 117.

FIG. 4 shows the structure of the partial product generating means 8. The partial product generating means 8 includes six partial product circuits 201-20.
Consists of six, each _{X 3 X 2 13, X 3} X 1 14, X 3
A partial product of X ₀ 15, X ₂ X ₁ 16, X ₂ X ₀ 17, and X ₁ X ₀ 18 is generated.

FIG. 5 shows the configuration of the partial product circuit. Booth code 1 210 is code bit 1 211, 2 ¹ bit 12
12,2 composed of a ⁰ bit 1 213. Booth code 2 214 is code bit 2 215, 2 ¹ bit 2 2
16,2 composed of a ⁰ bit 2 217.

The product is positive if the two sign bits match, so the resulting sign bit is positive 0, and negative if negative. Therefore, the exclusive OR circuit 2
It is sufficient to input two code bits 211 and 215 to 18. Also, if the absolute value of two Booth codes is 0, the sign is assumed to be positive, so the logical sum of 2 bits representing the respective absolute values is taken, and if the result of either logical sum is 0, It can be set to 0 for positive.

Therefore, 2 ¹ bit 1 212, 2 ⁰ bit 1 213 are input to the OR circuit 220 and 2 ¹ bit 2 21
6,2 ⁰ inputs the bit 2 217 to the OR circuit 219. These outputs and the output of the exclusive OR circuit 218 are input to the logical product circuit 221 to obtain the sign bit 222. The sign bit 222 constitutes the fourth bit of the partial product 229.

Two two¹If both bits are 1, the product
Two²Since the bit becomes 1, the logical product circuit 223 outputs 2¹Bit
To 12 12 and 2¹Enter bit 2 216 and exit
Power is 2 ² Bit 224, 3 bits of partial product 229
Make up the eyes.

The 2 ¹ bit of the product becomes 1 when one of the 2 ¹ bits of the Booth code is 1 and the other 2 ⁰ bit is 1, so 2 ¹ bits 1 212 and 2 ⁰
Bit 2 217,2 ¹ bit 2 216 2 ⁰ bit 1 213, logical product in combination of - OR circuit 22
Enter in 5. The output constitutes the second bit of the partial product 229 as 2 ¹ bits 226.

Two two⁰If both bits are 1, the product
Two⁰Since the bit becomes 1, the logical sum circuit 227 outputs 2⁰Bit
To 1 213, 2⁰Enter bit 2 217 and exit
Power is 2 ⁰ Bit 228, 1 bit of partial product 229
Make up the eyes. Partial square product generating means 7 and partial product generating means
The output of 8 is input to the partial square product / partial product adding means 19.
2 output signals addition result 1 20 addition result 2 21
Will be added until.

FIG. 6 shows the structure of the partial square product / partial product adding means 19. The output X ₃ ² 9 from the partial square product generation means 7,
X ₂ ² 10, X ₁ ² 11 and X ₀ ² 12 are multi-input adder circuits 401.
Entered in.

On the other hand, the output X from the partial product generating means 8₃X₂
13, X₃X₁14, X₃X₀15, X ₂X₁16, X₂X₀1
7, X₁X₀18 from the complement circuits 402 to 407 respectively
Is entered.

In the complement circuits 402-407, when the value of the input sign bit is 1, the remaining 3 bits are bit-inverted and the complement compensation bit is set to 1. Sign bit is 0
In the case of, the remaining 3 bits are output through and the complement compensation bit is set to 0.

The complemented X ₃ X ₂ 40 thus obtained
8, complemented X ₃ X ₁ 410, complemented X ₃ X ₀ 412, complemented X ₂ X ₁ 414, complemented X ₂ X ₀ 416, complemented X ₁ X ₀ 41
8 and complement compensation bits 409, 411, 413, 415,
417 and 419 are input to the multi-input adder circuit 401.
In the multi-input adder circuit 401, the input signal is left-shifted according to the power of 2 in (Equation 3), and the two output signal addition results 1
20 and the addition result 221 are added.

The addition result 1 20 and the addition result 2 21 are 2
It is input to the input addition means 22, and the output thereof is output as a squared product 23.

Next, the square circuit according to the second aspect of the present invention will be described in the case of 8 bits as a second embodiment.

FIG. 7 shows the configuration. The multiplicand 1 has four codes X ₃ 3, X ₂ 4, and X _{1 in the} Booth coding means 2.
5, X ₀ 6, and a partial square product generation / addition means 50
1 and the partial product generation / addition means 502. Each addition result, addition result 1 503 and addition result 2 50
4 is added by the 2-input addition means 505 and output as a squared product 506.

FIG. 8 shows the configuration of the partial square product generation / addition means 501. The four codes X ₃ 3, X ₂ 4, X ₁ 5, and X ₀ 6 are held in registers 601-604, respectively. The stored code is input to the selector 605, and X ₀ 6 to X ₃ 3 are input.
Are sequentially sent to the partial square product circuit 606.

Since the partial square product circuit 606 is exactly the same as that of the embodiment of claim 1, its explanation is omitted. The output of the partial square product circuit 606 is input to the adder circuit 607 and added to the output of the shifter 608. Addition result is register 60
Held at 9.

The output of the register 609 is input to the shifter 608, left-shifted by 4 bits and output. As a result, the addition from the lower digit is realized, and the final addition result is output as the addition result 1 503.

FIG. 9 shows the configuration of the partial product generating / adding means 502. The four codes X ₃ 3, X ₂ 4, X ₁ 5, and X ₀ 6 are held in registers 701 to 704, respectively. The stored code is input to the selectors 705 and 706.

The outputs from the two selectors are (X ₁ ,
X ₀ ), (X ₂ , X ₀ ), (X ₂ , X ₁ ), (X ₃ , X ₀ ),
The partial product circuit 707 is controlled so as to be a combination of (X ₃ , X ₁ ) and (X ₃ , X ₂ ).

The output of the partial product circuit 707 is the complement circuit 708.
To the complemented output 709 and the complement compensation bit 710.
To generate. Since the partial product circuit 707 and the complement circuit 708 are exactly the same as those of the embodiment of claim 1, their description will be omitted.

Complemented output 709 and complement compensation bits 710
Is input to the adder circuit 711 and added to the output of the shifter 712. The addition result is held in the register 713.
The output of the register 713 is input to the shifter 712 and 2
It is output by shifting left according to the power of. As a result, the addition from the lower digit is realized, and the final addition result is output as the addition result 2 504.

In the case of the present embodiment, the number of the partial square product circuits 606 and the partial product circuits 707 may be one each, and since a multi-input adder is not used, the circuit scale is smaller than that of the first embodiment. It is possible to

[0050]

As described above, according to the first aspect of the present invention.
According to the square circuit of, the Booth coding is used to code the multiplicand, divide the multiplicand into M parts, and generate _M partial square products and _M C ₂ partial products. By adding
The number of bits required for addition can be reduced, and the number of full adders / half adders can be reduced as compared with the case of a 2-input multiplier. As a result, it is possible to construct a squaring circuit that performs squaring without increasing the circuit scale so much.

Further, since unnecessary full adders and half adders are reduced, it is possible to perform higher speed calculation.

Further, according to the squaring circuit of the second aspect, the partial squaring product and the partial products are subjected to shift cumulative addition from the lower digit, thereby further reducing the number of the summing circuits from the circuit of the first aspect. You can

[Brief description of drawings]

FIG. 1 is a configuration diagram of a squaring circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a partial square product generating means in the embodiment.

FIG. 3 is a configuration diagram of a partial square circuit in the same embodiment.

FIG. 4 is a block diagram of a partial product generating means in the same embodiment.

FIG. 5 is a configuration diagram of a partial product circuit in the same embodiment.

FIG. 6 is a configuration diagram of a partial square product / partial product adding means in the embodiment.

FIG. 7 is a configuration diagram of a squaring circuit according to a second embodiment of the present invention.

FIG. 8 is a configuration diagram of a partial square product generation / addition unit in the embodiment.

FIG. 9 is a block diagram of a partial product generating / adding means in the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Multiplicand 2 Booth encoding means 7 Partial square product generating means 8 Partial product generating means 19 Partial square product / partial product generating means 22 2 Input adding means 101-104 Partial square product circuit 201-206 Partial product circuit 401 multi-input addition circuit 402-407 complement circuit 501 partial square product generation / addition means 502 partial product generation / addition means 505 2-input addition means 605 selector 606 partial square circuit 607 addition circuit 608 shifters 705, 706 selector 707 partial products Circuit 708 Complement circuit 711 Adder 712 Shifter

Claims (2)

[Claims] 1. A Booth coding means for converting a multiplicand into a code signal according to a quadratic Booth algorithm, and dividing the multiplicand into M parts using the code signal, and the M divided parts into 2 parts. A partial square product generating means for generating M partial square products obtained by multiplication, and _M C ₂ partial products obtained by multiplying different combinations of the divided parts. The partial product generating means, the M partial square products, and the _M C ₂ partial products are added by the partial square product / partial product adding means until two signals are obtained, and the output is added by two inputs. A squaring circuit characterized by obtaining a squared product by addition by means. 2. A Booth coding means for converting a multiplicand into a code signal according to a quadratic Booth algorithm and dividing the multiplicand into M parts using the code signal, and a digit for the M divided parts. From the lowest digit, the partial square product generating / adding means for performing the cumulative cumulative shift, and the different combinations of the M divided portions are multiplied from the lowest digit to obtain a partial product. Partial product generation for shift cumulative addition
A squaring circuit characterized by adding the output of the adding means, the partial square product generating / adding means, and the partial product generating / adding means in a two-input adding means to obtain a square product.