JPH07162976A - Bus type time switch circuit - Google Patents

Abstract

PURPOSE:To provide the bus type time switch circuit high in reliability as for hardware. CONSTITUTION:Concerning the bus type time switch circuit to connect each in-unit channel and each in-unit channel for the unit of a time slot while being distributedly arranged at respective units such as digital private branch exchanges consisting a system of plural units and constituting a channel between respective units in the shape of a bus, this circuit is provided with an output time slot setting means 20 for designating an in-unit time slot to be outputted to the inter-unit channel, data holding means 21 for temporarily holding the PCM data of the in-unit time slot and outputting them to the inter-unit channel, bus monitoring means 22 for monitoring the inter-unit channel and clock input/ output control means 23 for contorlling the inputs/outputs of a frame synchronizing signal to be used at the system and a PCM highway clock signal, and the time slot of the inter-unit channel can be dynamically used in the high-reliability environment corresponding to the traffic of respective units.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is distributed to each unit such as a digital private branch exchange which constitutes a system with a plurality of units, and the communication paths between the units are formed in a bus shape. The present invention relates to a bus type time switch circuit for connecting a communication path between units in time slot units.

[0002]

2. Description of the Related Art FIG. 5 shows a system configuration diagram of a conventional example. As an example, the case of eight units is taken up, and for convenience, the units # 1, # 2, and # 8 are illustrated, and the units # 3 to # 7 are omitted.
In FIG. 5, 1 to 3 are bus type time switch circuits for interconnecting the inter-unit speech path and the intra-unit speech path,
4 to 6 are unit control units that control exchange of each unit,
Reference numeral 7 is a master clock generator that generates a frame synchronization signal and a PCM highway clock signal that must be supplied to the entire system, and 8-10 are mode setting units 11 to 11 that set the bus type time switch circuits 1 to 3 in the clock supply mode. Reference numeral 13 denotes an inter-unit output setting unit that fixedly sets an output time slot for a unit-to-unit speech path for each of the bus type time switch circuits 1 to 3 by hardware. Each unit is multi-drop connected by an inter-unit interface 18 composed of a unit controller inter-communication bus 14, a PCM highway bus 15 which is an inter-unit communication path, a frame synchronization signal bus 16 and a PCM highway clock bus 17.

In the conventional example of FIG. 5, since the master clock generator 7 is equipped in the unit # 1, the bus type time switch circuit 1 of this unit is set in the mode setting section 8.
Is set to the master mode by the output of the above, and the bus type time switch circuit 2 and the bus type time switch circuit 3 of the units # 2 and # 8 are set to the mode setting unit 9 and the mode setting unit 1.
Set to slave mode with 0. Similarly, the bus type time switch circuits of the units # 4 to # 7 (not shown) are also set to the slave mode.

The bus type time switch 1 set to the master mode inputs the frame synchronization signal and the PCM highway clock signal from the master clock generator 7 and outputs these signals to the inter-unit interface. Further, the bus type time switch circuit 2 and the bus type time switch circuit 3 set in the slave mode receive the frame synchronization signal and P from the inter-unit interface 18.
Input and use the CM highway clock signal.

Here, the frame synchronization signal is 8 KHz, P
When the CM highway clock signal is 4.096 MHz, the PCM highway is an 8-bit parallel type bus.
Logically, a 512-channel time slot is secured in the unit-to-unit communication path. If this is divided into eight units, output time slots of 64 channels can be used per unit.

Therefore, in the conventional example, in order to avoid the hardware failure due to the output collision of the PCM highway bus, the output time slots used in each unit are fixedly set by the inter-unit output setting sections 11 to 13. For example, the unit # 1 uses time slot numbers 0 to 63, the unit # 2 uses time slot numbers 64 to 127, and the unit # 8 uses time slot numbers 448 to 511 as output time slots.

[0007]

In such a conventional bus type time switch circuit, as is apparent from the above description, the output time slot for the unit-to-unit speech path is
Since it is fixedly specified by hardware, there is a drawback in that it is not possible to use a dynamic communication path between units according to the usage status of the system.

The present invention solves the above-mentioned problems and is a bus type time switch which enables use of a time slot of a dynamic communication path between units according to the traffic of each unit in an environment with high hardware reliability. It is intended to provide a circuit.

[0009]

In order to achieve the above-mentioned object, the present invention achieves the above-mentioned object by the main control unit of each unit in order of unit time slot number output permission setting for unit time slots and output of unit time. Through the output time slot setting means for setting the slot number and the input buffer connected to the intra-unit speech path, the PCM data of the intra-unit time slots are input and temporarily held in the order of the intra-unit time slot numbers. According to the in-unit time slot number stored in the output time slot setting means read out in the order of the inter-time slot number, the PCM data of the in-unit time slot is output to the output buffer connected to the inter-unit speech path. Data storage means and the unit A first bus supervisory signal indicating the use status for all time slots of the inter-channel speech path, and output permission setting information for all time slots of the inter-unit speech channel from the output time slot setting means, and the output of the output buffer The output permission signal for control, the second bus supervisory signal for the lower unit, and the error detection information when the output setting is made for the time slot already used as an output by the upper unit, and this fact is By the bus monitoring means that outputs an error detection interrupt signal to notify the control unit and the mode setting input,
In the master mode, a unit-to-unit call is made by inputting a frame synchronization signal and a PCM highway clock signal as timing information for operating the output time slot setting means, the data holding means and the bus monitoring means from the clock generation unit in the unit. In the slave mode, a clock input / output control means for inputting the frame synchronization signal and the PCM highway clock signal from the inter-unit communication path and outputting them to the inside of the unit is provided.

[0010]

According to the present invention, with the above configuration, the bus monitoring means compares the output time slot information of the first bus monitoring signal input from the host unit with the setting contents of the output time slot setting means, and sets the output in duplicate. If there is no time slot allocated, the output permission control of the output buffer connected to the inter-unit time slot is performed according to the setting contents of the output time slot setting means, and the PCM data of the in-unit time slot taken in the data holding means is unitized. Output to the inter-time slot and generate the second bus supervisory signal in which the information newly set for the output time slot is added to the first bus supervisory signal input from the upper unit, and output to the lower unit. did.

Further, the bus monitoring means compares the output time slot information of the first bus monitoring signal input from the host unit with the setting contents of the output time slot setting means, and there is a time slot for which output is duplicated. If this time slot does not comply with the setting contents of the output time slot setting means, does not permit output of the output buffer connected to the unit-to-unit communication path, and outputs the time slot information that is set for double output as an error. It holds it as detection information and outputs an error detection interrupt signal to the main control unit of the unit, and also adds a new output to the first bus supervisory signal input from the host unit, except for the time slot that is set for dual output. The second that adds the information set for the output time slot to
The bus monitoring signal of is generated and output to the lower unit.

[0012]

(Embodiment 1) The operation of the bus type time switch circuit as the first embodiment of the present invention in a normal time will be described in detail below with reference to FIGS. 1, 2, 3 and 4. explain. FIG. 1 is an internal block diagram of a bus type time switch circuit according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining operations of a control memory and a data memory in the bus type time switch circuit. FIG. 3 is a system configuration diagram of a plurality of units having the same bus type time switch circuit, and FIG. 4 is a timing chart of the same bus type time switch circuit.

It should be noted that FIG. 1 shows only the part relating to the one-way connection function from the intra-unit communication path to the inter-unit communication path regarding the intra-unit communication path and the inter-unit communication path described in the conventional example. Further, FIG. 3 shows a case where it is composed of eight units as in the conventional example. For convenience, the unit # 1, the unit # 2, and the unit # 8 are illustrated, and the units # 3 to # 7 are omitted. . Furthermore, FIG.
2 shows the input / output timing of the bus type time switch circuit of FIG. 1 and the internal timing necessary for explaining the internal operation.

In FIGS. 1 and 2, reference numeral 20 is an output time slot setting means for designating an in-unit time slot to be output to a unit-to-unit speech path, and a CPU control interface 30, a control memory 31, a control memory read address counter. It consists of 32. Reference numeral 21 is a data holding means for temporarily holding the PCM data of the in-unit time slot and outputting it to the unit-to-unit speech path.
3, an output buffer 34, a data memory 35, a data memory write address counter 36, and a data holding unit 37. Reference numeral 22 is a bus monitoring means for monitoring the usage status of the communication path between the units, and includes an output permission signal generation unit 38, a clock synchronization unit 39, a monitoring signal generation unit 40, and a monitoring signal output unit 4.
1. The error detection unit 42. Reference numeral 23 is a clock input / output control means for controlling input / output of a frame synchronization signal and a PCM highway clock signal used in the system.

The detailed functions of each means will be described below. First, the functional blocks constituting the output time slot setting means 20 will be described. In the CPU control interface 30, a unit control unit having a function equivalent to that of the conventional example sets and reads data in the control memory 31 and reads error information from an error detection unit 42 of the bus monitoring unit 22 which will be described later. It controls the interface function when performing.

The control memory 31 stores output control information for inter-unit time slots as shown in FIG. 2B and intra-unit time slot number information to be output.
FIG. 2B shows a case where both the inter-unit time slot and the intra-unit time slot have 512 channels, and addresses 0 to 511 of the address are associated with the inter-unit time slot number. The most significant bit of the memory is used as the output setting bit (E) for the inter-unit time slot, and the 9 bits from the least significant bit are output to each inter-unit time slot.
8 to D0).

The control memory read address counter 32 is
Address information is generated for reading the data stored in the control memory 31 in the order of inter-unit time slot numbers. The output timing of this address information is shown in FIG. 4 (e. Control memory read address counter output).

Secondly, the functional blocks constituting the data holding means 21 will be described. The input buffer 33 has an interface buffer function of inputting PCM data of each time slot in the unit.

The output buffer 34 has an interface buffer function of outputting PCM data in each time slot between the units. As shown in FIG. 2A, the data memory 35 temporarily holds the PCM data of the unit time slot.

Data memory write address counter 36
Generates write address information for writing the PCM data of the in-unit time slot into the data memory 35. The output timing of this address information is shown in FIG. 4 (g. Data memory write address counter output).

The data holding unit 37 inputs the read address information of the data memory 35 from the control memory 31 and temporarily holds and outputs it. Figure 4 shows the output timing of this address information.
(F. Data holding unit output).

Thirdly, the functional blocks constituting the bus monitoring means 22 will be described. Output permission signal generator 38
Inputs the output setting information for each inter-unit time slot from the control memory 31 and compares the bus setting signal input from the upper unit with the output setting information and permits the output setting only for the inter-unit time slot not set by the upper unit. Generate a signal.

The clock synchronization unit 39 synchronizes the signal generated by the output permission signal generation unit 38 with the PCM highway clock signal and outputs it as the output control signal of the output buffer 34. The timing of this output control signal is shown in FIG. 4 (h. Output control signal output).

The supervisory signal generator 40 receives the output setting information for each inter-unit time slot from the control memory 31 and the bus supervisory signal from the upper unit, and produces a supervisory signal to be output to the lower unit.

The supervisory signal output unit 41 is a supervisory signal generation unit 4
The monitoring signal from 0 is input, and this is output at a timing one frame after the temporary holding. The output timing of this supervisory signal is shown in FIG. 4 (d. Bus supervisory signal input / output).

The error detection unit 42 inputs the output setting information for each unit time slot from the control memory 31 and the bus supervisory signal from the upper unit to detect a double setting error, and detects each unit time slot unit. Hold this. When an error of at least one time slot is detected, an error detection signal is output.

Fourth, the clock input / output control means 23 will be described. The clock input / output control means 23 selects a frame synchronization signal and a PCM highway clock signal used in the system by a mode setting input. The modes to be set are the master mode and the slave mode as in the conventional example. In the master mode, the frame synchronization signal A and the PCM highway clock signal A are input from the in-unit interface, and the frame synchronization signal B and the PCM highway clock signal B are output to the inter-unit interface. In the slave mode, the frame synchronization signal B and the PCM highway clock signal B are input from the inter-unit interface, and the frame synchronization signal A and the PCM highway clock signal A are output to the intra-unit interface. Frame sync signal, PCM
4 shows the timing of the highway clock signal and the PCM highway data (a. Frame synchronization signal, b.P.
CM highway clock signal, c. PCM highway data).

Since the detailed operation of the bus type time switch circuit of the present embodiment has been clarified in the above description, in the following description, a system similar to the conventional example is constructed using the bus type time switch circuit. The operation in this case will be described with reference to FIG.

In FIG. 3, 51 to 53 are bus type time switch circuits for interconnecting the inter-unit speech path and the intra-unit speech path, 54 to 56 are unit control units for controlling exchange control of each unit, and 57 is a system. A master clock generator that generates a frame synchronization signal and a PCM highway clock signal that must be supplied to the whole, 58-
A mode setting unit 60 sets the clock supply mode of the bus type time switch.

Similar to the conventional example, each unit has a communication bus 14 between unit control units and a PCM which is a communication path between units.
Highway bus 15, frame synchronization signal bus 16 and PC
A multi-drop connection is made by an inter-unit interface 18 composed of an M highway clock bus 17, and a supervisory signal bus 19 is further connected in cascade from unit # 1 to unit # 8. Here, the monitoring signal input of the bus type time switch circuit 51 of the unit # 1 is fixed to logic 1 (an unused state in which output is not set) for all time slots, and the monitoring signal input of the bus type time switch circuit 53 of the unit # 8. The monitor signal output is open because there are no more lower units.

In FIG. 3, since the master clock generator 57 is equipped in the unit # 1, the bus type time switch circuit 51 of this unit is set to the master mode by the output of the mode setting unit 58, and the unit # 2 and the unit # 2 are set. The bus type time switch circuit 52 and the bus type time switch circuit 53 of # 8 are set to the slave mode by the mode setting unit 59 and the mode setting unit 60. Similarly, the bus type time switch circuits of the units # 4 to # 7 (not shown) are also set to the slave mode.

The bus type time switch 51 set to the master mode inputs the frame synchronization signal and the PCM highway clock signal from the master clock generator 57 and outputs these signals to the inter-unit interface 18. Further, the bus type time switch circuit 52 and the bus type time switch circuit 53 set in the slave mode are used by inputting a frame synchronization signal and a PCM highway clock signal from the inter-unit interface 18.

As shown in FIG. 4, the frame synchronizing signal is 8 KHz and the PCM highway clock signal is 4.0.
If the frequency is 96 MHz and the PCM highway is an 8-bit parallel bus, 512 channels of time slots are logically secured in the unit-to-unit speech path.

The operation from the start of the system operation to the shift to the normal operation state will be described below. At the start of system operation, the unit control units 54 to 56 of the respective units are
The inter-unit time slot used is adjusted using the inter-unit control unit communication bus 14. For example, if the time slots that can be output equally are assigned, the unit # 1 has time slot numbers 0 to 63 and unit # 2.
Indicates time slot numbers 64-127, unit # 8
Decides to use time slot numbers 448-511 as respective output time slots.

Therefore, the unit control section 54 sets the most significant bit of the control memory 31 of the bus type time switch circuit 51 to logic 0 (output setting) for the addresses 0 to 63, and the unit control section 55 Addresses 64 to the control memory 31 of the bus type time switch circuit 52
For 127, the most significant bit is logical 0 (output setting)
In addition, the unit controller 56 sends the addresses 448 to 51 to the control memory 31 of the bus type time switch circuit 53.
For 1, the most significant bit is set to logic 0 (output set). At this time, each bus type time switch circuit 51-
The bus monitoring means 22 of 53 receives the bus monitoring signal from the host unit and compares it with the above information set in the control memory 31 to control the output buffer and detect an error. In the above setting, since the time slots between the units are not used twice, no error is detected and the normal operation state is started, so that each unit can use time slots of 64 channels.

Next, the operation when changing the available inter-unit time slots of each unit once set will be described. As an example, secure 32 channels in addition to the 64 channels currently used by unit # 1,
As a result, let us consider the case where 32 of the 64 channels currently used by the unit # 2 are released.

First, the unit controller 54 of the unit # 1
Between the unit and the unit controller 55 of the unit # 2, the unit # 2 releases the unit-to-unit time slots 64-95 through the unit controller communication bus 14, and the unit # 1 uses this time slot. It is decided.

Next, the unit controller 55 of the unit # 2
In the control memory 31 of the bus type time switch circuit 52, regarding the addresses 64 to 95, the highest bit is set to logic 1 (output disabled setting), and the unit control to the effect that the inter-unit time slots 64 to 95 is released. The notification is sent to the unit controller 54 of the unit # 1 via the inter-part communication bus 14.

In response to this, the unit control section 54 of the unit # 1 controls the control memory 3 of the bus type time switch circuit 51.
With respect to 1, for the addresses 64-95, the most significant bit is set to logical 0 (output setting). Therefore, the unit # 1 can use 96 channels of the inter-unit time slots 0 to 95 as output time slots.

(Embodiment 2) An emergency operation will be described in detail below as a second embodiment of the present invention. Example 1
In the normal operation state as described in, at least one unit controller in the system erroneously sets the bus type time switch circuit due to external noise such as static electricity,
Described below is the method of recovering from a failure when double use of the time slot between units occurs.

As an example of the occurrence of a failure, as described in the first embodiment, from the situation in which eight units uniformly use the inter-unit time slots of 64 channels as an output, the unit # 1 has a unit of 96 channels. An explanation will be given of the case where the time slot number 96 is output and set while the time slot number 95 should be output and set while the inter-time slot is secured and is being set in the bus type time switch circuit 51.

First, the bus type time switch circuit 51 of the unit # 1 is inconsistent with the erroneous setting contents of the control memory because the input bus supervisory signal is logical 1 (output prohibition setting) for all time slots. Therefore, the bus monitoring signal output from the bus monitoring means 22 is set to logic 0 (output setting) for the time slot numbers 0 to 94 and 96.

Next, the bus type time switch circuit 52 of the unit # 2 inputs the above-mentioned bus monitoring signal from the unit # 1 and the bus monitoring means 22 causes the bus monitoring means 22 to control the memory 31.
It is detected that the inter-unit time slot number 96 is dual setting by comparing with the setting contents of.

As a result, the bus monitor 22 controls the output buffer by the output enable signal generator 38 and the clock synchronizer 39, prohibits the output to the inter-unit time slot number 96, and only the time slot numbers 97 to 127. Allow output. Further, the error detection unit sets the error detection bit for the inter-unit time slot number 96, which is set to be double output, to logic 1 (error occurrence state) and outputs an error detection interrupt signal. Also, it generates and outputs a bus supervisory signal to be sent to a lower unit. This bus supervisory signal is an inter-unit time slot number 0-12.
7 is set to logic 0 (output setting).

Next, the unit controller 55 of the unit # 2
Detects the error detection interrupt signal to read the error detection information held in the error detection unit 42 of the bus type time switch circuit 52. As a result, the higher-level unit has an incorrect setting and the unit time slot number 9
It is detected that 6 is used. Therefore, the unit controller 55 notifies the above-mentioned failure occurrence status via the unit controller 54 of the unit # 1 and the unit controller communication bus 14.

Receiving this, the unit controller 54 of the unit # 1 sets the control memory 31 again. Therefore, with respect to the addresses 0 to 95, the most significant bit is set to logic 0 (output setting), and the bus supervisory signal output from the bus supervisor 22 is the time slot numbers 0 to 95.
Is set to logic 0 (output setting).

Next, the bus-type time switch circuit 52 of the unit # 2 inputs the above-mentioned bus monitoring signal from the unit # 1 and the bus monitoring means 22 controls this by the control memory 31.
It is detected that the double setting of the inter-unit time slot number 96 is released by comparing with the setting content of.

As a result, the bus monitoring means 2 of the unit # 2
2 is an output permission signal generation unit 38 and a clock synchronization unit 39.
The output buffer is controlled by to permit output to the inter-unit time slot number 96, and permit output only to the time slot numbers 96 to 127.

Further, the error detecting section 42 of the bus monitoring means 22.
At, the double output setting error of the time slot number 96 is not detected, and the error detection interrupt signal output is canceled. By the above operation, the normal operation state is restored from the occurrence of the failure.

[0050]

As is apparent from the above, according to the present invention, the bus monitoring means compares the output time slot information of the first bus monitoring signal input from the host unit with the setting contents of the output time slot setting means. However, if there is no time slot with dual output settings, output permission control of the output buffer connected to the inter-unit time slot is performed according to the setting contents of the output time slot setting means, and the unit is loaded into the data holding means. Time slot P
The CM data is output to the unit-to-unit time slot, and the second bus supervisory signal in which the information newly set for the output time slot is added to the first bus supervisory signal input from the upper unit is generated to the lower unit. Further, the bus monitoring means compares the output time slot information of the first bus monitoring signal input from the higher-level unit with the setting contents of the output time slot setting means, and the time slot for which dual output is set is determined. In this case, for this time slot, time slot information that is set for dual output without complying with the setting contents of the output time slot setting means and without permitting output of the output buffer connected to the unit-to-unit communication path Is stored as error detection information, an error detection interrupt signal is output to the main control unit of the unit, and The first bus monitor signal inputted from Tsu bets, the added information newly set output time slot except the output are time slots configured as double 2
Since the bus monitoring signal of is generated and output to the lower unit, it is possible to use the time slot of the dynamic communication path between units according to the traffic of each unit in the environment with high hardware reliability. There is an effect that it is possible to provide a bus type time switch circuit.

[Brief description of drawings]

FIG. 1 is an internal block diagram of a bus type time switch circuit according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining operations of a control memory and a data memory in the same bus type time switch circuit.

FIG. 3 is a system configuration diagram of a plurality of units having a bus type time switch circuit according to an embodiment of the present invention.

FIG. 4 is a timing chart of a bus type time switch circuit according to an embodiment of the present invention.

FIG. 5 is a system configuration diagram of a conventional example.

[Explanation of symbols]

 20 output time slot setting means 21 data holding means 22 bus monitoring means 23 clock input / output control means 30 CPU control interface 31 control memory 32 control memory read address counter 33 input buffer 34 output buffer 35 data memory 36 data memory write address counter 37 Data holding unit 38 Output permission signal generation unit 39 Clock synchronization unit 40 Monitoring signal generation unit 41 Monitoring signal output unit 42 Error detection unit

Claims (2)

[Claims] 1. A call path between each unit is distributed in each unit such as a digital private branch exchange which constitutes a system with a plurality of units, and a call path between each unit is formed into a bus. A bus-type time switch circuit that connects in time slot units. The main control unit of each unit sets output permission settings for unit time slots and output unit time slot numbers in the order of unit time slot numbers. Via the output time slot setting means and the input buffer connected to the intra-unit speech path, the PCM data of the intra-unit time slots is input and temporarily held, and the inter-unit time slot number is ordered. It is stored in the read output time slot setting means. Data holding means for outputting the PCM data of the intra-unit time slot to the output buffer connected to the inter-unit speech path in accordance with the intra-unit time slot number, and the use from the upper unit to all time slots of the inter-unit speech path A first bus supervisory signal indicating the status and output permission setting information for all time slots of the unit-to-unit speech path are input from the output time slot setting means, and an output permission signal for controlling output of the output buffer and a lower unit The second bus supervisory signal and error detection information when the output setting is made for the time slot already used as an output by the host unit, and the error detection rate for notifying this to the main control unit of the unit The bus monitoring means that outputs an embedded signal and the mode setting input In the terminal mode, a frame synchronizing signal and PCM highway clock signal as timing information for operating the output time slot setting means, the data holding means, and the bus monitoring means are input from the clock generation unit in the unit, and the unit-to-unit communication path is input. In the slave mode, there is provided clock input / output control means for inputting the frame synchronization signal and the PCM highway clock signal from the unit-to-unit communication path and outputting them to the inside of the unit. The output time slot information of the first bus supervisory signal input from the unit is compared with the setting contents of the output time slot setting means, and if there is no time slot that is set as a dual output, the output connected to the inter-unit time slot Output buffer output permission control Output time slot setting means setting According to the contents, the PCM data of the in-unit time slot taken into the data holding means is output to the inter-unit time slot, and
A bus-type time switch circuit characterized by generating a second bus supervisory signal in which information for newly setting an output time slot is added to a first bus supervisory signal input from an upper unit, and outputting the signal to a lower unit. . 2. The bus monitoring means compares the output time slot information of the first bus monitoring signal input from the host unit with the setting contents of the output time slot setting means, and there is a time slot for which output is duplicated. In this case, regarding this time slot, the output buffer connected to the unit-to-unit communication path is not permitted to output without complying with the setting contents of the output time slot setting means It holds it as detection information and outputs an error detection interrupt signal to the main control unit of the unit, and also adds a new output to the first bus supervisory signal input from the host unit, except for the time slot that is set for dual output. The second bus supervisory signal to which the information set in the output time slot is added is generated and output to the lower unit. Bus type time switch circuit described.