JPH0271652A - System test control system - Google Patents

Abstract

PURPOSE:To confirm the normality of a register by allowing a processing unit to identify test information set from a management processor to a register section, setting prescribed notice information to the register section and allowing the processor to read it. CONSTITUTION:The management processor 1 sets test information to the register section 2 to confirm the normality of the register section 2 of a control interface section 19 periodically or at an optional point of time. When a microprocessor 18 identifies the test information set in the register section 2, the processor 18 sets the notice information preset to the test information to the register section 2. The management processor 1 reads the content of the register section 2 and discriminates it normal in the case of prescribed notice information. It is discriminated as a fault of the register section 2 if no fault information is outputted from the microprocessor 18 in the case of not prescribed notice information and the management processor 1 sends an alarm signal via a line 30.

Description

[Detailed Description of the Invention] [Summary] Regarding a system test control method for checking the normality of a system such as an exchange system, the purpose of this method is to check the normality of devices controlled by a management processor, especially registers, and to check the normality of each part. In a system comprising a management processor that controls and collects failure information, and a processing device that has a register section that sets control information from the management processor and sends failure information to the management processor, The management processor sets test information in the register section, the processing device identifies the test information, sets predetermined notification information corresponding to the test information in the register section, and the management processor is configured to read the notification information of the register section and check the normality of the register section.

[Industrial application field]

The present invention relates to a system test control method for checking the normality of a system such as an exchange system.

In a system such as a switching system, if the function of collecting failure information of each part does not operate normally, it will not be possible to quickly recognize the failure that actually occurred, leading to system failure. Therefore, it is necessary to confirm the normality of such functions.

[Conventional technology]

A conventional system clock generator in a switching system has a duplex configuration of a 0 system and a 1 system, for example, as shown in FIG. In the figure, 11 is a clock receiver (CREC), 12 is a clock selector (C3EL), 13 is a digital processing phase locked circuit (DP-PLL), 14 is a digital phase comparator (DPC), and 15 is a random access memory. (R
AM) 16 is read-only memory (ROM), 17
is an interface section (IF), 18 is a microprocessor (μP), 19 is a control interface section (CIF),
20 is a DA converter (DA), 21 is a voltage controlled crystal oscillator (VCXO), 22 is a control device (CTL), 33 is a pulse generator (PC), 34 is a selector (SEL),
35 is a distributor (DIS).

The clock signal extracted from the PCM line is passed through the clock receiver 11 to the clock selector 12 for the 0 system and 1 system.
and the selected clock signals are applied to the digital processing phase synchronization circuit 13. The clock signal in this case is, for example, an IKHz system clock signal, and the digital processing phase synchronization circuit 13 determines the phase of this clock signal and the output signal of the voltage-controlled crystal oscillator 21 by a path (not shown). The digital phase comparator 14 compares the information, transfers the phase difference information to the microprocessor 18, processes the microprocessor 18, outputs control data that makes the phase difference zero or a predetermined value, and transfers the control data to the interface. The input signal is applied to the DA converter 20 via the section 17, and the DA converter 20 converts it into an analog control voltage and applies it to the voltage controlled crystal oscillator 21, thereby outputting a clock signal phase-synchronized with the input clock signal.

The output signal of this voltage controlled crystal oscillator 21 is applied to a pulse generator 33, and from the pulse generator 33, for example, 16
．． 384MHz, 8.192MHz clock signals,
An 8 KHz frame clock signal color and a 500 Hz multi-frame clock signal are output, and are added to the O-system or 1-system detripulator 35 via the selector 34, and from the 0-system or 1-system detripulator 35 to the O-system or 1-system detripulator 35.
A clock signal is supplied to each part of the system.

The control device 22 mutually transfers current and standby switching information, etc. between the θ system and the 1 system, and controls each part accordingly.

Also, via a register (not shown) of the control interface section 19 of the digital processing phase synchronization circuit 13,
Information is transferred to and from the control device 22, and fault information of the digital processing phase synchronized circuit 13 is transferred to the control device 22 via the register of the control interface section 19 under the control of the microprocessor 18. The lighting control of the fault indicator lamp, etc. is performed.

[Problem to be solved by the invention]

If a failure occurs in the system clock generating device as described above, it will no longer be possible to supply a stable lock signal to each part, which will affect the entire exchange system and cause the system to go down. Therefore, 0 series and 1
Due to the redundant configuration with the systems, even if a failure occurs in one system, if the other system is healthy, it is possible to continue supplying a stable lock signal.

The occurrence of a failure is indicated by, for example, lighting up an indicator lamp on the front panel of the system clock generation device under the control of the control device 22. If fault information cannot be collected via the control interface section 19 of the digital processing phase synchronized circuit 13, the indicator lamp cannot be turned on even if a fault occurs. Therefore, there is a drawback that the occurrence of a failure cannot be recognized until the system goes down.

The present invention aims to confirm the normality of devices, particularly registers, controlled by a management processor.

[Means to solve the problem]

The system test control method of the present invention is for checking the normality of a register section of a processing device controlled by a management processor, and will be explained with reference to FIG.

A management processor that controls each part and collects fault information
and a system such as a switching system that includes a processing device 3 such as a system clock generation device having a register unit 2 that sets control information from the management processor 1 and also sets fault information to be notified to the management processor 1. Test information is set from the management processor 1 to the register section 2, the processing device 3 identifies this test information, sets predetermined notification information corresponding to the test information to the register section 2, and manages the test information. The processor 1 reads the notification information of the register section 2 and confirms the normality of the register section 2.

[Effect]

When the processing device 3 identifies that the test information has been set in the register section 2 from the management processor 1, it shifts to the test mode and sets predetermined notification information in the register section 2 corresponding to the test information. do. When the management processor 1 reads notification information corresponding to the test information written into the register section 2 from the register section 2, it determines that the register section 2 is normal. If the test mode is not entered and the specified notification information is not set in the register section 2, this indicates a runaway of the register section 2 or the microprocessor, etc. of the processing device 3, and if there is no alarm information due to the runaway of the microprocessor, etc. , it is determined that there is a failure in the register unit 2.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, showing a system clock generation device with a dual configuration of θ system and 1 system as in the conventional example, [l is a clock receiver (CREC),
12 is a clock selector (C3EL), 13 is a digital processing phase locked circuit (DP-PLL), 1
4 is a digital phase comparator (DPC), 15 is a random access memory (RAM), 16 is a read-only memory (ROM), and 17 is an interface unit (IP)
, 18 is a microprocessor (μP), 19 is a control interface unit (CIF), 20 is a DA converter (DA),
21 is a voltage controlled crystal oscillator (VCXO), 22 is a control device (CTL), and 23 is a timing generator (TG).
, 24 is a selector (SEL), 25 is a pulse generator (
PC), 26 is a distributor (Dis), 27.
28 is a line interface unit (LIF), 29 is a microprocessor (μP), 30 is a line for connecting to a console etc. (PLC), l is a management processor (Al:IM)
, 2 is a register section. In FIG. 2 and FIG. 1, the same reference numerals correspond to the same parts, and the processing device 3 in FIG. 1 corresponds to the digital processing phase synchronization circuit 13 in FIG.

Clock receiver 11, clock selector 12, digital processing phase synchronization circuit 13, selector 24,
The configuration and operation of the pulse generator 25, detripulator 26, etc. are the same as those in the conventional example described above, and the clock receiver 11 has a line interface unit 27, 28 that supports two lines.
, and a microprocessor 29 that controls these according to control information from the control device 22. Furthermore, the internal configurations of the first system clock receiver 11 and digital processing phase synchronization circuit 13 are omitted from illustration.

This system clock generation device is a timing generator that outputs a clock signal phase-synchronized with a clock signal extracted from a PCM line from a voltage controlled crystal oscillator 21, and adds the clock signal from a timing generator 23 to a pulse generator 25 based on the output signal. The various clock signals mentioned above are generated from the pulse generator 25 and supplied to each section from the distributor 26.

Further, the management processor l transfers information between the 0 system and the 1 system, and also transfers control information and the like to and from a maintenance console and the like via the line 30. It also transfers control information for the digital processing phase-locked circuit 13 via the control device 22, and collects failure information for the digital processing phase-locked circuit 13. In this case, control information transferred from the management processor l via the control device 22 is set in the register unit 2 provided in the control interface unit 19, and is read and identified by the microprocessor 18, and the control information is read and identified by the microprocessor 18. Control is performed, and the results and failure information are set in the register section 2 under the control of the microprocessor 18 and read by the management processor 1 via the control device 22.

If a failure occurs in the register section 2 of the control interface section 19, the digital processing phase synchronized circuit 13 cannot be controlled from the management processor 1 and the control device 22, and the digital processing phase synchronized circuit 13 cannot be controlled by the management processor 1. 13 failure information cannot be collected. In that case, the management processor
In this case, the occurrence of a failure cannot be recognized.

Therefore, in the present invention, the normality of the register section 2 of the control interface section 19 is checked periodically or at any arbitrary time. For this purpose, test information is set in the register section 2 from the management processor 1. When the microprocessor 18 identifies the test information set in the register section 2, it sets predetermined notification information in the register section 2 corresponding to the test information.

The management processor 1 reads the contents of the register section 2, and if it is the predetermined notification information, it determines that the register section 2 is normal. If the notification information is not the predetermined notification information, and if no failure information is output from the microprocessor 18, it is determined that there is a failure in the register section 2.

When the occurrence of such a failure in the register section 2 and the failure in the microprocessor 18, etc., is identified, the management processor 1 performs a turn! 30 to send an alarm signal to a maintenance console or the like.

FIG. 3 is an explanatory diagram of the register section, and registers R1-R
5 is shown. Note that a configuration including other registers is also possible.

Registers R1 to R5 show an 8-bit configuration, register R1 is a mode register that notifies the management processor 1, and the mode is displayed using bits bo and bl.
"OO" is normal mode, 601" is high speed mode, '10"
"11" indicates free run mode, and "11" indicates holdover mode. Also, bit b6 is the clock receiver CRE
Bit b7 indicates a response to the mode change command (“1”); bit b7 indicates a response to the mode change command (“1”).

Register R2 is used to set mode change designation information from management processor 1, and bits bo and bt display the mode in the same way as register R1 described above, and bit b6 specifies test mode (1" ) and bit b7 enables (“1”) or disables (“O”)
shows.

Further, registers R3 and R4 are registers in which the management processor 1 sets instruction information to change the alarm generation threshold.In register R3, bits bO-b3 instruct a frequency offset value, and bits b4 to b7 instruct a phase step value. In register R4, bit bONb3 specifies the timing, bits b4 to b7 specify the false failure point. For example, b4 is the frequency offset, b5 is the fast startup timeout, b6 is the phase step, and bl is the Specifies the end of the range.

Further, register R'5 is a register for notifying failure information to the management processor 1, bit bo is a frequency offset, bl is a fast startup timeout, b2 is a phase step,
b3 is the end of the range, b4 is the input disconnection to the digital processing phase synchronized circuit 13, b5 is the parity error of the microprocessor 18 of the digital processing phase synchronized circuit 13, b6 is the parity error of the control data, b
l indicates a watchdog timer error.

When the management processor 1 checks the normality of the register section 2 of the control interface section 19 while the digital processing phase synchronized circuit 13 is operating in the normal mode, the management processor 1 checks the register section 2 of the control interface section 19 via the control device 22. b7 to bO of register R2 of section 2
11000011”. That is, write b6 “
1” to specify the test mode, bits bo and bl
The mode display will be set to 11".

When the microprocessor 18 of the digital processing phase synchronized circuit 13 reads the contents of this register R2 and recognizes that the test mode is specified,
Information sending to registers other than 1 is stopped, and bits bQ and bl of register R1 are set to "11" in accordance with the mode "11" designated by management processor 1.

The management processor 1 reads the contents of this register R1 via the control device 22 and can recognize that the mode has shifted to the mode "11" specified when the test mode was specified, so it determines that the register section 2 is normal. Then, an instruction is given to change from test mode to normal mode.

If the management processor l reads the contents of the register R1 and a mode other than the specified mode is displayed, it assumes that there is a failure in the register section 2 or a runaway in the microprocessor 18, and changes bit b5 of the register R5, etc. If there is no indication of a fault in the microprocessor 18, it is determined that the fault is in the register unit 2, and the fault information is transferred to a maintenance console or the like via the line 30.

For the digital processing phase synchronization circuit 13,
Even if the test mode is specified from the management processor 1, register processing is sufficient, so the output signal from the voltage control and crystal oscillator 21 is applied to the timing generator 23 as usual, which has a negative effect on the generation of the system clock signal. will not be given. In addition to the system clock generation device, it is also possible to check the normality of register units in various processing devices controlled by the management processor, as described above.

〔Effect of the invention〕

As explained above, the present invention sets test information from the management processor 1 to the register section 2, and the processing device 3 such as the system clock generation device identifies the test information.
Predetermined notification information corresponding to the test information, for example, mode information specified in the test mode, is sent to the register section 2, and the management processor 1 sends it to the register section 2.
The normality of the register section 2 can be confirmed by reading the contents of the register section 2, and the normality of the register section 2 can be confirmed without affecting the operation of the processing device 3 such as the system clock generation device. Since it is possible to avoid an uncontrollable state or a state in which failure information cannot be collected due to a fault in the register unit 2, there is an advantage that reliability can be improved.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is an explanatory diagram of a register section, and FIG. 4 is a block diagram of a conventional example. 1 is a management processor, 2 is a register section, 3 is a processing device,
11 is a clock receiver, 12 is a clock selector, 1
3 is a digital processing phase synchronized circuit, 18 is a microprocessor, 19 is a control interface unit, 21
2 is a voltage controlled crystal oscillator, and 22 is a control device.

Claims (1)

[Claims] A management processor (which controls each part and collects failure information)
1); and a processing device (3) having a register section (2) for setting control information from the management processor (1) and fault information to be notified to the management processor (1). Test information is set in the register section (2) from the management processor (1), the processing device (3) identifies the test information, and sends a predetermined notification corresponding to the test information. The information is stored in the register section (
2), and the management processor (1) reads the notification information of the register section (2) to confirm the normality of the register section (2).