JP2001067274A - Self-diagnostic system and method for main storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a bank control part function test and memory test performable by a single main storage device including a cross bar function constituting a multi-processor system without connecting any processor with this storage device. SOLUTION: A pseudo request generating function part 21 is provided between a processor 1 and a cross bar 22 in a main storage device 2. The pseudo request generating function part 21 generates a command, an in-memory bank address and an RA, and issues a pseudo request for operating bank control part function test or memory test to the cross bar 22. Also, the pseudo request generating function part 21 is provided with a counter for counting the number of request/reply and an address counter for counting-up this each time the request is issued at the time of memory test. Moreover, this pseudo request generating function 21 is provided with a function for comparing data read with a reading command with held writteen data and a function for checking-on an ECC circuit at the time of memory test.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a method for diagnosing a main memory device including a crossbar coupled to a plurality of processors, and more particularly to a means for generating a pseudo request for self-diagnosis between a processor and a crossbar. The present invention relates to a self-diagnosis method and method for a main storage device having

[0002]

2. Description of the Related Art Examples of conventional diagnostic methods for checking the function of a main storage device are disclosed in JP-A-10-312311 and JP-A-10-12311.
124438.

In these conventional systems, FIG.
As shown in FIG. 1, it is necessary to connect an external device (a processor or an external input / output device) in order to check the operation and function of the main storage device. A request for performing an operation check or a function check diagnosis is generated by an external device.

[0004]

However, in the above-mentioned conventional system, there is a problem that it is impossible to diagnose only the main storage device.

[0005] The reason is that in the main storage device of the above-mentioned system, since a request for performing an operation check and a function check diagnosis is performed by an external device, the operation check and the function check diagnosis can be performed without the connection of the external device. This is because it cannot be done.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a means for performing a function test of a bank control unit and a memory bank test in a main storage device having a crossbar by itself without connecting to an external device such as a processor. It is in.

[0007]

According to a first aspect of the present invention, there is provided a self-diagnosis method for a main storage device, comprising a plurality of memory banks, a plurality of bank controllers for controlling the memory banks, and a crossbar connected to a plurality of processors. A self-diagnosis method for a main storage device, comprising: a pseudo request generation function unit that generates a pseudo request for self-diagnosis between the processor and the crossbar.

According to a second aspect of the present invention, in the self-diagnosis method of the main storage device according to the first aspect, the pseudo request generation function unit includes a pseudo request for performing a function test of the bank control unit and a memory of the memory bank. A pseudo request for performing a test is generated.

In a self-diagnosis method for a main storage device according to a third aspect of the present invention, in the first aspect, the pseudo request generation function unit has selector means for separating the pseudo request from a processor request issued by the processor. Features.

In a self-diagnosis method for a main memory device according to a fourth aspect of the present invention, in the first aspect, the pseudo request generation function unit has an address counter for performing memory access by the pseudo request. .

According to a fifth aspect of the present invention, in the self-diagnosis method of the main storage device according to the first aspect, the pseudo request generation function unit holds the data set by the pseudo request and compares the data with the reply data. It is characterized by having.

In a self-diagnosis method for a main storage device according to a sixth aspect of the present invention, in the first aspect, the pseudo request generation function unit includes a request counter for counting the number of issued pseudo requests and a result of the pseudo request. A reply counter for counting the number of certain replies; and a means for comparing the value of the request counter with the value of the reply counter.

In a self-diagnosis method for a main storage device according to a seventh aspect of the present invention, in the first aspect, the pseudo request generation function unit checks the ECC function for a memory bank in the main storage device. It is characterized by having means for performing self-diagnosis.

According to an eighth aspect of the present invention, there is provided a self-diagnosis method for a main storage device, comprising: a plurality of memory banks; a plurality of bank controllers for controlling the memory banks; and a crossbar connected to a plurality of processors. A self-diagnosis method, wherein a selector for separating a pseudo request generated by a pseudo request generation function unit provided between the processor and the crossbar from a processor request issued by the processor is switched to a pseudo request side, and a bank control unit function is provided. Switch the selector that separates the test from the memory test to the bank controller functional test side, generate a pseudo request for writing, hold the generated write data, and write the write data to the memory bank set address based on the generated pseudo request Pseudo requests for writing and reading It reads data from the setting address of the memory bank based on the pseudo requests generated form, and comparing the write data stored with data read from the memory banks.

According to a ninth aspect of the present invention, there is provided a self-diagnosis method for a main storage device, comprising: a plurality of memory banks; a plurality of bank controllers for controlling the memory banks; and a crossbar connected to a plurality of processors. A self-diagnosis method, wherein a selector for separating a pseudo request generated by a pseudo request generation function unit provided between the processor and the crossbar from a processor request issued by the processor is switched to a pseudo request side, and a bank control unit function is provided. A selector for switching between a test and a memory test is switched to the memory test side, a pseudo request for writing to all addresses of the memory bank is generated, the generated write data is held, and a failure of the memory bank is detected. Check the ECC circuit on Writes the generated write data to all addresses of the memory bank based on the request, generates a pseudo request for reading from all addresses of the memory bank, and generates all pseudo addresses for the read based on the pseudo request for reading. , And comparing the data read from the memory bank with the held write data.

According to a tenth aspect of the present invention, in the self-diagnosis method of the main storage device according to the eighth or ninth aspect, a value of a request counter for counting the number of issued pseudo requests and a reply of a result of the pseudo requests are provided. It is characterized in that the value is compared with the value of a reply counter for counting the number, and when the values are different, an error is generated.

[0017]

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the embodiment of the present invention.

FIG. 2 is a diagram showing the flow of information between blocks. The processor 1 shown in FIG. 1 and the pseudo request generation function unit 21 and the crossbar 22 corresponding to the processor 1 are shown in FIG.
And the flow of information between the arbitrary bank control unit 23 and the memory bank 24 corresponding to the bank control unit 23.

Referring to FIG. 1, in the self-diagnosis method of the main storage device of the present invention, the processors (# 1) 1a to 1m are connected to the main storage device 2, and the main storage device 2 is a pseudo memory. Request generation function unit (# 1) 21a to pseudo request generation function unit (#m) 21m, crossbar 22, bank control unit (# 1) 23a to bank control unit (#n) 23
n and memory bank (# 1) 24a to memory bank (#
n) 24n. The processor (# 1) 1a to processor (#m) 1m, the pseudo request generation function unit (# 1) 21a to the pseudo request generation function unit (#m) 21m, the bank control unit (# 1) 23a to the bank control unit (#N) 23n and memory bank (# 1) 2
4a to memory bank (#n) 24n,
In the case of representing one, a processor 1, a pseudo request generation function unit 21, a bank control unit 23, and a memory bank 2
Notation 4

The processor (# 1) 1a to the processor (#)
m) 1m each have one access port to the main storage device 2 and correspond to corresponding pseudo request generation function units (# 1) 21a to #m in the main storage device 2 Connected to As shown in FIG. 2, four buses of a routing address (hereinafter abbreviated as RA) bus 61, a data bus 62, a reply bus 68 and a reply data bus 69 are provided between the processor 1 and the pseudo request generation function unit 21. Connected by

Simulated request generation function unit (# 1) 21a
The pseudo request generation function unit (#m) 21m exists corresponding to the access port of the processor (# 1) 1a to the processor (#m) 1m, and includes the processor (# 1) 1a to the processor (#m) 1m. It is located between the crossbar 22. As shown in FIG. 2, an RA bus 61 and a data bus 62 are provided between the processor 1 and the pseudo request generation function unit 21.
, A reply bus 68 and a reply data bus 69, and a pseudo request generation function unit 21 and a crossbar 22.
, A reply bus 68, a reply data bus 69, a crossbar input RA bus 81, and a crossbar input data bus 9
1 connected.

The pseudo request generating function unit 21 generates a pseudo request for performing a bank controller functional test and a memory test, and performs memory access based on the generated pseudo request. The mode is switched between a mode for processing a processor request issued from the processor 1 (processor request mode) and a mode for processing a pseudo request generated by the pseudo request generation function unit 21 (pseudo request mode).

The pseudo request generation function unit 21 performs the following three functions.

The first function is to check the operation of the bank control unit 23 in the pseudo request mode. This function confirms the operation of the bank control unit 23 by giving an access command, an address in an access destination memory bank, and write data according to an external designation, and comparing the reply data with preset data. I do.

The second function is to test a memory bank in the pseudo request mode. This function specifies the memory test command from the outside, writes data specified from the address 0 to the maximum address in the memory bank from the outside, and reads from the address 0 to the maximum address in the memory bank after the write operation is completed. I do. During this operation, an error correction code (hereinafter abbreviated as ECC) circuit in the bank control unit 23 is checked on to provide a function of specifying a failure / failure location of the memory bank 24. The above-described series of processing from writing to reading is automatically performed.

Finally, a third function is to process a request from the processor 1 in the processor request mode. Information transferred from the processor 1 via the RA bus 61 and the data bus 62 is sent to the crossbar 22 via the crossbar input RA bus 81 and the crossbar input data bus 91. The information transferred from the crossbar 22 via the reply bus 68 and the reply data bus 69 is sent to the processor 1 as it is.

The configuration and operation of the dummy request generation function unit 21 will be described later in detail.

The crossbar 22 includes a pseudo request generation function unit (# 1) 21a to a pseudo request generation function unit (#m).
21m and each of the bank control units (# 1) 23a to (n) 23n. As shown in FIG. 2, the pseudo request generation function unit 21 and the crossbar 2
Reply bus 68 and reply data bus 69
, A crossbar input RA bus 81 and a crossbar input data bus 91, and a crossbar 22 and a bank control unit 23.
Are connected by a bank access bus 63, a bank reply bus 66, and a bank reply data bus 67.

The crossbar 22 is connected to the crossbar input RA bus 8.
In accordance with the request RA by No. 1, data is sent to the bank access bus 63 of the bank control unit 23 corresponding to the memory bank 24 to be accessed. In the case of a reply, based on the data returned from the bank control unit 23 via the bank reply bus 66 and the bank reply data bus 67, the dummy request generation function unit 21 is sent via the reply bus 68 and the reply data bus 69 based on the data returned. To return.

The bank control units (# 1) 23a to (n) 23n are connected to the crossbar 22, respectively.
Also, they are connected to memory banks (# 1) 24a to memory banks (#n) 24n, respectively. As shown in FIG. 2, the crossbar 22 and the bank control unit 23 are connected by a bank access bus 63, a bank reply bus 66 and a bank reply data bus 67, and the memory between the bank control unit 23 and the memory bank 24 is a memory. The bank access bus 64 and the read data bus 65 are connected. Bank control unit 2
3 is capable of memory access to the corresponding memory bank 24.

The memory banks (# 1) 24a to (n) 24n correspond to the corresponding bank control units (# 1) 2.
3a to the bank control unit (#n) 23n. FIG.
As shown in (1), the bank control unit 23 and the memory bank 24 are connected by a memory bank access bus 64 and a read data bus 65. Based on the memory request data of the memory bank access bus 64 received from the corresponding bank control unit 23, data is written to or read from a specified address.

Next, the interface between the blocks will be described with reference to FIGS. The interface between the pseudo request generation function unit and the crossbar will be described in the detailed description of the pseudo request generation function unit.

FIG. 3 is a diagram for explaining an interface between the processor and the main storage device, FIG. 4 is a diagram for explaining an interface between the crossbar and the bank controller, and FIG. 5 is a diagram for explaining the interface between the bank controller and the memory bank. FIG. 3 is a diagram for explaining an interface between them.

First, the interface between the processor 1 and the main storage device 2 will be described.

Referring to FIG. 3, RA bus 6 which is a connection bus between processor 1 and main storage device 2 shown in FIG.
1, the details of the interface contents of the data bus 62, the reply bus 68 and the reply data bus 69 are shown.

In FIG. 3, the vertical direction indicates the time axis,
The contents of the interface at each of the first to fifth clocks are shown from top to bottom. The RA bus 61 in FIG. 2 is a bus to which RAs 611 to 615 are transferred, and the data bus 62 in FIG. 2 is main bus access data 621 to 625.
Is a bus to be transferred.

A main memory access request issued from the processor 1 to the main memory 2 is composed of RA and main memory access data. A set of RA and main storage access data at each T in FIG. 3 is a main storage access request, and FIG. 3 shows that the processor 1 has issued five consecutive requests.

RA 611 to 615 take one of the values 1 to n, and this value indicates the memory bank to which the main memory access request wants to access. For example, RA
Of the memory bank (#) by setting the value of
1) Enable 24a memory access.

The main storage access data 621 to 625 are composed of data necessary for performing a bank access in the main storage device 2. That is, it is composed of a command indicating the bank access type, an address in the memory bank, and data to be written in the memory bank.

The reply bus 68 in FIG. 2 is a bus to which replies (hereinafter referred to as RPY) 681 to 685 are transferred, and the reply data bus 69 in FIG. 2 transfers reply data 691 to 695. It is a bus.

FIG. 3 shows that replies are returned five consecutive times after NT after receiving the main memory access request.

Next, an interface between the crossbar 22 and the bank controller 23 will be described.

Referring to FIG. 4, the crossbar 2 shown in FIG.
The details of the interface contents of the bank access data bus 63, the bank reply bus 66, and the bank reply data bus 67 which are connection buses between the bank control unit 2 and the bank control unit 23 are shown.

In FIG. 4, the vertical direction indicates the time axis,
The contents of the interface at each of the first to fifth clocks are shown from top to bottom. The bank access data bus 63 in FIG.
The bank reply bus 66 in FIG. 2 is a bus to which bank control unit reply signals (hereinafter, referred to as B-RPY) 661 to 665 are transferred, and the bank reply data bus 67 is a bank reply bus. Data 671
To 675 are buses to be transferred. FIG. 4 shows that the request has been issued five times.

The bank access data 631 to 635 are constituted by data necessary for memory access. That is,
It is composed of a command indicating memory access, an address for memory access, and data for writing to a memory bank.

The B-RPYs 661 to 665 are composed of reply destination information and the like, and the bank reply data 671 to 675 are composed of data read from the memory bank 24 and the like.

FIG. 4 shows that replies are returned five times consecutively after the MT after receiving the bank access data.

Finally, the interface between the bank control unit 23 and the memory bank 24 will be described.

Referring to FIG. 5, details of the interface contents of a memory bank access bus 64 and a read data bus 65 which are connection buses between the bank control unit 23 and the memory bank 24 shown in FIG. 2 are shown.

In FIG. 5, the vertical direction indicates the time axis,
The contents of the interface at each of the first to fifth clocks are shown from top to bottom. The memory bank access bus 64 in FIG.
A read data bus 65 in FIG. 2 is a bus to which read data 651 to 655 are transferred.

Memory bank access data 641 to 64
Reference numeral 5 is composed of a random access memory (hereinafter abbreviated as RAM) control signal and data to be written to the RAM, and read data 651 to 655 are composed of data output from the RAM.

FIG. 5 shows that the memory bank is accessed five times and the reply data is returned five times after LT.

Next, the configuration and operation of the pseudo request generation function unit 21 of the present invention will be described in detail.

The configuration of the dummy request generation function unit 21 will be described with reference to FIG. FIGS. 6A and 6B are diagrams showing the configuration of the pseudo request generation function unit, where FIG. 6A shows the configuration related to output to the crossbar, and FIG. 6B shows the configuration related to input from the crossbar.

The RA generation unit 2101 generates an RA for issuing a request to the memory bank 24 to be accessed. An RA for the memory bank 24 in its own port may be automatically generated, or an arbitrary memory bank 2
4 may be designated. For example, when the RA for the memory bank 24 in its own port is automatically generated, if the pseudo request generation function unit 21 is the pseudo request generation function unit (# 1) 21a, the memory bank (# 1) 24a R to issue a request to
A ("1") is generated.

The command generator 2102 generates a write command or a read command in response to an external instruction at the time of the bank controller function test.

The write data generation unit 2103 sets the write data at the time of the bank control unit function test and the memory test, and holds the set data after issuing the request. As the write data, any data may be set according to an instruction from the outside, or data may be automatically generated and set internally.

The address generator 2104 sets an arbitrary address from the outside at the time of the bank controller function test.

The command generation unit 2105 generates a write command for all addresses of the memory bank 24 and issues a request at the time of a memory test, and then generates a read command for all addresses and issues a request.

The address generation unit 2106 has an internal address counter for the addresses in the memory bank, and uses the value of the address counter as an address for memory access. At the start of writing or reading of the memory test, the address counter is reset and incremented by one each time a request is issued.

The test switching selector 2107 discriminates between the bank control unit function test and the memory test in accordance with the bank control unit function test / memory test switch signal 711. Bank control unit function test / memory test switching signal 7
When 11 is "0", a bank control unit function test is performed.
When it is 1 ", a memory test is performed.

The RA switching selector 2108 uses the pseudo request switching signal 710 to
A and the processor request RA are switched. When the pseudo request switching signal 710 is "0", the request becomes a processor request RA, and when it is "1", the request becomes a pseudo request RA.

The data switching selector 2109 switches between pseudo request data and processor request data in response to a pseudo request switching signal. When the pseudo request switching signal 710 is "0", it becomes processor request data, and when it is "1", it becomes pseudo request data.

The request counter 2110 is a counter that counts up each time a request is issued.

The reply counter 2111 is a counter that counts up each time a reply is returned.

Each time a reply is returned, the reply data comparison unit 2112 compares the reply data with the data held in the write data generation unit 2103.

The operation of the dummy request generation function unit 21 will be described with reference to FIGS. 1, 6 and 7 to 10. FIGS. 7 and 8 are time charts showing a function test of the bank control unit by generating a pseudo request, and FIGS. 9 and 10 are time charts showing a memory test by generating a pseudo request.

The operation of the pseudo request generation function unit 21 is as follows.
It has three modes: a normal operation for processing a request from the processor 1, a bank controller functional test by pseudo request generation, and a memory test by pseudo request generation.
That is, the main storage device 2 can perform these three operations. Which mode is operated depends on the settings of the selectors 2107 to 2109 in the pseudo request generation function unit 21.

Here, of the three operation modes, two operations of a bank controller functional test by generating a pseudo request and a memory test by generating a pseudo request will be described. In the description, the pseudo request generation function unit (# 1) 21a connected to the port 1 and the bank control unit (# 1)
23a and a memory bank (# 1) 24a as an example.

First, the operation in the case of performing a bank controller functional test by generating a pseudo request will be described with reference to FIGS. 7 and 8. FIG.

The pseudo request generation function unit (# 1) 21a
When the mode is switched from the outside to the mode for performing the bank control unit function test, the pseudo request switching signal 710 for switching the selector 2108 becomes “1” (meaning the pseudo request selection), and the value generated by the RA generation unit 2101 “1” (because it is port 1 in this example) is selected, and the crossbar input R via the crossbar input RA bus 81 is selected.
The signal is transferred to the crossbar 22 as an A signal.

The bank control unit function test / memory test switch signal 711 for switching the selector 2107 is “
0 "(means a bank controller functional test), selector 2
Pseudo request switching signal 710 for switching 109
Becomes "1" (meaning pseudo request selection), and a command (written in this example) set in advance in the command generation unit 2102 from the outside and the write data generation unit 2
103 also includes data set in advance from outside (in this example, “F
F ”) and an address (“ 01 ”in this example) preset from the outside by the address generation unit 2104 and transferred to the crossbar 22 as a crossbar input data signal via the crossbar input data bus 91. .

Since one request has been issued, the request counter 2110 is incremented by one.
1 ".

The crossbar 22 receives the above signal and operates in a manner that no contention occurs.
3 to the bank control unit (#
1) Send to 23a.

The bank control unit (# 1) 23a receives the bank access data sent from the crossbar 22, generates a signal for writing data "FF" to the address "01" of the memory bank (# 1) 24a, The data is transmitted to the memory bank (# 1) 24a as memory bank access data via the memory bank access bus 64.

The memory bank (# 1) 24a receives the memory bank access data transmitted by the bank control unit (# 1) 23a, and stores the data "FF" at the address "01".
Write.

When the above operation is completed, the bank control unit (#
1) 23a is B-RP via bank reply bus 66
Y is returned to the crossbar 22. Note that the bank control unit (#
1) B-RPY (represented as RYn in FIG. 8) which is a reply from 23a is returned after several T.

The crossbar 22 operates in such a manner that no conflict occurs, and returns the RPY to the pseudo request generating function unit (# 1) 21a via the reply bus 68. At this time, since one reply is returned, the reply counter 2111 is incremented by one to “1”.

If the bank controller (# 1) 23a or the memory bank (# 1) 24a does not operate normally, the RPY is not returned and the reply counter 2111 counts up even if the above operation is completed. Therefore, the value of the request counter 2110 is different from the value of the reply counter 2111 and is detected as an error.

When the above-mentioned write operation is completed normally, a read operation is performed on the same address, so that the operation of the read operation can be confirmed.
The operation in this case will be described.

Also in this case, since the pseudo request switching signal 710 for switching the selector 2108 is "1" (meaning pseudo request selection), the RA generation unit 21
01 is selected and the crossbar input RA is selected.
The signal is transferred to the crossbar 22 via the bus 81 as a crossbar input RA signal.

The bank control unit function test / memory test switching signal 711 for switching the selector 2107 is “
0 "(means a bank controller functional test), selector 2
Pseudo request switching signal 710 for switching 109
Becomes "1" (meaning pseudo request selection), and a command (read in this example) set in advance in the command generation unit 2102 and the address generation unit 2104
The address previously set from outside (“01” in this example)
Is transferred to the crossbar 22 via the crossbar input data bus 91 as a crossbar input data signal.

Since one request has been issued, the request counter 2110 is incremented by one.
2 ".

The crossbar 22 receives the above signal and operates in a manner that no contention occurs.
3 to the bank control unit (#
1) Send to 23a.

The bank control unit (# 1) 23a receives the bank access data transmitted from the crossbar 22, generates a signal for reading data from the address "01" of the memory bank (# 1) 24a, and generates a signal for the memory bank access. The data is transmitted to the memory bank (# 1) 24a via the bus 64 as memory bank access data.

The memory bank (# 1) 24a receives the memory bank access data and reads the data from the address "01". The read data is sent to the bank controller (# 1) 23a via the read data bus 65.

When receiving the read data, the bank controller (# 1) 23a returns the B-RPY and the bank reply data to the crossbar 22 via the bank reply bus 66 and the bank reply data bus 67.

The crossbar 22 operates in such a manner that no competition occurs, and returns the RPY and the reply data to the pseudo request generation function unit (# 1) 21a via the reply bus 68 and the reply data bus 69.

The reply counter 2111 indicates that the reply is 1
Since it has been returned, it is incremented by one to "2".

If the bank controller (# 1) 23a or the memory bank (# 1) 24a does not operate normally, the RPY is not returned and the reply counter 2111 counts up even if the above operation is completed. Therefore, the value of the request counter 2110 is different from the value of the reply counter 2111 and is detected as an error.

The reply data comparison unit 2112 stores the reply data and the write data generation unit 210 in advance.
The data is compared with the data (reference value) that has been set and stored in step 3, and if different, the error is detected and reported.

With the above operation, the function of the bank control unit 23 can be confirmed.

Second, the operation when a memory test is performed by generating a pseudo request will be described with reference to FIGS. 9 and 10. FIG. Here, for the sake of simplicity, the description will be made assuming that the addresses of the memory bank (# 1) 24a are addresses 0 to 3.

The pseudo request generation function unit (# 1) 21a
When the mode is switched from the outside to the memory test mode, the pseudo request switching signal 710 for switching the selector 2108 becomes “1” (meaning pseudo request selection), and the value “1” generated by the RA generation unit 2101
(Because it is set to port 1 in this example), it is transferred to the crossbar 22 via the crossbar input RA bus 81 as a crossbar input RA signal.

The bank control section function test / memory test switch signal 711 for switching the selector 2107 is “1”.
1 "(means a memory test), and the pseudo request switching signal 710 for switching the selector 2109 is" 1 ".
(Meaning pseudo request selection), the write command generated by the command generation unit 2105, the data set in advance in the write data generation unit 2103 ("FF" in this example), and the data generated by the address generation unit 2106. (In this example, the value of a 2-bit address counter that counts up by one each time a request is issued, the initial value is “00”), and the crossbar input data signal is input to the crossbar 2 via the crossbar input data bus 91.
Transfer to 2.

Since one request has been issued, the request counter 2110 is incremented by one.
1 ".

The crossbar 22 receives the above signal and operates in a manner that no contention occurs.
3 to the bank control unit (#
1) Send to 23a.

The bank control unit (# 1) 23a receives the bank access data sent from the crossbar 22, generates a signal for writing data "FF" to the address "00" of the memory bank (# 1) 24a, The data is transmitted to the memory bank (# 1) 24a as memory bank access data via the memory bank access bus 64.

The memory bank (# 1) 24a receives the memory bank access data transmitted by the bank controller (# 1) 23a, and stores the data "FF" in the address "00".
Write.

The reply B-RPY (denoted as RYn in FIG. 10) from the bank control unit (# 1) 23a is returned after a few T. In the example of FIG. 10, B-RPY is returned after 4T.

The above-mentioned writing process is repeated three times, for a total of 4
Times of write command, memory bank address 0-3
Data "FF" is written at the address (in this example, the command is issued four times because the addresses of the memory banks are addresses 0 to 3).

After writing to address 3 by the write command, the address counter is counted up and returns to zero. Here, the writing stage ends and the reading stage starts.

Subsequently, since the pseudo request switching signal 710 for switching the selector 2108 is “1” (meaning pseudo request selection), the RA generation unit 2101
The value “1” generated in step (1) is selected and the crossbar 22 is output as a crossbar input RA signal via the crossbar input RA bus 81.
Transfer to

The bank control section function test / memory test switch signal 711 for switching the selector 2107 is “1”.
1 "(means a memory test), and the pseudo request switching signal 710 for switching the selector 2109 is" 1 ".
(Meaning pseudo request selection), the read command generated by the command generation unit 2105 and the address generated by the address generation unit 2106 (in this example, the value of a 2-bit address counter that counts up by 1 every time a request is issued, The initial value “00”) is selected and transferred to the crossbar 22 via the crossbar input data bus 91 as a crossbar input data signal.

Since one request has been issued, the request counter 2110 is incremented by one.
5 ".

The crossbar 22 receives the above signal and operates in a manner that no contention occurs.
3 to the bank control unit (#
1) Send to 23a.

The bank control unit (# 1) 23a receives the bank access data sent from the crossbar 22, generates a signal for reading data from the address "00" of the memory bank (# 1) 24a, and The data is transmitted to the memory bank (# 1) 24a via the bus 64 as memory bank access data.

The memory bank (# 1) 24a receives the memory bank access data and reads the data from the address "00".

The B-RPY (shown as RYn in FIG. 10) and the bank reply data from the bank control unit (# 1) 23a are returned after a number T. In the example of FIG. 10, B-RPY and bank reply data are returned after 4T.

The above reading process is repeated three times, for a total of four
Memory bank addresses 0 to 3
Data is read from the address (in this example, the command is issued four times because the addresses of the memory banks are addresses 0 to 3).

After reading up to address 3 by the read command, the address counter is counted up and returns to zero. Here, the read stage ends.

The read data is sent to the bank control unit (# 1) 23a via the read data bus 65,
When receiving the read data, the bank control unit (# 1) 23a returns the B-RPY and the bank reply data to the crossbar 22 via the bank reply bus 66 and the bank reply data bus 67, so that no conflict occurs in the crossbar 22. And returns the RPY and the reply data to the pseudo request generation function unit (# 1) 21a via the reply bus 68 and the reply data bus 69, and the reply data comparison unit 2112 causes the reply data and the pre-write data generation unit 2103 to be returned. Is compared with the data (reference value) that has been set and stored. If they differ, it is detected as an error and reported.

The reply counter 2111 is incremented by one each time one reply is returned, and finally becomes “8”. When the above operation is completed, the value of the request counter 2110 and the value of the reply counter 2111 are changed. If different, it is detected as an error.

During the above operation, the ECC circuit is turned on so that the memory bank (#
1) When a failure or failure occurs in 24a, an error can be detected by the ECC circuit.

Thus, a memory test can be performed.

The pseudo request generation function unit 21 of the present invention has been described above in detail. However, the crossbar 22 and the bank control unit 23 in FIG. 1 are well known to those skilled in the art, and detailed description thereof will be omitted. .

[0118]

The first effect is that the function test of the bank controller can be performed by the main memory alone without connecting the processor in the main memory provided with the crossbar.

The reason is that the request input section of the crossbar is provided with a pseudo request generation function, a reply data comparison function, a request counter, and a reply counter for performing a bank control section function test by a pseudo request.

A second effect is that a memory test can be performed on the main storage device alone without connecting a processor in the main storage device including the crossbar.

The reason is that the request input section of the crossbar is provided with a pseudo request generation function for performing a memory test by a pseudo request and an address counter, and a function of checking on the ECC circuit during the memory test.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing a flow of information between blocks.

FIG. 3 is a diagram illustrating an interface between a processor and a main storage device.

FIG. 4 is a diagram illustrating an interface between a crossbar and a bank control unit.

FIG. 5 is a diagram illustrating an interface between a bank control unit and a memory bank.

FIG. 6 is a diagram showing a configuration of a pseudo request generation function unit (a) a part related to output to the crossbar (b) a part related to input from the crossbar

FIG. 7 is a time chart showing a bank control unit functional test by generating a pseudo request (part 1);

FIG. 8 is a time chart showing a bank control unit functional test by generating a pseudo request (part 2).

FIG. 9 is a time chart showing a memory test by generating a pseudo request (part 1).

FIG. 10 is a time chart showing a memory test by generating a pseudo request (part 2).

FIG. 11 is a diagram illustrating a conventional technique.

[Explanation of symbols]

Reference Signs List 1 processor 1a processor (# 1) 1m processor (#m) 2 main storage device 21 pseudo request generation function unit 21a pseudo request generation function unit (# 1) 21m pseudo request generation function unit (#m) 22 crossbar 23 bank control unit 23a Bank control unit (# 1) 23n Bank control unit (#n) 24 Memory bank 24a Memory bank (# 1) 24n Memory bank (#n) 61 RA bus 62 Data bus 63 Bank access data bus 64 Memory bank access bus 65 Read data bus 66 Bank reply bus 67 Bank reply data bus 68 Reply bus 69 Reply data bus 81 Crossbar input RA bus 91 Crossbar input data bus 710 Pseudo request switching signal 711 Bank control unit function test / memory test Replacement signal 2101 RA generator 2102 Command generator 2103 Write data generator 2104 Address generator 2105 Command generator 2106 Address generator 2107 Test switching selector 2108 RA switching selector 2109 Data switching selector 2110 Request counter 2111 Reply counter 2112 Reply data comparison Department

Claims (10)

[Claims] 1. A self-diagnosis method for a main storage device comprising a plurality of memory banks, a plurality of bank controllers for controlling the memory banks, and a crossbar connected to a plurality of processors, wherein the processor, the crossbar, A self-diagnosis method of a main storage device including a pseudo request generation function unit for generating a pseudo request for self-diagnosis during the period. 2. The pseudo request generating function unit generates a pseudo request for performing a function test of the bank control unit and a pseudo request for performing a memory test of the memory bank. Self-diagnosis method of the main storage device as described. 3. The self-diagnosis method of a main storage device according to claim 1, wherein said pseudo request generation function unit has selector means for separating said pseudo request from a processor request issued by said processor. 4. The self-diagnosis method for a main storage device according to claim 1, wherein the pseudo request generation function unit has an address counter for performing a memory access by the pseudo request. 5. The self-diagnosis of the main storage device according to claim 1, wherein the pseudo request generation function unit has means for holding data set by the pseudo request and comparing the data with the reply data. method. 6. The pseudo-request generation function unit includes a request counter that counts the number of issued pseudo requests and a reply counter that counts the number of replies that are the result of the pseudo request. 2. A self-diagnosis method for a main storage device according to claim 1, further comprising means for comparing the value of said reply counter. 7. The pseudo-request generation function unit according to claim 1, further comprising means for performing a memory bank self-diagnosis for checking on an ECC function for a memory bank in the main storage device. Self-diagnosis method of main memory. 8. A self-diagnosis method for a main storage device, comprising: a plurality of memory banks, a plurality of bank controllers for controlling the memory banks, and a crossbar connected to a plurality of processors, wherein the processor, the crossbar, The selector for separating the pseudo request generated by the pseudo request generation function unit and the processor request issued by the processor is switched to the pseudo request side, and the selector for separating the bank control function test and the memory test is provided by the bank control unit function. Switch to the test side, generate a pseudo request for writing, hold the generated write data, write the write data to the set address of the memory bank based on the generated pseudo request, and generate and generate a pseudo request for reading Memory bar based on pseudo request A method of self-diagnosing a main storage device, comprising: reading data from a set address of a link; and comparing data read from the memory bank with held write data. 9. A self-diagnosis method for a main storage device, comprising: a plurality of memory banks; a plurality of bank controllers for controlling the memory banks; and a crossbar connected to a plurality of processors, wherein the processor, the crossbar, The selector for separating the pseudo request generated by the pseudo request generation function unit and the processor request issued by the processor is switched to the pseudo request side, and the selector for separating the bank control unit function test and the memory test is switched to the memory test side. Switching, generating a pseudo request for writing to all addresses of the memory bank, holding the generated write data, checking on an ECC circuit to detect a failure of the memory bank, and performing writing. All addresses of the memory bank based on the pseudo request Write the generated write data, generate a pseudo request for reading from all addresses of the memory bank, read data from all addresses of the memory bank based on the pseudo request for reading, A self-diagnosis method for a main storage device, which comprises comparing data read from a storage device with write data stored therein. 10. A value of a request counter that counts the number of issued pseudo requests and a value of a reply counter that counts the number of replies as a result of the pseudo request are compared. 10. The self-diagnosis method for a main storage device according to claim 8, wherein: