JPH07162138A - Integrated circuit mounting method - Google Patents
Integrated circuit mounting methodInfo
- Publication number
- JPH07162138A JPH07162138A JP5304200A JP30420093A JPH07162138A JP H07162138 A JPH07162138 A JP H07162138A JP 5304200 A JP5304200 A JP 5304200A JP 30420093 A JP30420093 A JP 30420093A JP H07162138 A JPH07162138 A JP H07162138A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- lead terminal
- hole
- electronic circuit
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/306—Lead-in-hole components, e.g. affixing or retention before soldering, spacing means
- H05K3/308—Adaptations of leads
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】集積回路の電子回路基板への実装
方法に関し、特に半田付工程を不要とする密着型リード
端子を用いた実装方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of mounting an integrated circuit on an electronic circuit board, and more particularly to a method of mounting using a contact type lead terminal that does not require a soldering step.
【0002】[0002]
【従来の技術】従来の集積回路の電子回路基板への実装
技術としては、図3(a),(b)に示す様に集積回路
2の有するリード端子6を電子回路基板3に設けられた
スルーホールに挿入した後に、当該スルーホールの導電
部4とリード端子6とを半田5にて付着する方法が大多
数を占めている。2. Description of the Related Art As a conventional mounting technique of an integrated circuit on an electronic circuit board, a lead terminal 6 included in the integrated circuit 2 is provided on the electronic circuit board 3 as shown in FIGS. The majority of the methods are to attach the conductive portion 4 of the through hole and the lead terminal 6 with the solder 5 after the insertion into the through hole.
【0003】また、薄膜状基板への実装方法として、当
該薄膜基板上に形成されたリード端子に対応する導体パ
ターンに集積回路のリード端子を挟みこんで圧着する技
術が特開昭61−121493号公報に開示されてい
る。As a method of mounting on a thin film substrate, a technique of sandwiching and crimping a lead terminal of an integrated circuit with a conductor pattern corresponding to the lead terminal formed on the thin film substrate is disclosed in Japanese Patent Laid-Open No. 61-121493. It is disclosed in the official gazette.
【0004】[0004]
【発明が解決しようとする課題】従来の半田付工程を伴
う方法においては、その工程でフロン又は代替フロンの
様な薬品を使用するために二次的障害が発生したり、設
備に対する保守や品質の面において管理維持に多大なコ
ストがかかるという問題がある。In the conventional method involving a soldering process, a secondary failure occurs due to the use of a chemical such as CFC or a CFC substitute in the process, and maintenance and quality of equipment are reduced. However, there is a problem in that management and maintenance cost a lot of money.
【0005】更に、半田付された集積回路は、その交換
等に係る保守作業においてもその作業性が悪いという問
題がある。Further, the soldered integrated circuit has a problem that its workability is poor even in maintenance work such as replacement.
【0006】また、特開昭61−121493号公報に
開示された方法は、薄膜状の回路基板にのみ適用し得る
技術である。The method disclosed in Japanese Patent Laid-Open No. 61-121493 is a technique applicable only to a thin film circuit board.
【0007】[0007]
【課題を解決するための手段】このような課題は半田付
工程を伴う実装方法にあることに鑑み、本発明に係る集
積回路の実装方法は半田付工程を不要とする。In view of such a problem in a mounting method involving a soldering step, the integrated circuit mounting method according to the present invention does not require a soldering step.
【0008】本発明に係る集積回路の実装方法は、集積
回路のリード端子は、電子回路基板のスルーホールに設
けられた導電部の上部と接触する突起部と、当該リード
端子に端子長方向に沿った縦長の貫通穴を有し、さらに
当該リード端子の形状は、上部寸法が下部寸法より大な
るくさび状をなし、当該リード端子を、電子回路基板の
スルーホールに挿入して当該スルーホールに設けられた
導電部と密着させることにより実装することを特徴とす
る。According to the method of mounting an integrated circuit of the present invention, the lead terminal of the integrated circuit has a protrusion contacting an upper portion of a conductive portion provided in a through hole of an electronic circuit board, and the lead terminal in the terminal length direction. The lead terminal has a wedge shape with an upper dimension larger than a lower dimension, and the lead terminal is inserted into a through hole of an electronic circuit board to form a through hole. It is characterized in that it is mounted by being brought into close contact with the provided conductive portion.
【0009】[0009]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【0010】図1は本発明の一実施例に係るリード端子
を有する集積回路の外観図であり、同図(b)はリード
端子部のみを示す斜視図である。FIG. 1 is an external view of an integrated circuit having lead terminals according to an embodiment of the present invention, and FIG. 1B is a perspective view showing only the lead terminal portion.
【0011】図2は本発明の一実施例を示す図であり、
同図(b)はリード端子を電子回路基板のスルーホール
に挿入した部分の断面図である。FIG. 2 is a diagram showing an embodiment of the present invention.
FIG. 3B is a sectional view of a portion where the lead terminal is inserted into the through hole of the electronic circuit board.
【0012】なお、これらの図及び既に説明した図3に
おいて同一対象物は同一符号で表している。The same object is denoted by the same reference numeral in these figures and in FIG. 3 which has already been described.
【0013】図1(a)に示す集積回路2の有するリー
ド端子1は、同図(b)に示す様に突起部10及び端子
長方向に沿った縦長の貫通穴11を有し、更にその形状
は上部寸法が下部寸法より大なるくさび状をなしてい
る。The lead terminal 1 of the integrated circuit 2 shown in FIG. 1 (a) has a protrusion 10 and a vertically elongated through hole 11 along the terminal length direction, as shown in FIG. 1 (b). The shape is wedge-shaped with the upper dimension larger than the lower dimension.
【0014】このような形状のリード端子1を有する集
積回路2を電子回路基板3に実装したものが図2(a)
に示されている。The integrated circuit 2 having the lead terminal 1 having such a shape is mounted on the electronic circuit board 3 as shown in FIG.
Is shown in.
【0015】図2(b)に示す様に、リード端子1がく
さび状となっているために電子回路基板3のスルーホー
ルへの挿入をガイドし、更にスルーホールに設けられた
導電部4との密着性を持たせている。As shown in FIG. 2B, since the lead terminal 1 has a wedge shape, it guides the insertion of the electronic circuit board 3 into the through hole, and the conductive portion 4 provided in the through hole. It has the adhesiveness of.
【0016】更に、リード端子1をスルーホールに押し
込んだ際に、突起部10が導電部4の上部と接触し、貫
通穴11は内側へのたわみを吸収,反発してより密着性
を高める効果を有している。Further, when the lead terminal 1 is pushed into the through hole, the protrusion 10 comes into contact with the upper portion of the conductive portion 4, and the through hole 11 absorbs the inward deflection and repels the adhesive to further improve the adhesion. have.
【0017】[0017]
【発明の効果】以上述べたように本発明によれば、集積
回路の電子回路基板への実装において半田付作業を不要
とすることができるので、作業の能率向上,品質の向上
および保守性の向上に十分寄与し得る集積回路の実装方
法を提供することができる。As described above, according to the present invention, it is possible to eliminate the need for soldering work when mounting an integrated circuit on an electronic circuit board. Therefore, work efficiency, quality, and maintainability are improved. An integrated circuit mounting method that can sufficiently contribute to improvement can be provided.
【図1】本発明の一実施例に係るリード端子を説明する
図であり、(a)は集積回路の外観図、(b)はリード
端子部のみを示す斜視図。1A and 1B are diagrams illustrating a lead terminal according to an embodiment of the present invention, FIG. 1A is an external view of an integrated circuit, and FIG. 1B is a perspective view showing only a lead terminal portion.
【図2】本発明の一実施例を示す図であり(a)は集積
回路を電子回路基板に実装した状態を示す斜視図、
(b)は図2(a)のA−A断面図。FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 2 (a) is a perspective view showing a state in which an integrated circuit is mounted on an electronic circuit board;
2B is a sectional view taken along line AA of FIG.
【図3】従来の集積回路の実装方法を示す図であり、
(a)は外観図、(b)は図3(a)のB−B断面図。FIG. 3 is a diagram showing a conventional integrated circuit mounting method;
3A is an external view, and FIG. 3B is a sectional view taken along line BB of FIG.
1 リード端子 2 集積回路 3 電子回路基板 4 導電部 5 半田 6 リード端子 10 突起部 11 貫通穴 1 Lead Terminal 2 Integrated Circuit 3 Electronic Circuit Board 4 Conductive Part 5 Solder 6 Lead Terminal 10 Projection 11 Through Hole
Claims (1)
のスルーホールに設けられた導電部の上部と接触する突
起部と、前記リード端子に端子長方向に沿った縦長の貫
通穴を有し、前記リード端子の形状は、上部寸法が下部
寸法より大なるくさび状のリード端子であって、 当該リード端子を電子回路基板のスルーホールに挿入し
て当該スルーホールに設けられた導電部と密着させるこ
とにより実装することを特徴とする集積回路の実装方
法。1. A lead terminal of an integrated circuit has a protrusion that comes into contact with an upper portion of a conductive portion provided in a through hole of an electronic circuit board, and the lead terminal has a vertically long through hole along the terminal length direction. , The lead terminal is a wedge-shaped lead terminal having an upper dimension larger than a lower dimension, and the lead terminal is inserted into a through hole of an electronic circuit board to be in close contact with a conductive portion provided in the through hole. A method of mounting an integrated circuit, which is characterized in that the mounting is performed by
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5304200A JPH07162138A (en) | 1993-12-03 | 1993-12-03 | Integrated circuit mounting method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5304200A JPH07162138A (en) | 1993-12-03 | 1993-12-03 | Integrated circuit mounting method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH07162138A true JPH07162138A (en) | 1995-06-23 |
Family
ID=17930227
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5304200A Pending JPH07162138A (en) | 1993-12-03 | 1993-12-03 | Integrated circuit mounting method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07162138A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10257527A1 (en) * | 2002-12-10 | 2004-06-24 | Marquardt Gmbh | circuit support |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54131868A (en) * | 1978-04-04 | 1979-10-13 | Nec Corp | Electronic apparatus terminal for through-hole |
JPH02201880A (en) * | 1989-01-31 | 1990-08-10 | Junkosha Co Ltd | Circuit device |
JPH0496392A (en) * | 1990-08-14 | 1992-03-27 | Nec Corp | Mounting method for electric component and eyeletused therefor |
JPH04225295A (en) * | 1990-12-26 | 1992-08-14 | Okaya Electric Ind Co Ltd | Method of mounting electronic element and electronic element used therein |
JPH05191025A (en) * | 1992-01-10 | 1993-07-30 | Nec Corp | Method of mounting part on printed wiring board |
-
1993
- 1993-12-03 JP JP5304200A patent/JPH07162138A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54131868A (en) * | 1978-04-04 | 1979-10-13 | Nec Corp | Electronic apparatus terminal for through-hole |
JPH02201880A (en) * | 1989-01-31 | 1990-08-10 | Junkosha Co Ltd | Circuit device |
JPH0496392A (en) * | 1990-08-14 | 1992-03-27 | Nec Corp | Mounting method for electric component and eyeletused therefor |
JPH04225295A (en) * | 1990-12-26 | 1992-08-14 | Okaya Electric Ind Co Ltd | Method of mounting electronic element and electronic element used therein |
JPH05191025A (en) * | 1992-01-10 | 1993-07-30 | Nec Corp | Method of mounting part on printed wiring board |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10257527A1 (en) * | 2002-12-10 | 2004-06-24 | Marquardt Gmbh | circuit support |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19960618 |