JPH07161982A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent channeling phenomenon that implanted ions pass through a gate electrode serving as a mask when a source and a drain of MOS are formed in a self-alighnment manner. CONSTITUTION:A method of manufacturing a semiconductor device comprises a step of forming a gate oxide film 103 on a semiconductor substrate 101; a step of forming a polysilicon gate electrode 104 on a gate oxide film; a step of forming an insulation film 105 on the entire semiconductor substrate; and thereafter a step of implanting ions into the semiconductor substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a MOS field effect transistor.

[0002]

2. Description of the Related Art A conventional semiconductor device generally uses self-alignment in its manufacturing method. This is a technique that enables good alignment of the device and diffusion without causing a problem of exposure mask alignment. For example, in a MOS field effect transistor (hereinafter referred to as MOS), ion implantation is performed using a gate electrode as a mask to form a source / drain diffusion layer. By doing so, the gate electrode and the source / drain diffusion layer can be arranged at the predetermined positions without any problem in the exposure mask alignment.

A conventional method of manufacturing a semiconductor device will be described with reference to FIG. FIG. 3 is a sectional view of the semiconductor device in each step. First, as shown in FIG. 3A, the semiconductor substrate 201
A LOCOS oxide film 202 is formed thereon by a known method. Next, the semiconductor substrate 201 is oxidized to obtain the gate oxide film 2
03, and a gate electrode 204 made of polysilicon is formed. This state is shown in FIG. Then, the polysilicon gate electrode 204 and the oxide film 2
Using 02 and 203 as masks, for example, phosphorus is ion-implanted at a predetermined position and heat-treated to form a phosphorus diffusion layer 206 serving as a source / drain. This state is shown in FIG.
It is (c). After that, the PSG film 2 is formed as a first insulating film.
05 and SOG as a second insulating film for planarization
A film 207 is formed as shown in FIG. 3D, and an interlayer insulating film is arranged. Finally, as shown in FIG. 3E, after opening a contact hole 208 to the semiconductor substrate 201 and the polysilicon gate 204, a wiring 209 such as an aluminum alloy is formed.

[0004]

However, in the above manufacturing method, a phenomenon called channeling has occurred. This is a phenomenon in which ions to be ion-implanted pass through the gate electrode, which is a mask. When this phenomenon occurs, ions are implanted at an unplanned location, which causes a problem that expected characteristics of the semiconductor device cannot be obtained.

Further, in the above manufacturing method, there is a limit to miniaturization of the semiconductor device. The present invention has been made in view of such problems.

[0006]

As a result of earnest research, the inventor of the present invention has found out that the above problems can be solved by only partially changing the order of conventional manufacturing steps, and has completed the invention. That is, the present invention relates to "a step of forming a gate oxide film on a semiconductor substrate, a step of forming a gate electrode on the gate oxide film, and forming an insulating film on the entire semiconductor substrate. And a step of performing ion implantation into the semiconductor substrate after that, the manufacturing method of the semiconductor device ”is provided.

[0007]

When channeling occurs, as shown in FIG. 3C, the diffusion layer 210 is also introduced into the semiconductor substrate 201 which will be the channel region of the MOS, and as a result, the MOS is formed.
Change in the threshold voltage and deterioration of mutual conductance. Further, there is a problem in that variations in various MOSFET characteristics in the wafer are increased and the yield is deteriorated.

Further, in the above manufacturing method, it is difficult to miniaturize the device. This will be described with reference to FIG. After ion implantation using the gate electrode as a mask, heat treatment for carrier activation is performed to form the source / drain 306.
Are also diffused in the lateral direction, and the distance 310 is shorter than the length Lg of the gate electrode 304. However, in order to miniaturize semiconductor devices such as MOS, the gate electrode 204
It is generally performed to shorten the length (gate length). Therefore, the distance between the source and the drain becomes short. Then, when a predetermined voltage is applied to the drain diffusion layer, the punch-through phenomenon in which the depletion layer reaches the source from the drain, the breakdown voltage drop due to impact ionization, the threshold voltage drop, etc. Various problems occur depending on the effect. Therefore, there has been a limit to the miniaturization of the device.

Here, if the acceleration voltage at the time of ion implantation is lowered, the above channeling does not occur. But,
When the accelerating voltage is lowered, the source-drain diffusion resistance rises, so the mutual conductance deteriorates, and new problems such as an increase in the contact resistance between the source-drain diffusion layer and the wiring layer occur. Of. In the present invention, when the ion implantation is performed for forming the source / drain diffusion layer in the MOS, the ion implantation is performed after forming the insulating film on the gate electrode of the MOS. This insulating film is generally arranged as an interlayer insulating film or a protective film,
Conventionally, it is arranged after forming the source / drain. By disposing this insulating film before the ion implantation, the implanted ions are scattered even if the acceleration voltage is high, and the channeling does not occur.

In contrast to the conventional length Lg which is an effective mask for ion implantation, according to the manufacturing method of the present invention, as shown in FIG. It becomes twice as long as the film thickness T. Therefore, the short channel effect such as punch through when the MOS is miniaturized is less likely to occur due to the gate length being increased by 2 × T, and therefore the gate length of the MOS is further reduced. Can be converted.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view of a semiconductor device in each step according to the manufacturing method of the present invention. The manufacturing method of the semiconductor device of the present invention will be described in detail with reference to this drawing. However, the present invention is not limited to this. First, as shown in FIG. 1A, LO is formed on the semiconductor substrate 101 by a known method.
A COS oxide film 102 is formed. Next, the semiconductor substrate 10
1 is oxidized to form a gate oxide film 103, and a polysilicon gate 104 is formed. This state is shown in Figure 1.
It is (b). Next, as shown in FIG. 1C, a PSG film 105 is formed as a first interlayer insulating film by CVD using a CVD method.
Form 0Å. Then, using the polysilicon gate 104 and the oxide films 102, 103 and 105 as a mask, phosphorus is ion-implanted at an implantation amount of 3 × 10 ¹⁵ / cm ² and an acceleration voltage of 70 KeV. Then, heat treatment is performed at 900 ° C. for 30 minutes in a nitrogen atmosphere, and the phosphorus diffusion layer 10 serving as a source / drain is formed.
6 is formed. This state is shown in FIG. Then, the SOG film 107 is formed as a second interlayer insulating film to flatten it. Next, as shown in FIG. 1E, the semiconductor substrate 101 and the polysilicon gate 1
After opening the contact hole 108 to 04, the wiring 109 of aluminum alloy or the like is formed.

The film thickness of the first interlayer insulating film depends on the ion species of the impurities to be implanted, the implantation amount, the accelerating voltage and the species of the first interlayer insulating film. Therefore, it may be set as appropriate according to the process conditions used.

[0013]

As described above, according to the method for manufacturing a semiconductor device of the present invention, the phenomenon of channeling can be suppressed and the short channel effect can be suppressed even if the self-alignment method is used. You can It is also a manufacturing method suitable for miniaturization of semiconductor devices and improvement of yield.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device in each step according to a manufacturing method of the present invention.

FIG. 2 is a sectional view of a semiconductor device showing an effective mask for ion implantation.

FIG. 3 is a sectional view of a semiconductor device in each step of a conventional manufacturing method.

FIG. 4 is a sectional view of a semiconductor device illustrating a short channel effect.

[Explanation of symbols]

 101, 201, 301 ... Semiconductor substrate 102, 202, 302 ... LOCOS oxide film 103, 203, 303 ... Gate oxide film 104, 204, 304 ... Polysilicon gate 105, 205, 305・ ・ ・ First interlayer insulating film 106, 206, 306 ... Source / drain diffusion layer 107, 207 ... Second interlayer insulating film 108, 208 ... Contact hole 109, 209. .... Aluminum alloy wiring 210, 310 ... Phosphorus-implanted layer by channeling

Claims (2)

[Claims] 1. A step of forming a gate oxide film on a semiconductor substrate, a step of forming a gate electrode on the gate oxide film, and a step of forming an insulating film over the entire semiconductor substrate. ,
A method of manufacturing a semiconductor device, comprising a step of implanting ions into the semiconductor substrate thereafter. 2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the gate electrode, a gate electrode containing polysilicon as a main component is formed.