JPH07161811A - Method of forming semiconductor thin film - Google Patents

Abstract

PURPOSE:To form a semiconductor integrated circuit whose integration degree is high without undergoing restriction due to the minimum line width of lithography. CONSTITUTION:A silicon oxide film 14 and a polycrystal silicon film 15 are formed on the surface of a silicon substrate 11 on which a recessed part 11A has been formed. The polycrystal silicon film 15 is left only inside the recessed part 11A. After that, silicon oxide films 17, 18 and the like are formed. A silicon substrate 20 is pasted via a polycrystal silicon film 19. The back of the silicon substrate 11 is ground and polished, to exposure the polycrystal silicon film 15. Thereby, the polycrystal silicon film 15 and the silicon substrate 11 can be separated by the silicon oxide film 14 which is narrower than the minimum line width of lithography.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a semiconductor thin film, for example, SOI (silicon-on-in).
It can be used in the field of manufacturing semiconductor devices.

[0002]

2. Description of the Related Art In recent years, the degree of integration of VLSIs (two-dimensional LSIs) has dramatically improved year by year. However, since the size of the basic element has become submicron or half-micron, it is becoming difficult to miniaturize the element, and the limit of the two-dimensional LSI is beginning to be seen. A three-dimensional semiconductor device (three-dimensional LSI) in which multiple layers of this two-dimensional LSI are laminated with an insulating film is not only high in density with the secondary LSI but also high-speed, multi-functional, and parallel processing of signals. 2D LSI
It is being developed as a product with features not found in. In order to manufacture such a three-dimensional LSI, the SOI technique of forming a single crystal silicon thin film on an insulating film is indispensable.

Conventionally, this type of SOI technology is the first
There is known a method in which an element is formed on an SOI semiconductor thin film made of the first semiconductor substrate by bonding the first semiconductor substrate and the second semiconductor substrate together. This method is a method that can be expected to have various applications because of the advantage that elements can be formed on both sides of the SOI semiconductor thin film.

FIGS. 6A to 7B show a conventional SOI.
FIG. 6 is a sectional view of a key portion, showing a specific method of forming a semiconductor thin film in the order of steps. In the conventional method, first, as shown in FIG. 6A, after applying the resist 2 to the first semiconductor substrate 1,
The resist 2 is patterned on the element formation region 1A by a photolithography technique. And this resist 2
The first semiconductor substrate 1 is, for example, 100 n
Anisotropically etch about m. Next, after removing the resist 2, as shown in FIG. 6B, the surface of the first semiconductor substrate 1 on which the uneven portion is formed is subjected to thermal oxidation to form a silicon oxide film 3. Furthermore, on this silicon oxide film 3,
As shown in FIG. 6C, a silicon oxide film 4 is deposited by the CVD method to have a thickness of 100 nm to 1000 nm, for example. Next, as shown in FIG. 7A, a polycrystalline silicon film 5 is formed by a CVD method, and the polycrystalline silicon film 5 is formed.
The surface of is polished to form a flat bonding surface. Note that FIG.
(A) shows a state after polishing the polycrystalline silicon film 5.

Next, the surface of the second semiconductor substrate 6 is attached to the polycrystalline silicon film 5, and as shown in FIG.
The first semiconductor substrate 1 is ground from the back surface to form a thin film. At this time, the back surface of the first semiconductor substrate 1 is polished using the silicon oxide film 3 in the element isolation region as a stopper to form an SOI layer 1C as shown in FIG. 7B. Here, the polishing is carried out by physical polishing while using a polishing liquid, that is, so-called chemical polishing. At this time,
As shown in FIG. 6B, the SOI layer 1C has the element isolation region 1 corresponding to the width of the recess formed in the step shown in FIG.
B separates it from the adjacent SOI layer 1C. Various semiconductor elements can be formed on the SOI layer 1C thus formed by a known method.

[0006]

Although a single crystal thin film having good film thickness controllability can be formed by the above method of forming an SOI semiconductor thin film, the width of the element isolation region 1B is not limited to exposure light,
The minimum line width is limited by the lithography performance, which consists of factors such as exposure equipment, type of resist and its characteristics. That is, the element isolation region 1 narrower than this minimum line width
There is a problem that B cannot be formed and the degree of integration of the integrated circuit cannot be increased.

The photolithography technology, which has been supporting the improvement in the integration degree of ULSI until recently, is now approaching a corner. This is mainly because the minimum size of ULSI required has become equivalent to the wavelength of light used for exposure. For example, 64MDR under development
In AM, i-line (wavelength: 0.365 μm) is likely to be used as exposure light, but the minimum dimension here is 0.
The main pattern rule is 35 to 0.4 μm. By the way, the i-line has been used in 4M DRAM and 16M DRAM, but the minimum dimensions are 0.8 μm and 0.5 to 0.6 μm, respectively.
And was larger than the wavelength of the exposure light. Therefore, in order to reduce the minimum dimension, the wavelength of the exposure light should be shortened. However, in reality, there are various problems in shortening the wavelength, which cannot be easily realized.

The problem to be solved by the present invention is to obtain a method for forming a semiconductor thin film capable of increasing the degree of integration of a semiconductor integrated circuit without being limited by the minimum line width of a resist pattern formed by lithography. The question is what kind of measures should be taken.

[0009]

According to a first aspect of the present invention, a step of forming a recess on the surface of a first substrate, a step of forming an insulating film along the surface of the first substrate, Forming a semiconductor thin film on the insulating film, and flattening the semiconductor thin film so that the semiconductor thin film remains in the recess;
The solution is to include a step of adhering the second substrate to the front surface side of the substrate via another film, and a step of polishing the back surface of the first substrate to expose the semiconductor thin film.

The invention according to claim 2 of this application is
A step of forming a plurality of recesses on the surface of the first substrate at predetermined intervals, a step of forming an insulating film on the surface of the first substrate, and a step of embedding a semiconductor thin film in a predetermined recess of the recesses. A step of embedding an insulating film in another of the recesses, a step of adhering a second substrate to the front surface side of the first substrate via the other film, and a back surface of the first substrate being polished. And a step of exposing the semiconductor thin film.

[0011]

According to the first aspect of the present invention, at least the insulating film is deposited after the semiconductor thin film is embedded in the concave portion of the surface of the first substrate through the insulating film, and the second substrate is bonded thereon.
Then, by polishing the back surface of the first substrate to expose the semiconductor thin film, the SOI semiconductor thin film can be reliably formed. First
When the substrate is a semiconductor substrate, the exposed semiconductor thin film and the first substrate (semiconductor region) are separated by an insulating film. Therefore, by controlling the thickness of this insulating film (for example, controlling the film forming conditions such as the thermal oxidation condition and the CVD condition), the separation film structure having a width dimension shorter than the limit of lithography can be formed. At this time, the element isolation distance between the semiconductor thin film and the first substrate (which can be formed with the conventional minimum line width) can be narrowed by reducing the thickness of the insulating film to a width that does not cause dielectric breakdown. Therefore, it is possible to increase the degree of integration by forming the elements in the inter-element region, which has been conventionally defined by lithography. In addition, the insulating film between the semiconductor thin film and the first substrate is made shallower (from the thickness of the semiconductor thin film and the first substrate) from the back surface side of the first substrate before the bonding step. By processing it, it becomes possible to form it as a trench isolation or a trench capacitor.

According to the second aspect of the present invention, the semiconductor thin film embedded in the recess serves as an element forming region, and the portion in which the insulating film is embedded can be a complete isolation film or trench isolation.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the method for forming a semiconductor thin film according to the present invention will be described below with reference to the embodiments shown in the drawings.

1A to 1C and 2A to
(C), FIG. 3 (A)-(B), FIG. 4 (A), (B), and FIG. 5 (A), (B) show an embodiment in which the present invention is applied to the formation of an SOI semiconductor thin film. It is a principal part sectional view shown in order of a process.

First, in this embodiment, as shown in FIG. 1 (A), for example, a positive resist 12 is applied on the surface of a silicon substrate 11 as a first semiconductor substrate, and the resist 12 is formed by using a lithography technique. To expose. In FIG. 9A, 13 is an exposure mask, 12A is an exposed portion of the resist, and 12B is an unexposed portion. At this time, an exposure mask is set according to the design circuit so that the boundary between the exposed portion 12A and the unexposed portion 12B of the resist 12 is at the position where the element isolation portion is to be formed. In this embodiment, the minimum line width of the resist is 500 nm, for example.

Next, as shown in FIG. 1B, after the phenomenon of resist is performed, the unexposed portion 12B of the resist 12 is used as a mask as shown in FIG. Anisotropic etching is performed under the conditions, and the recess 11A is formed by anisotropically processing to a depth (for example, 100 nm) obtained by adding a desired film thickness of the element isolation portion to the desired thickness dimension of the semiconductor thin film to be formed. To do. In this example, a μ wave etcher was used for this anisotropic etching.

(Conditions for anisotropic etching) μ wave power: 250 W RF power: 150 W Etching gas: SF ₆ and C ₂ Cl ₃ F ₃ Gas pressure: 0.01 Torr Time: 12 seconds After the resist is peeled off, a silicon oxide film 14 is formed along the surface of the silicon substrate 11 by thermal oxidation or a CVD method so as to have a film thickness of 100 nm, for example, as shown in FIG. Next, as shown in FIG. 2B, the polycrystalline silicon film 15 is deposited by the low pressure CVD method to have a film thickness of, for example, 500 nm. After that, as shown in FIG. 3A, the polycrystalline silicon film 15 is polished flat from the surface using the silicon oxide film 14 as a stopper until the silicon oxide film 14 is exposed. As a result, the polycrystalline silicon film 15 has a structure in which only the recess 11A is filled, as shown in FIG.

After that, a resist 16 is applied on the surface side of the silicon substrate 11, and the resist 16 is patterned by a lithographic technique so as to cover the portion where the polycrystalline silicon film 15 is left. Next, anisotropic etching is performed using the resist 16 as a mask, and then isotropic etching is performed to remove unnecessary portions of the buried polycrystalline silicon film 15.

Next, after removing the resist 16, a silicon oxide film 17 as shown in FIG. 3B is formed on the surface of the polycrystalline silicon 15 by thermal oxidation to a thickness of, for example, 10 nm. As shown in FIG. 3B, a silicon oxide film 18 is deposited by a CVD method to a film thickness of 300 nm, for example, which completely fills the empty recess 11A. Then, a polycrystalline silicon film 19 is deposited on the silicon oxide film 18 by the CVD method and the surface thereof is polished to form a flat bonding surface, as shown in FIG. 3 (C). Next, FIG.
As shown in (A), the silicon substrate 20 as the second substrate is bonded to the bonding surface of the polycrystalline silicon film 19. Note that FIG. 4A shows a state in which the back surface of the silicon substrate 11, which is the first substrate, is faced up. And
After the back surface of the silicon substrate 11 is ground, polishing is performed using the silicon oxide film 14 as a stopper to form a silicon substrate 11 made of single crystal silicon having an SOI structure as shown in FIG. 4B.

Further, a polishing agent having a strong mechanical polishing is used to perform polishing without a selection ratio between the silicon substrate 11 and the silicon oxide film 14, and as shown in FIG. 5A, a polycrystalline silicon film is formed. Expose 15 At this time, the polishing amount is controlled by time, for example. In this way, the silicon substrate 11 of single crystal silicon and the polycrystalline silicon film 15 are separated by the silicon oxide film 14, and each can be formed into an SOI structure.
Here, since the silicon oxide film 14 has a film thickness (width) of 50 nm as described above, the element isolation width is smaller than the minimum line width (500 nm) of lithography. As described above, according to this embodiment, the element isolation region for isolating the element region formed by the SOI structure can be suppressed to be equal to or smaller than the minimum line width of lithography, and the dielectric breakdown does not occur depending on the resolution of lithography. Since the element separation distance can be narrowed to a certain width, the degree of integration of the semiconductor integrated circuit can be increased.

FIG. 5B shows a step of irradiating the laser beam 21 to anneal it to change the polycrystalline silicon film 15 into a polycrystalline silicon film 15A having a large grain size.

Although the embodiments of the present invention have been described above, the present invention can also form a semiconductor thin film structure including a trench isolation and a trench capacitor other than the element isolation portion having such a structure.

In the above embodiment, the recess 11A is filled with polysilicon by the low pressure CVD method.
Conditions may be used, and further, silicon may be epitaxially grown.

Further, although the silicon substrate 20 is used as the second substrate in the above embodiment, a substrate made of another material may be used.

[0025]

As is clear from the above description, according to the present invention, there is an effect of increasing the degree of integration of a semiconductor integrated circuit without being limited by the minimum line width of a resist pattern formed by lithography.

[Brief description of drawings]

FIG. 1A to FIG. 1C are cross-sectional views of essential parts showing steps of an embodiment of the present invention.

FIG. 2A to FIG. 2C are cross-sectional views of essential parts showing the steps of the embodiment of the present invention.

3 (A) to 3 (C) are cross-sectional views of essential parts showing the steps of the embodiment of the present invention.

4A and 4B are cross-sectional views of the essential part showing the steps of the embodiment of the present invention.

5 (A) and 5 (B) are cross-sectional views of essential parts showing the steps of the embodiment of the present invention.

FIG. 6A to FIG. 6C are cross-sectional views of main parts showing the steps of a conventional example.

7A and 7B are cross-sectional views of a main part showing the steps of a conventional example.

[Explanation of symbols]

 11 ... Silicon substrate (first substrate) 11A ... Recessed portion 12 ... Resist 14 ... Silicon oxide film (insulating film) 15 ... Polycrystalline silicon film 15A ... Polycrystalline silicon film 20 ... Silicon substrate (second substrate)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/12 F

Claims (2)

[Claims] 1. A step of forming a concave portion on the surface of a first substrate, a step of forming an insulating film along the surface of the first substrate, and a step of forming a semiconductor thin film on the insulating film, and then forming the inside of the concave portion. And a step of adhering a second substrate to the front surface side of the first substrate via another film, and a back surface of the first substrate is polished to remove the semiconductor thin film. A method of forming a semiconductor thin film, comprising: exposing the semiconductor thin film. 2. A step of forming a plurality of recesses on a surface of a first substrate with a predetermined space therebetween, a step of forming an insulating film on a surface of the first substrate, and a semiconductor in a predetermined recess of the recesses. A step of embedding a thin film, a step of embedding an insulating film in another recess of the recess, a step of adhering a second substrate to the front surface side of the first substrate via another film, A step of polishing the back surface of the substrate to expose the semiconductor thin film.