JPH07161733A - Manufacture of compound semiconductor device - Google Patents

Manufacture of compound semiconductor device

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Publication number
JPH07161733A
JPH07161733A JP30451593A JP30451593A JPH07161733A JP H07161733 A JPH07161733 A JP H07161733A JP 30451593 A JP30451593 A JP 30451593A JP 30451593 A JP30451593 A JP 30451593A JP H07161733 A JPH07161733 A JP H07161733A
Authority
JP
Japan
Prior art keywords
insulating film
semiconductor
layer
hydrogen
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30451593A
Other languages
Japanese (ja)
Inventor
Yusuke Matsukura
祐輔 松倉
Shigeru Kuroda
滋 黒田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP30451593A priority Critical patent/JPH07161733A/en
Publication of JPH07161733A publication Critical patent/JPH07161733A/en
Pending legal-status Critical Current

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  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Chemical Vapour Deposition (AREA)
  • Formation Of Insulating Films (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To obtain the method of forming an insulating film which is not affected by hydrogen passivation of a P-type semiconductor layer, regarding the manufacturing method of an insulating film which is used in a semiconductor device. CONSTITUTION:In the method of manufacturing a semiconductor device wherein a P-type compound semiconductor turns to a part of an operating layer, a first insulating film 2 in contact with the surface of a P-type semiconductor 1 is stuck by a forming method which does not use plasma. A second insulating film 3 is subsequently formed on the first insulating film 2 by laminating, or the formation of the insulating film in contact with the surface of the P-type semiconductor 1 is started at 350 deg.C or higher in a plasma atmosphere containing hydrogen.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置に用いる絶
縁膜の製造方法に関する。近年、携帯型情報通信システ
ムの発達によって、高密度情報伝送が重要となり、マイ
クロ波領域の無線通信装置の需要が増大しつつある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an insulating film used in a semiconductor device. In recent years, with the development of portable information communication systems, high-density information transmission has become important, and the demand for microwave communication devices in the microwave region is increasing.

【0002】このような装置を構成するためには、従来
のシリコンを基本とした半導体装置では周波数特性とし
て不十分であり、より高速動作が可能となるGaAs等
の化合物半導体を用いた装置が必要となってきている。
In order to construct such a device, a conventional semiconductor device based on silicon is insufficient in frequency characteristics, and a device using a compound semiconductor such as GaAs which enables higher speed operation is required. Is becoming.

【0003】[0003]

【従来の技術】化合物半導体を用いたトランジスタは、
現状ではおおむねn型をチャネルとした電界効果トラン
ジスタで,いわゆるエンハンスメント型とデプレッショ
ン型素子によって回路が構成されている。
2. Description of the Related Art Transistors using compound semiconductors are
At present, it is a field-effect transistor whose channel is generally an n-type, and the circuit is composed of so-called enhancement type and depletion type elements.

【0004】しかし、通常このような構成の回路では、
動作時のみならず待機中にも電流が流れ、電力を消費す
るために、携帯型の装置で重要な電池寿命が短くなって
しまうといった問題が生じる。このような欠点を克服す
るため、化合物半導体電界効果トランジスタにおいて
も、シリコン素子での様なp型チャネル素子を開発し、
相補型回路を構成し、待機時の電流消費を削減すること
が重要である。
However, in a circuit having such a structure, normally,
Since a current flows not only during operation but also during standby and consumes power, there arises a problem that an important battery life is shortened in a portable device. In order to overcome such drawbacks, in compound semiconductor field effect transistors, a p-type channel device like a silicon device was developed,
It is important to configure complementary circuits to reduce standby current consumption.

【0005】化合物半導体においても、従来n型の導電
性を持つ素子の製造プロセスは確立されており、またp
型素子とn型素子の構造上の相違は、その動作に本質的
な層の導電性の相違のみであるため、その作成プロセス
は互換性があると考えられている。
Also in the compound semiconductor, a manufacturing process of an element having n-type conductivity has been conventionally established, and p
The fabrication process is believed to be compatible because the only structural differences between the type and n-type elements are the differences in the conductivity of the layers that are essential to their operation.

【0006】[0006]

【発明が解決しようとする課題】しかし、化合物半導体
においては、p型の半導体層は成長中やプロセス中の水
素雰囲気、例えば絶縁膜形成の為のシランプラズマ中の
水素等が層中に取り込まれ、アクセプタと結びついてア
クセプタを不活性化する、いわゆる水素パッシベーショ
ンの影響をn型の半導体層よりも顕著に受け、プロセス
時の絶縁膜形成プロセス後に素子特性が著しく劣化して
しまう。
However, in the compound semiconductor, in the p-type semiconductor layer, hydrogen atmosphere during growth or process, for example, hydrogen in silane plasma for forming an insulating film is taken into the layer. The effect of so-called hydrogen passivation, which is associated with the acceptor and inactivates the acceptor, is more significantly affected than that of the n-type semiconductor layer, and the element characteristics are significantly deteriorated after the insulating film forming process during the process.

【0007】また、この水素パッシベーションによって
不活性化されたアクセプタは、いわゆるアニーリングと
いう加熱処理によって再活性化する事が出来るが、通
常、それに必要な温度は500〜600℃で、層の結晶
成長温度に近く、界面の急峻性を損なう等の問題を生じ
る。
Further, the acceptor inactivated by the hydrogen passivation can be reactivated by a heat treatment called so-called annealing. Usually, the temperature required for it is 500 to 600 ° C., and the crystal growth temperature of the layer. This causes problems such as impairing the steepness of the interface.

【0008】本発明はp型の半導体層の水素パッシベー
ションの影響を受けないような絶縁膜の形成方法を得る
ことを目的とする。
An object of the present invention is to obtain a method for forming an insulating film which is not affected by hydrogen passivation of a p-type semiconductor layer.

【0009】[0009]

【課題を解決するための手段】図1は本発明の原理説明
図、図2は水素プラズマ中におけるp型GaAs基板温
度とキャリア濃度、ならびに水素取り込まれ量の関係を
示す図である。
FIG. 1 is a diagram illustrating the principle of the present invention, and FIG. 2 is a diagram showing the relationship between the p-type GaAs substrate temperature and carrier concentration in hydrogen plasma, and the amount of hydrogen taken in.

【0010】図において、1はp型の半導体、2は第1
の絶縁膜、3は第2の絶縁膜、4は水素を含むプラズマ
である。そこで、発明者は、第一の方法として、化合物
半導体装置の半導体1の表面に直接接する第1の絶縁膜
2をプラズマを用いない方法によって形成し、しかるの
ちに水素を含むプラズマ4を用いた成膜方法によって第
2の絶縁膜3を形成するか、あるいは、第二の方法とし
て、成膜時の温度を高くする(いわゆる同時アニール)
ことによって、半導体1の表面に直接接する絶縁膜への
水素の侵入を減少させる、等の方法により、p型の半導
体1中に侵入する水素を減少させる方法を発明した。
In the figure, 1 is a p-type semiconductor and 2 is a first
Insulating film 3, 3 is a second insulating film, and 4 is plasma containing hydrogen. Therefore, as a first method, the inventor formed the first insulating film 2 that is in direct contact with the surface of the semiconductor 1 of the compound semiconductor device by a method not using plasma, and then used the plasma 4 containing hydrogen. The second insulating film 3 is formed by the film forming method, or the second method is to raise the temperature during film formation (so-called simultaneous annealing).
As a result, a method of reducing hydrogen intrusion into the insulating film which is in direct contact with the surface of the semiconductor 1 and the like has been invented.

【0011】即ち、本発明の目的は、図1(a)に示す
ような、p型の化合物半導体が動作層の少なくとも一部
となる半導体装置の製造方法であって、図1(b)に示
す半導体1の表面に接する第1の絶縁膜2をプラズマを
用いない形成方法で被着し、続いて、図1(C)に示す
第2の絶縁膜3を水素を含むプラズマ4雰囲気中等によ
り第1の絶縁膜2上に積層して形成することにより、或
いは、半導体1の表面に接する絶縁膜を水素を含むプラ
ズマ4の雰囲気中、350℃以上の温度で形成を開始す
ることにより達成される。
That is, an object of the present invention is a method of manufacturing a semiconductor device in which a p-type compound semiconductor is at least a part of an operation layer as shown in FIG. The first insulating film 2 in contact with the surface of the semiconductor 1 shown in the figure is deposited by a forming method that does not use plasma, and then the second insulating film 3 shown in FIG. This is achieved by stacking the first insulating film 2 on the first insulating film 2 or by starting the formation of the insulating film in contact with the surface of the semiconductor 1 at a temperature of 350 ° C. or higher in the atmosphere of the plasma 4 containing hydrogen. It

【0012】[0012]

【作用】図1に示すように、半導体表面に直接接する絶
縁膜をプラズマを用いない方法によって形成することに
より、半導体中への水素の侵入を防ぐ説明図である。
As shown in FIG. 1, it is an explanatory view for preventing hydrogen from penetrating into a semiconductor by forming an insulating film which is in direct contact with the semiconductor surface by a method which does not use plasma.

【0013】図中第1の絶縁膜2は、半導体に直接接す
る絶縁膜であり、水素を含むプラズマを用いない堆積
法、例えば真空蒸着法によって形成する。第2の絶縁膜
3は第1の絶縁膜2を形成したのち、水素を含むガスに
よるプラズマ化学気相堆積法を含む堆積法によって形成
された絶縁膜である。
In the figure, the first insulating film 2 is an insulating film that is in direct contact with the semiconductor, and is formed by a deposition method that does not use plasma containing hydrogen, for example, a vacuum evaporation method. The second insulating film 3 is an insulating film formed by a deposition method including a plasma chemical vapor deposition method using a gas containing hydrogen after forming the first insulating film 2.

【0014】このような絶縁膜堆積法、あるいは絶縁膜
構造を用いると、第1の絶縁膜2の堆積時には、半導体
表面は大量の水素に曝されることがなく、半導体中への
水素の侵入が抑制され、且つ、堆積法によって絶縁膜種
類が限定されるような場合(例えば酸化窒化膜(SiO
N)は真空蒸着法での成膜は困難)においても、第1の
絶縁膜2を水素の侵入を防ぐ為の最小限の膜厚とし、し
かるのちに第2の絶縁膜3を形成することにより、素子
作製プロセスの自由度を損なうことがない。
When such an insulating film deposition method or insulating film structure is used, the semiconductor surface is not exposed to a large amount of hydrogen during the deposition of the first insulating film 2, and hydrogen invades into the semiconductor. Is suppressed and the type of insulating film is limited by the deposition method (for example, oxynitride film (SiO 2
(N) is difficult to form by a vacuum vapor deposition method), the first insulating film 2 has a minimum film thickness for preventing the invasion of hydrogen, and then the second insulating film 3 is formed. Therefore, the degree of freedom in the device manufacturing process is not impaired.

【0015】図2は水素プラズマ中におけるp型GaA
s基板温度と水素の取り込まれ量、ならびにキャリア濃
度の関係を示している。(Watanabe et al.,J.Appl.Phys
Vol.73,p8146(1993) これによれば、基板温度250℃付近で水素取り込まれ
量ならびにキャリア濃度減少が最大となり、基板温度上
昇につれて水素取り込まれ量ならびにキャリア濃度の減
少が少なくなり、350℃以上では、キャリア濃度には
ほとんど変化はない。従って、プラズマを用いた絶縁膜
形成時に、基板温度を350℃以上とする事によって、
試料中への水素の侵入を防ぐ事ができる。また、成膜後
にアニールによってアクセプタを再活性化するのに必要
な温度(500〜600℃)よりも低い温度で素子劣化
が防げるので、界面の急峻性等、結晶の質を低下させる
心配もない。
FIG. 2 shows p-type GaA in hydrogen plasma.
s shows the relationship between the substrate temperature, the amount of hydrogen taken in, and the carrier concentration. (Watanabe et al., J.Appl.Phys
Vol.73, p8146 (1993) According to this, when the substrate temperature is around 250 ° C, the hydrogen uptake amount and the carrier concentration decrease maximally, and as the substrate temperature rises, the hydrogen uptake amount and the carrier concentration decrease less, and 350 ° C Above, there is almost no change in carrier concentration. Therefore, by setting the substrate temperature to 350 ° C. or higher when forming the insulating film using plasma,
It is possible to prevent hydrogen from penetrating into the sample. Further, since element deterioration can be prevented at a temperature lower than the temperature (500 to 600 ° C.) required for reactivating the acceptor by annealing after film formation, there is no fear of degrading crystal quality such as interface sharpness. .

【0016】[0016]

【実施例】図3は本発明の第1の実施例の工程順模式断
面図、図4は本発明の第2の実施例の工程順模式断面図
であるある。
FIG. 3 is a schematic sectional view in order of steps of a first embodiment of the present invention, and FIG. 4 is a schematic sectional view in order of steps of a second embodiment of the present invention.

【0017】図において、5は半絶縁性GaAs基板、
6はHEMT構成層、7はSiO2膜、8はSiON膜、9は
ゲート電極、10はソース電極、11はドレイン電極であ
る。先ず、図3により本発明の第1の実施例について説
明する。
In the figure, 5 is a semi-insulating GaAs substrate,
Reference numeral 6 is a HEMT constituent layer, 7 is a SiO 2 film, 8 is a SiON film, 9 is a gate electrode, 10 is a source electrode, and 11 is a drain electrode. First, a first embodiment of the present invention will be described with reference to FIG.

【0018】図3(a)に示すように、半絶縁性GaA
s基板5上に、バッファ層、チャネル層、正孔供給層、
キャップ層等として、GaAs、AlGaAs層等を交
互にエピタキシャル法により積層して成長し、HEMT
構成層6を得る。
As shown in FIG. 3A, semi-insulating GaA
On the substrate 5, a buffer layer, a channel layer, a hole supply layer,
As a cap layer, etc., GaAs, AlGaAs layers, etc. are alternately laminated and grown by an epitaxial method, and HEMT
The constituent layer 6 is obtained.

【0019】次に、図3(b)に示すように、プラズマ
を用いない成長法等により薄く1000Å程度の二酸化シリ
コン(SiO2)膜をp型GaAs層上に成長する。続いて
図3(c)に示すように、シラン・アンモニア・笑気
(SiH4/NH3/N2O)混合ガスを用いたプラズマ化学気相堆
積法によって酸化窒化シリコン(SiON)膜8を3,000 Å
の膜厚で堆積する。
Next, as shown in FIG. 3B, a thin silicon dioxide (SiO 2 ) film of about 1000 Å is grown on the p-type GaAs layer by a growth method without using plasma. Subsequently, as shown in FIG. 3C, a silicon oxynitride (SiON) film 8 is formed by a plasma chemical vapor deposition method using a mixed gas of silane, ammonia and laughing gas (SiH 4 / NH 3 / N 2 O). 3,000 Å
Deposited at a film thickness of.

【0020】その後、周知の技術を用いてSiO2膜7とSi
ON膜8の積層された絶縁膜に開口部を形成し、HEMT
構成層6のゲート領域をエッチングしてキャップ層を形
成し、その上にリセス構造のゲート電極9を形成し、同
時にソース電極10、ドレイン電極11をHEMT構成層6
のキャップ層上に形成してHEMTを完成する。
After that, the SiO 2 film 7 and the Si are
An opening is formed in the insulating film in which the ON film 8 is laminated, and HEMT
The gate region of the constituent layer 6 is etched to form a cap layer, and the gate electrode 9 having a recess structure is formed on the cap layer. At the same time, the source electrode 10 and the drain electrode 11 are formed on the HEMT constituent layer 6
Is formed on the cap layer to complete the HEMT.

【0021】次に、図4により本発明の第2の実施例に
ついて説明する。図4(a)に示すように、半絶縁性G
aAs基板5上に、バッファ層、チャネル層、正孔供給
層、キャップ層等として、GaAs、AlGaAs層等
を交互にエピタキシャル法により積層して成長し、HE
MT構成層6を得る。
Next, a second embodiment of the present invention will be described with reference to FIG. As shown in FIG. 4A, semi-insulating G
As a buffer layer, a channel layer, a hole supply layer, a cap layer, etc., GaAs, AlGaAs layers, etc. are alternately laminated and grown on the aAs substrate 5 by an epitaxial method.
The MT constituent layer 6 is obtained.

【0022】次に、図4(b)に示すように、シラン・
アンモニア・笑気(SiH4/NH3/N2O)混合ガスを用いたプ
ラズマ化学気相堆積法によって基板温度を例えば400
℃とした条件でSiON膜8を3,000 Åの膜厚でHEMT構
成層6の上に堆積する。
Next, as shown in FIG.
The substrate temperature is set to, for example, 400 by the plasma chemical vapor deposition method using a mixed gas of ammonia and laughing gas (SiH 4 / NH 3 / N 2 O).
A SiON film 8 having a film thickness of 3,000 Å is deposited on the HEMT constituent layer 6 under the condition of ° C.

【0023】その後、周知の技術を用いてSiON膜8に開
口部を形成し、HEMT構成層6のゲート領域をエッチ
ングしてキャップ層を形成し、その上にリセス構造のゲ
ート電極9を形成し、同時にソース電極10、ドレイン電
極11をHEMT構成層6のキャップ層上に形成してHE
MTを完成する。
After that, an opening is formed in the SiON film 8 by a well-known technique, the gate region of the HEMT constituting layer 6 is etched to form a cap layer, and a gate electrode 9 having a recess structure is formed thereon. At the same time, the source electrode 10 and the drain electrode 11 are formed on the cap layer of the HEMT constituting layer 6 and HE
Complete MT.

【0024】[0024]

【発明の効果】以上説明したように、本発明によれば、
水素パッシベーションによる素子特性の劣化のない、p
型の能動層を持つ化合物半導体が得られる効果があり、
化合物半導体集積回路を始めとする化合物半導体素子製
造に寄与するところが大きい。
As described above, according to the present invention,
P does not deteriorate element characteristics due to hydrogen passivation
Has the effect of obtaining a compound semiconductor having a positive active layer,
It greatly contributes to the production of compound semiconductor devices such as compound semiconductor integrated circuits.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の原理説明図FIG. 1 is an explanatory view of the principle of the present invention.

【図2】 水素プラズマ中におけるp型GaAs基板温
度とキャリア濃度、ならびに水素取り込まれ量の関係
FIG. 2 shows the relationship between the p-type GaAs substrate temperature and carrier concentration in hydrogen plasma, and the amount of hydrogen taken up.

【図3】 本発明の第1の実施例の工程順模式断面図3A to 3C are schematic cross-sectional views in order of the processes of the first embodiment of the present invention.

【図4】 本発明の第2の実施例の工程順模式断面図FIG. 4 is a schematic cross-sectional view in order of the steps of a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 p型の半導体 2 第1の絶縁膜 3 第2の絶縁膜 3' 絶縁膜 4 水素を含むプラズマ 5 半絶縁性GaAs基板 6 HEMT構成層 7 SiO2膜 8 SiON膜 9 ゲート電極 10 ソース電極 11 ドレイン電極1 p-type semiconductor 2 first insulating film 3 second insulating film 3'insulating film 4 plasma containing hydrogen 5 semi-insulating GaAs substrate 6 HEMT constituent layer 7 SiO 2 film 8 SiON film 9 gate electrode 10 source electrode 11 Drain electrode

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/203 Z 8719−4M 21/316 X 7352−4M 29/778 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 21/203 Z 8719-4M 21/316 X 7352-4M 29/778

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 p型の化合物半導体が動作層の少なくと
も一部となる半導体装置の製造方法であって、 半導体(1) の表面に接する第1の絶縁膜(2) をプラズマ
を用いない形成方法で被着し、続いて、第2の絶縁膜
(3) を該第1の絶縁膜(2) 上に積層して形成することを
特徴とする化合物半導体装置の製造方法。
1. A method of manufacturing a semiconductor device in which a p-type compound semiconductor is at least a part of an operating layer, wherein a first insulating film (2) in contact with a surface of a semiconductor (1) is formed without using plasma. Method and then a second insulating film
A method for manufacturing a compound semiconductor device, comprising: forming (3) on the first insulating film (2).
【請求項2】 p型の化合物半導体が動作層の少なくと
も一部となる半導体装置の製造方法であって、 半導体(1) の表面に接する絶縁膜(3')を水素を含むプラ
ズマ(4) の雰囲気中で350℃以上の温度で形成を開始
することを特徴とする化合物半導体装置の製造方法。
2. A method for manufacturing a semiconductor device in which a p-type compound semiconductor is at least a part of an operation layer, wherein a plasma (4) containing hydrogen in an insulating film (3 ′) in contact with the surface of a semiconductor (1). In the atmosphere, the formation is started at a temperature of 350 ° C. or higher, and the method for manufacturing a compound semiconductor device.
JP30451593A 1993-12-06 1993-12-06 Manufacture of compound semiconductor device Pending JPH07161733A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30451593A JPH07161733A (en) 1993-12-06 1993-12-06 Manufacture of compound semiconductor device

Applications Claiming Priority (1)

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JPH07161733A true JPH07161733A (en) 1995-06-23

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990064934A (en) * 1999-05-25 1999-08-05 이환철 Fabrication method of an insulating films for MIS electronic devices
KR20110136827A (en) * 2009-04-08 2011-12-21 이피션트 파워 컨버젼 코퍼레이션 Compensated gate misfet and method for fabricating the same
CN105609408A (en) * 2015-12-23 2016-05-25 上海华虹宏力半导体制造有限公司 Forming method of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990064934A (en) * 1999-05-25 1999-08-05 이환철 Fabrication method of an insulating films for MIS electronic devices
KR20110136827A (en) * 2009-04-08 2011-12-21 이피션트 파워 컨버젼 코퍼레이션 Compensated gate misfet and method for fabricating the same
JP2012523701A (en) * 2009-04-08 2012-10-04 エフィシエント パワー コンヴァーション コーポレーション Compensated gate MISFET and manufacturing method thereof
CN105609408A (en) * 2015-12-23 2016-05-25 上海华虹宏力半导体制造有限公司 Forming method of semiconductor device

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