JPH07154301A - Spread spectrum signal demodulator - Google Patents

Abstract

PURPOSE:To synchronize spread codes with a simple device. CONSTITUTION:The spread code from a spread code generator 16 is forcively changed by a shift register control circuit 48. Then, the spread code from the spread code generator 16 and a received signal are multiplied by a multiplier 10 for inverse spread, and the power of a provided signal is detected by a power detector 40. When the provided power is larger than a prescribed value, it is detected that the spread code to be multiplied by the multiplier is synchronized with a spread signal in the received signal, the shift control circuit 48 is disconnected, and the device is operated as a normal DLL.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum signal demodulation device for demodulating a signal spread spectrum by a predetermined spread code.

[0002]

2. Description of the Related Art Conventionally, various wireless communication systems have been proposed, and a spread spectrum communication system is one of them. In this spread spectrum communication system (particularly, direct spread system), the transmission side multiplies the primary modulation signal modulated by the information signal by a spread code to obtain a spread spectrum signal. Then, the spectrum-spread signal is wirelessly transmitted. On the other hand, on the receiving station side, the received signal is despread by multiplying it by a spreading code, the received signal is returned to a primary modulated signal, and this is demodulated to obtain an information signal. As described above, in the spread spectrum communication method, since the spread spectrum signal is wirelessly communicated, it is possible to perform communication while eliminating interference with radio communication by radio waves of a predetermined frequency.

Here, in the spread spectrum communication system, the received signal must be despread. For this despreading, the spreading code generated on the receiving side must be multiplied by the spreading code in the received signal (reception spreading code) in synchronization.

As one of such demodulating means, there is a delay lock loop (hereinafter referred to as DLL). As shown in FIG. 4, the DLL performs despreading by multiplying a received signal by a spreading code in a despreading multiplier 10. The spread code (PN (pseudo noise) code in this example) to be multiplied by the received signal in the despreading multiplier 10 must be synchronized with the spread code superimposed on the received signal. Therefore, in this device, the two multipliers 12 and 14 multiply the received signals by the PN codes at different timings. In this example, P
Two PN codes generated by the N code generator 16 and different by one bit are supplied to the multipliers 12 and 14.

Envelope detectors 18 and 20 detect the envelopes of the obtained signals, and obtain correlation outputs 1 and 2. The correlation outputs 1 and 2 are at a high level when they are synchronized. Therefore, as shown in FIG.
As shown in (B), a triangular wave which becomes high level when synchronized and which becomes 0 when shifted by 1 bit or more is output from the envelope detectors 18 and 20. And
The two triangular waves are shifted by one bit and are input to the comparator 22. When the difference between the two triangular waves is taken in the comparator 2, a correlation signal as shown in FIG. 5C is obtained.

The output of the comparator 22 is the low-pass filter 2
4, the phase of the output signal is input to the voltage controlled crystal oscillator (VCXO) 26 whose phase is controlled by the input voltage.
Therefore, the phase of the output signal of the voltage controlled crystal oscillator 26 is controlled according to the output voltage of the comparator 22. The output signal of the voltage controlled oscillator 26 is the PN code generator 16
Since it is the output control clock of, the timing of the PN code output from the PN code generator 16 is changed according to the output of the comparator 22. Therefore, with this operation,
P so that the output of the comparator 22 reaches the point a in FIG.
The output from the N code generator 16 will be controlled.

Here, the point a is located in the middle of the synchronization points of the outputs of the two 1-bit shifted PN codes which are the outputs of the PN code generator 16. The time corresponding to 1 bit of the PN code is 1T (chip), and the signal of which the phase of the PN code generator 16 is advanced is (1/2) T.
By delaying by T / 2 by the delay device 28, a PN code synchronized with the received signal can be obtained. So this P
Despreading can be performed by supplying the N code to the despreading multiplier 10.

In this way, the DLL can despread the signal spectrum-spread with the predetermined PN code,
Can demodulate signals.

[0009]

However, such D
The LL can effectively perform follow-up control for shifts of 1 bit or less, but cannot follow when shifts of 1 bit or more are out of synchronization. Therefore, another device is required for the initial synchronization acquisition. As such a device, a sliding correlator that detects a correlation output while changing the phase of the PN code to be multiplied and stops the phase change when a predetermined correlation output is output is used. Therefore, the conventional device requires a large number of correlators,
There is a problem that the device becomes complicated.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a spread spectrum signal demodulating device which can surely synchronize spread codes with a simple device.

[0011]

The present invention is a spread spectrum signal demodulating device for demodulating a signal spread spectrum by a predetermined spread code, and a spread code generating circuit for generating two spread codes having different phases. , The first and second multipliers for multiplying the received signal by the two spread codes generated in the spread code generating circuit, respectively, and the difference between the output signals from the first and second multipliers Detecting a phase difference, controlling means for controlling the generation of the spreading code in the spreading code generating circuit according to the detected difference, and forcible changing means for forcibly changing the spreading code generated in the spreading code generating circuit, Phase adjusting means for adjusting one phase of the spread code output from the spread code generating circuit;
According to the despreading multiplier that multiplies the spread signal whose phase has been adjusted by the phase adjusting means and the received signal, and the output level of the despreading multiplier and the first or second multiplier, And an operation control means for controlling the operation of the forced change means.

[0012]

According to the present invention, the spreading code generated in the spreading code generating circuit can be changed by the forced changing means. Then, the output level of the despread signal at that time is monitored while changing the spreading code for performing the despreading by the forced changing means, and when this level becomes equal to or higher than the predetermined value, it is confirmed that the synchronization is achieved. Detect and perform initial acquisition of spreading code in received signal. Then, when the initial capture is performed, the operation of the forced change means is prohibited and the control means operates the normal DLL. In this way, by using the compulsory changing means, the spreading code generating means in the DLL is controlled,
Since the initial acquisition is performed, the entire apparatus can be simplified to achieve effective initial acquisition and tracking of synchronization.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the entire system of the present embodiment. A received signal is input to a despreading multiplier 10 for despreading as in the conventional example, and here, a synchronized spreading code (PN) is used. Code) is performed to obtain a despread signal (primary modulated signal). Then, by demodulating this, an information signal can be obtained.

The multipliers 12 and 14 respectively multiply the received signal by the two PN codes supplied from the PN code generator 16 and shifted by one bit. Then, the envelopes of the two signals obtained by the two envelope detectors 18 and 20 are detected, and the comparator 22 obtains the difference between the detection result signals. As described above, this output becomes a triangular wave as shown in FIG. 5, so the signal of the obtained difference is output to the low-pass filter 2
The oscillation frequency of the voltage-controlled crystal oscillator 26 is controlled by supplying it to the voltage-controlled crystal oscillator 26 via No. 4.

The output signal of the voltage-controlled crystal oscillator 26 whose oscillation frequency is controlled by the voltage of the signal supplied from the low-pass filter 24 is supplied to the PN code generator 16 and the phase of the PN code generated from it is supplied. Is controlled.

Here, the PN code generator 16 is constituted by a shift register which shifts the data of the PN code stored therein one by one bit by the signal pulse from the voltage controlled crystal oscillator 26 and circulates the data. Has been done. Then, the signal stored in the register 16 of the n-th bit and the register of the (n-1) -th bit of the spread code generator 16 (hereinafter referred to as shift register 16) is multiplied by the multiplier 1.
2 and 14, respectively. Therefore, the multiplier 12,
The PN code different by 1 bit is supplied to 14 according to the oscillation frequency of the voltage controlled crystal oscillator 26. Note that any bit signal of the shift register 16 may be supplied to the despreading multiplier 10 if the corresponding phase adjustment is performed.

Therefore, if the phase difference between the PN code in the received signal and the PN code generated from the shift register 16 is within 1 bit, the oscillation frequency of the voltage controlled crystal oscillator 26 is the PN code in the received signal. To follow, n
-T / 2 of the signal stored in the 1st bit register
The signal delayed by only becomes a signal synchronized with the PN code in the received signal, and the despreading multiplier 10 despreads the PN code. In this way, in this embodiment, the DLL is configured as in the conventional example.

In this embodiment, the power detector 40 for detecting the output of the despreading multiplier 10 is provided. The power detector 40 detects the power level in the output signal of the despreading multiplier 10 by rectifying the output signal of the despreading multiplier 10 and integrating it with a predetermined time constant. This power level becomes large when the PN code multiplied by the despreading multiplier 10 and the PN code in the received signal are synchronized.

The output of the power detector 40 is input to a comparator 42 and a comparator 44, where it is compared with a predetermined reference voltage. The output of the power detector 40 being equal to or higher than the reference voltage means that the PN code multiplied by the despreading multiplier 10 and the PN code in the received signal are synchronized.

On the other hand, the output of the comparator 42 is the switch 46.
Is supplied to the shift register control circuit 48 via the. Further, the switch 46 is turned on / off by the signal of the comparison result of the comparator 44, and the shift register control circuit 48 is PN in the PN code generator 16 formed of a shift register by the signal of the comparator 42 supplied via the switch 46. Controls code generation.

That is, the comparator 44 is the power detector 40.
According to the output from, when the detected power is small, the switch 46 is turned on, and when the detected power is a predetermined value or more, the switch 46 is turned off. The comparator 42 outputs a control signal when the power detected by the power detector 40 is below a predetermined value. Therefore, the shift register control circuit 48 controls so that the output from the PN code generator 16 changes at a predetermined clock according to the output control signal of the comparator 42. The timing of this change is earlier than the clock of the normal PN code. Further, in this embodiment, the shift register control circuit 4
8 generates a PN code for several cycles in one shift of the normal PN code. Further, this signal generation is not performed by shifting the PN code generator 16, but is performed by supplying the PN code for all bits from the shift register control circuit 48 at a required cycle. Of course, this output may be performed from the PN code generator 16 by supplying a predetermined shift clock.

In this way, when the power detected by the power detector 40 is less than or equal to the predetermined value, the output from the shift register 16 is controlled by the output of the shift register control circuit 48. Therefore, when the PN code from the shift register 16 is not synchronized with the PN code in the received signal, the output from the shift register 16 is controlled by the shift register control circuit 48.

When the synchronization deviation between the PN code generated from the shift register 16 and the PN code in the received signal becomes 1 bit or less, the predetermined power (triangular wave) is reversed as shown in FIG. It is output from the spreading multiplier 10. Therefore, it is recognized that the generation of this power causes the bit deviation of the spreading code to be multiplied in the despreading multiplier 10 to be within 1 bit, and the switch 46 is operated to prohibit the operation of the shift register control circuit 48. To do. That is, when the bit shift is within 1 bit, by controlling the shift register 16 by the output of the comparator 22, the PN code generated from the shift register 16 and the PN code in the received signal are The synchronization can be preferably maintained. Therefore, thereafter, the phase of the PN code output from the shift register 16 is controlled by the signal from the voltage controlled crystal oscillator 26.

That is, the output of the power detector 40 is output when the bit deviation between the PN code multiplied by the despreading multiplier 10 and the PN code in the received signal is within 1 bit as shown in FIG. growing. And FIG. 5 (C)
As shown in (3), when the bit shift is within 1 bit, the DLL operates as desired. Therefore, the power detector 4
When the output of 0 detects that it is within the range of t2 in FIG. 2, the process shifts to tracking by DLL. During the period of t1 and t3 in FIG. 2, the switch 46 is turned on to perform the initial capture.

As described above, according to the present embodiment, the output of the power detector 40 causes a phase shift of 1 bit between the PN code to be multiplied in the despreading multiplier 10 and the PN code in the received signal. Detect that you are within. If the phase shift is within 1 bit, the DLL
The PN code in the received signal is tracked by. Therefore, the initial acquisition of the PN code in the received signal can be performed at high speed, and thereafter the DLL can perform reliable tracking.

Then, according to the present embodiment, the initial acquisition is performed by controlling the spread code generated from the shift register 16 constituting the DLL. Therefore, it is possible to simplify the configuration of the entire apparatus and effectively perform the initial supplement and tracking of the PN code. In the embodiment of FIG. 1, the output signal of the despreading multiplier 10 is set to the power detector 4.
Although synchronous or asynchronous is detected by applying 0, the same detection can be performed by applying the output of the first or second multiplier 12 or 14 to the power detector 40.

Next, FIG. 3 shows another embodiment. In this embodiment, the output of the power detector 40 is fed to the digital processing circuit 5
Supply to 0. The digital processing circuit 50 A / D converts the input signal, controls the switch 46 by this value, and supplies a control signal to the shift register control circuit 48 when this value is less than a predetermined value. It consists of Therefore, the digital processing circuit 50 includes the two comparison circuits 42 and 4 in the above-described embodiment.
The same process as 4 is performed. Therefore, also in this embodiment, the same operation and effect as in the above case can be obtained.

[0028]

As described above, according to the spread spectrum signal demodulating device of the present invention, the operation control means operates the forcing changing means to force the spreading code generated from the spreading code generator in the DLL. , And the initial acquisition of synchronization for the spread code is performed. Then, when the initial acquisition is successful, normal tracking is performed by the DLL.
Therefore, the entire apparatus can be simplified and effective initial acquisition and tracking of synchronization can be achieved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment.

FIG. 2 is a waveform diagram showing an output of the power detector 40.

FIG. 3 is a block diagram showing the overall configuration of another embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional DLL.

FIG. 5 is a waveform diagram showing the waveform of each part in the DLL.

[Explanation of symbols]

 10 Despreading Multiplier 12, 14 Multiplier 16 Spreading Code Generator 22, 42, 44 Comparator 48 Shift Register Control Circuit

Claims (1)

[Claims] 1. A spread spectrum signal demodulating device for demodulating a signal spread spectrum by a predetermined spread code, comprising: a spread code generating circuit for generating two spread codes having different phases; and a spread code generating for a received signal. 2 generated in the circuit
First and second multipliers for multiplying two spreading codes respectively, and a difference in phase between the two signals is detected from a difference between output signals from the first and second multipliers, and spreading is performed according to the detected difference. Control means for controlling the generation of the spread code in the code generation circuit, forced change means for forcibly changing the spread code generated in the spread code generation circuit, and one phase of the spread code output from the spread code generation circuit. Of despreading means for multiplying the received signal with the spread code whose phase is adjusted by the phase adjusting means, and the despreading multiplier of the first or second multiplier. A code spread signal demodulation device comprising: an operation control unit that controls the operation of the forced change unit according to an output level.