JPH07153949A - Mos transistor - Google Patents

Abstract

PURPOSE:To obtain the output signals for the number of channels by forming the rear of a MOS gate in N-type and P-type multilayer structure, forming a plurality of the channels of N channels and P channels in different depth and shaping drains and sources for each channel. CONSTITUTION:A P-type layer 3 and an N-type region 2 on the layer 3 are formed onto an N-type substrate. A square MOS gate 1 consisting of an SiO2 layer is and an electrode 1M composed of aluminum, etc., is formed onto the N-type layer region 2. P<-> regions 3S, 3D are shaped on the left and right sides of the square MOS gate 1, and used as the source and drain of a P-type MOS transistor. N<+> regions 2S, 2D are formed on the upper and lower sides of the square MOS gate 1, and employed as the source and drain of an N-type MOS transistor. The MOS transistor constitutes one gate of three channels and the MOS transistor having two outputs. When the MOS gate 1 is supplied with an input signal, output signals can be acquired in the drain 2D and source 2S of the N-type MOS transistor and the drain 3D and source 3S of the P-type MOS transistor.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a MOS transistor suitable for use in various electronic circuits.

[0002]

2. Description of the Related Art Generally, in a MOS transistor, one source electrode and one drain electrode are provided for one gate electrode, and one source electrode and one drain electrode are provided when an input signal is supplied to this gate electrode. Only two output signals could be taken out.

Therefore, in a digital circuit using a large number of MOS transistors, for example, the pattern of the MOS transistors becomes large, resulting in a large area.

In view of the above problems, an object of the present invention is to make it possible to reduce the pattern of MOS transistors in a digital circuit, for example.

[0005]

In the MOS transistor of the present invention, as shown in FIGS. 1, 2 and 3, for example, N-type and P-type multilayer structures 2 and 3 are provided on the back side of the MOS gate 1 and N having different depths. A channel and a P channel are formed, and a drain and a source are formed in each channel.

Further, according to the present invention, in the above-mentioned MOS transistor, an input signal is supplied to the MOS gate 1 and output signals of the number of channels can be taken out.

Further, the MOS transistor of the present invention, for example, as shown in FIG. 4, in the above, supplies a constant voltage to the MOS gate 1, supplies an input signal to one of the above-mentioned channels, and takes out an output signal from the other channel. It was done like this.

Further, the MOS transistor of the present invention is, for example, as shown in FIG. 4, in the above description, it controls the constant voltage supplied to the MOS gate 1 to control the threshold voltage of this channel.

[0009]

According to the present invention, the back surface of the MOS gate 1 has a multi-layered structure of N type and P type, and N channel and P of different depth
Since a plurality of channels are formed, and a drain and a source are formed respectively, by supplying an input signal to this MOS gate 1, an output signal of this channel number can be obtained, and the pattern of the MOS transistor can be obtained accordingly. Can be made smaller.

Further, according to the present invention, a constant voltage is supplied to the MOS gate 1 of the MOS transistor, and an input signal is supplied to one of the plurality of channels.
Output signals can be obtained from other channels. Further, in this case, the threshold voltage Vth of each channel can be adjusted by adjusting the constant voltage supplied to the MOS gate 1.

[0011]

Embodiments of the MOS transistor of the present invention will be described below with reference to the drawings. 2 and 3,
Reference numeral 4 denotes an N-type substrate made of, for example, silicon.
A P-type layer 3 is formed on a substrate having a shape of 3, and a region 2 of an N-type layer is formed on the P-type layer 3.

On the region 2 of the N-type layer, a quadrilateral MOS comprising a SiO ₂ layer 1S and an electrode 1M made of aluminum, polycrystal or the like.
Gate 1 is formed. In this case, an N channel forming an N-type MOS transistor is formed in the region 2 of the N-type layer on the back side of the MOS gate 1, that is, the lower side, and the P-type layer 3 is formed.
A P channel that forms a P-type MOS transistor is formed in.

Also, in FIG. 1 of this rectangular MOS gate 1.
As shown in FIG. 2, P is shown on the left and right sides. ⁺Regions 3S and 3D
Forming a source and a drain of a P-type MOS transistor.
1 and the rectangular MOS gate 1 shown in FIG.
On the bottom and N as shown in FIG.⁺Form areas 2S and 2D
The source and drain of the N-type MOS transistor.
It

The potentials in the depth direction of the P-channel and the N-channel when the voltages V ₁ , V ₂ and V ₃ are supplied to the MOS gate 1 of the MOS transistor as shown in FIGS. 5 and FIG. 6, the MOS transistors shown in FIGS. 1, 2 and 3 constitute a 3-channel 1-gate, 2-output MOS transistor. In this example, the P channel of the interface is not used and the remaining 2
It is configured to use one channel.

In this example, when an input signal is supplied to the MOS gate 1, output signals can be obtained at the drain 2D and source 2S of the N-type MOS transistor and the drain 3D and source 3S of the P-type MOS transistor, respectively. An output signal can be obtained.

FIG. 4 shows another embodiment of the present invention.
The example of FIG. 4 is constructed as shown in FIGS.
In the MOS transistor, keep the MOS gate 1 at a constant voltage.
Pressure V ₃Grounded via a battery 5 that supplies
The input signal is supplied to the source 2S that constitutes the OS transistor.
I will supply it.

At this time, as shown in FIG. 7, the potential of the source 2S fluctuates due to this input signal, and the amount of current flowing through this N channel changes, and along with this, the P channel forming the P type MOS transistor. Of the P-type MOS transistor constituting the output circuit is also modulated.

In this case, when an input signal is supplied to the source 3S constituting the P-type MOS transistor and a constant voltage V ₁ is supplied to the MOS gate 1 and the N-type MOS transistor is used as an output circuit, as shown in FIG. It can be easily understood that the same operation as described above is performed.

Further, in FIG. 4, by adjusting the constant voltage supplied to the MOS gate 1, the N type and P
-Shaped MOS transistor threshold voltage Vt
h can be adjusted.

In this embodiment, the back side, that is, the lower side of the MOS gate 1 has the two-layer structure of N type and P type as described above to form N type and P type MOS transistors having different depths.
By supplying an input signal to the OS gate 1, two output signals can be obtained, and when this is applied to a MOS transistor which constitutes a digital circuit, the area can be reduced by that much.

In the above embodiment, the MOS gate 1
The N-type has a two-layer structure of one layer 2 and P-type one layer 3 on the back side of this, and this is provided with two or more N-type and P-type layers alternately as shown in FIG. Sources 2S ₁ , 2S ₂ , ... 2S _n , 3S ₁ , 3 are formed in a layered structure corresponding to each layer.
S ₂ , ... 3S _n , drain 2D ₁ , 2D ₂ , ... 2D
_n , 3D ₁ , 3D ₂ , ... 3D _n may be provided. It can be easily understood that the same effects as those of the above embodiment can be obtained in this case as well.

Further, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

[0023]

According to the present invention, the back side of the MOS gate 1 is N
Since a plurality of channels of N-channel and P-channel having different depths are formed as a multi-type structure of P-type and P-type and a drain and a source are formed respectively, the number of channels can be increased by supplying an input signal to the MOS gate 1. Output signal can be obtained, and MO in a digital circuit or the like can be obtained.
There is an advantage that the pattern area of the S transistor can be reduced.

Further, according to the present invention, it is possible to obtain a MOS transistor in which a constant voltage is supplied to the MOS gate, an input signal is supplied to one of the plurality of channels, and an output signal is obtained from the other channels.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of a MOS transistor of the present invention.

2 is a cross-sectional view of FIG.

FIG. 3 is a vertical cross-sectional view of FIG.

FIG. 4 is a plan view showing another embodiment of the present invention.

5 is a diagram used to explain FIG. 1. FIG.

FIG. 6 is a diagram used to explain FIG.

FIG. 7 is a diagram used to explain FIG.

FIG. 8 is a diagram used to explain FIG.

FIG. 9 is a plan view showing another embodiment of the present invention.

[Explanation of symbols]

1 MOS gate 1S SiO ₂ layer 1M electrode 2 N type layer 2S, 3S source 2D, 3D drain 3 P type layer 4 N type substrate 5 battery

Claims (4)

[Claims] 1. The back of the MOS gate has a multi-layered structure of N-type and P-type, and N-channel and P-channel having different depths are formed, and a drain and a source are formed in each channel. MOS transistor to do. 2. The MOS transistor according to claim 1, wherein an input signal is supplied to the MOS gate, and output signals corresponding to the number of the channels can be taken out. 3. The MOS transistor according to claim 1, wherein a constant voltage is supplied to the MOS gate, an input signal is supplied to one of the channels, and an output signal is taken out from the other channel. And MOS transistor. 4. The MOS transistor according to claim 3, wherein a constant voltage supplied to the gate is controlled to control a threshold voltage of the channel.