JPH07153283A - Control circuit for non-volatile memory - Google Patents

Abstract

PURPOSE:To obtain a control circuit for a non-volatile memory which can input address data in parallel even if an EPROM having large storage capacity is incorporated in a microcomputer having less terminal pins. CONSTITUTION:Address data AO-A9 of an EPROM 28 is divided with a unit of two bits, analog voltage corresponding to divided address data is generated, and this circuit is constituted so that the divided address data can be restored by taking analog voltage in a microcomputer 24 through one terminal 23. Therefore, address data can be inputted in parallel even if an EPROM having large storage capacity is incorporated in a microcomputer having less terminal pins.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory control circuit suitable for reducing the number of terminal pins of an EPROM (non-volatile memory) built-in microcomputer.

[0002]

2. Description of the Related Art Generally, a mask ROM built-in microcomputer for mass production operates according to information obtained by decoding the program data stored in the mask ROM. By the way, since the mask ROM has memory cells corresponding to "0" and "1" of program data burned on the chip, the program data cannot be modified again. Therefore, it is necessary to check in advance so that there is no error in the program data.
Therefore, an EPROM built-in microcomputer capable of writing and reading program data, which has substantially the same function as a mass-production microcomputer, is used.
After writing the program data in the PROM, the program data is read and various functions are executed to correct errors in the program data.

Now, the EPROM built-in microcomputer realizes the check of the program data by transferring the address data and the program data in parallel. However, due to the chip area of the microcomputer, it may not be possible to secure a sufficient number of terminal pins corresponding to the storage capacity of the EPROM. For example, when an EPROM having a storage capacity of 1 Kbyte in which address and program data are set to 10 bits and 8 bits is built in a microcomputer capable of arranging only 18 terminal pins and parallel transfer is realized, To handle address data, program data, control signals (chip enable signal, output enable signal, EPROM mode signal), and power supply (Vdd, Vss),
Since a total of 23 terminal pins are required, there is a problem that the microcomputer cannot input address data in parallel. Therefore, when the EPROM is built in the microcomputer, the address data is serially input and the program data is calibrated.

[0004]

However, there is a problem in that the peripheral circuit of the EPROM in the microcomputer is complicated because a means for converting the address data into parallel after inputting the address data serially is required. Further, there is a problem that the writing and reading time of the EPROM becomes long, and it takes a lot of time to calibrate the program data. Further, a general-purpose PROM writer for parallel input of address data cannot be used, and a dedicated PROM writer for serially input of the address data is required, which requires a large amount of money to calibrate the program data.

Therefore, an object of the present invention is to provide a non-volatile memory control circuit capable of parallel input of address data even when an EPROM having a large storage capacity is built in a microcomputer having a small number of terminal pins. To do.

[0006]

The present invention has been made to solve the above-mentioned problems, and is characterized in that it has a built-in non-volatile memory capable of writing and reading program data. In the microcomputer, the address data of the non-volatile memory is divided into units of at least 2 bits, and decoding means for decoding the divided address data and an analog voltage corresponding to the divided address data are generated according to the output of the decoding means. Analog voltage generating means, first reference voltage generating means for generating a first reference voltage, and first comparing means for comparing the analog voltage and the first reference voltage and outputting the most significant bit of the divided address data. A second reference voltage generating means for generating a second reference voltage that changes according to the output of the first comparing means; Comparing the log voltage and the second reference voltage, a second comparing means for outputting the lower bits immediately after the most significant bit of the divided address data, in that with a.

[0007]

According to the present invention, the address data of the non-volatile memory is divided into at least two bit units, an analog voltage corresponding to the divided address data is generated, and the analog voltage is supplied to the microcomputer via one terminal. It is structured such that the divided address data can be restored by being taken in. Therefore, even when a non-volatile memory having a large storage capacity is built in a microcomputer having a small number of terminal pins, address data can be input in parallel.

[0008]

The details of the present invention will be described in detail with reference to the drawings. FIG. 1 shows a control circuit of the nonvolatile memory of the present invention. The nonvolatile memory is an EPROM having a storage capacity of 1 Kbyte in which address and program data are set to 10 bits and 8 bits, respectively, and is integrated in the microcomputer.

In FIG. 1, (1), (2) and (3) are resistors, which are connected in series between a power source Vcc (5V) and ground. (4) is an analog voltage generating circuit,
Divided address data A9A8, A7A6, A5A4 obtained by dividing the address data A0 to A9 of the PROM into 2 bits,
The analog voltage corresponding to A3A2 and A1A0 is generated. Inside the analog voltage generation circuit (4), (5), (6), (7) and (8) are NAND gates (decoding means), and the divided address data A9A8, A7.
A6, A5A4, A3A2, A1A0 can each be 4
NAND gates (5) (6) (7) depending on the type value
It is wired so that any one output of (8) becomes a low level. Therefore, when the values of the divided address data change to "11", "10", "01", and "00", respectively, the outputs of the NAND gates (5), (6), (7), and (8) sequentially become low level. become. (9) (10) (11) (1
2) is a transmission gate, one end of which is connected to each connection point of the resistors (1), (2) and (3) and the other end of which is commonly connected, and NAND gates (5) (6) (7)
It opens and closes according to the output of (8). That is, the transmission gates (9) (10) (11) (12)
Opens only one of the NAND gates (5), (6), (7) and (8) according to the output, and derives the connection point voltage of the resistors (1) (2) (3) corresponding to the transmission gate. To do. The transmission gates (9), (10), (11) and (12) are 5V and 3.12, respectively.
The values of the resistors (1), (2) and (3) are set so that 5V, 1.875V and 0V can be derived.

(13) and (14) are resistors (first reference voltage generating means), which are connected in series between the power source Vcc and the ground. The values of the resistors (13) and (14) are made equal so that the first reference voltage appearing at the connection point of the resistors (13) and (14) becomes Vcc / 2 (2.5V). (15) is an address data restoring circuit, which restores the divided address data corresponding to the analog voltage. Inside the address data restoring circuit (15), (16) is a P-type comparator (first comparing means), and the + (non-inverting input) terminal is a transmission gate (9) (10).
Commonly connected to the other ends of (11) and (12), and the- (inverting input) terminal is connected to the connection point of the resistors (13) and (14). That is, the P-type comparator (16) compares the analog voltage and the first reference voltage, and when the analog voltage is higher than the first reference voltage, “1” (5V), and the analog voltage is the first voltage.
The higher bits A9, A7, A5, A3, A1 of the divided address data which become "0" (0V) when lower than the reference voltage are output. (17), (18) and (19) are resistors (second reference voltage generating means), and the resistors (17) and (18) are power sources V.
Connected in series between cc and ground, the resistor (19) is the output terminal of the P-type comparator (16) and the resistor (17) (1
It is connected between the connection points of 8). That is, when the output of the P-type comparator (16) is 5V, the resistance (17) (1
9) are connected in parallel, and when the output of the P-type comparator (16) is 0V, the resistors (18) and (19) are connected in parallel.
When the output of the P-type comparator (16) is 5V, the second reference voltage appearing at the connection point of the resistors (17), (18) and (19) is 5V derived from the transmission gates (9) and (10) and 3. Voltage between 125V (eg 3.75
V) and when the output of the P-type comparator (16) is 0V, the second reference voltage appearing at the connection point of the resistors (17), (18) and (19) is the transmission gate (1).
1) The resistance (17) (1) is set so that the voltage (for example, 1.25V) between 1.875V and 0V derived from (12) is obtained.
8) The value of (19) is set. (36) and (37) are N-type MOSFETs, which are connected between the resistors (18) and (14) and the ground. That is, the N-type MOSFET (3
6) In (37), the resistance (1) is set only when the control signal EPM for setting the EPROM to the write / read state is "1".
3) Current is supplied to (14), (17), (18) and (19) to reduce current consumption. (20) is a P-type comparator (second comparing means), the + terminal is commonly connected to the other ends of the transmission gates (9), (10), (11) and (12), and the-terminal is a resistor (17) (18). )
It is connected to the connection point of (19). That is, the P-type comparator (20) compares the analog voltage and the second reference voltage, and "1" when the analog voltage is higher than the second reference voltage and "0" when the analog voltage is lower than the second reference voltage. Lower order bit A8 of the divided address data,
It outputs A6, A4, A2 and A0. Since the P-type comparators (16) and (20) form a differential pair and a current source using P-type MOSFETs, the power supplies Vcc to (Vcc-α).
There is a so-called dead zone in which analog voltages in the range can not be compared. α is about 1.5V. Therefore, the P-type comparators (16) and (20) use a power source (Vcc + α) obtained by boosting the power source Vcc to eliminate the dead zone. (21)
Reference numeral (22) is an N-type MOSFET, which is connected between the power supply (Vcc + α) of the P-type comparators (16) and (20) and the ground. That is, the N-type MOSFET (21) (2
2) is turned on when the control signal EPM for setting the EPROM to the write / read state is "1" to put the P-type comparators (16) and (20) in the operating state. The analog voltage generating circuit (4) is provided outside the microcomputer and the address data restoring circuit (15) is integrated inside the microcomputer with one terminal (23) as a boundary.

The operation of FIG. 1 will be described below. First, when a command to put the EPROM into a write / read state is executed, the control signal EPM becomes "1", so the N-type MOSF
ET (21) (22) is turned on and the P-type comparator (1
6) In (20), the comparison operation can be executed. For example, the divided address data A1A0 will be described, particularly when the divided address data is “10”.
In this case, since the output of the NAND gate (6) becomes "0", the transmission gate (10) opens to 3.1.
Derive 25V. Inside the microcomputer, first, the P-type comparator (16) outputs 5V because the analog voltage 3.125V is higher than the first reference voltage 2.5V.
Is output. Therefore, the upper bit A1 of the divided address data is "1" and the second reference voltage is 3.75V. Next, the P-type comparator (20) outputs the analog voltage 3.1.
Since 25V is lower than the second reference voltage 3.75V, 0V is output. Therefore, the lower bit A0 of the divided address data
Becomes "0". From the above, by providing only one terminal (23), it is possible to restore the 2-bit divided address data after converting it to an analog voltage.

FIG. 2 shows an application circuit using the control circuit of the nonvolatile memory of the present invention. 1 and 2, the same components are denoted by the same reference numerals, and the description thereof will be omitted. In FIG. 2, reference numeral (24) is a microcomputer, and only 18 terminal pins can be arranged according to the size of the chip area. Reference numeral (25) is a booster circuit, which boosts the power supply Vcc to (Vcc + α) when an instruction to put the EPROM into a write / read state, which will be described later, is executed. The booster circuit (25) is externally connected to the microcomputer (24). (26)
Is a high voltage detecting circuit, which sets the control signal EPM to "1" when the level of the boosted power source (Vcc + α) is detected. The high voltage detection circuit (26) is integrated in the microcomputer (24). The booster circuit (25) and the high voltage detection circuit (26) are connected via a terminal (27). The address data restoration circuit (15) starts its operation only after the boosted power supply (Vcc + α) and the control signal EPM of "1" are applied. Reference numeral (28) is an EPROM having a storage capacity of 1 Kbyte and having address data A0.
The program data is written to and read from designated addresses A to A9. The EPROM (28) is integrated in the microcomputer (24). The EPR
The OM (28) has terminals (2) for applying the power supplies Vcc and Vss.
9) (30), a terminal (31) for applying a chip enable signal * CE, a terminal (32) for applying a high voltage Vpp or an output enable signal * OE, and eight terminals for inputting / outputting program data D0 to D7 (33) is connected. That is, in the EPROM (28), the chip enable signal * CE is "0" and the high voltage Vpp is "1" (12
At the time of V), the output of the NOR gate (34) becomes "0", so that the transmission gate (35) is closed and the program data D0 is assigned to the designated addresses of the address data A0 to A9.
~ D7 is ready for writing. Also, the EPR
The chip enable signal * CE of the OM (28) is "0".
And when the output enable signal * OE is "0",
Since the output of the NOR gate (34) becomes "1", the transmission gate (35) opens and the address data A
The program data D0 to D7 can be read from the designated addresses 0 to A9.

By the way, the address data A0 to A9 are
It is divided into 5 parts like A9A8, A7A6, A5A4, A3A2 and A1A0. Therefore, five analog voltage generation circuits (4) and address data restoration circuits (15) are required. The five analog voltage generating circuits (4) and the address data restoring circuit (15) have five terminals (23).
Connected through. Therefore, even when only 18 terminal pins of the microcomputer (24) can be arranged, the address data A0 to A9 can be input in parallel.

From the above, the address data A0 to A9 of the EPROM (28) is divided into 2-bit units, and the divided address data A9A8, A7A6, A5A4, A3A2,
The divided address data A9A8, A7A6, A5A4, A3A2, A3 are generated by generating an analog voltage corresponding to A1A0 and taking the analog voltage into the microcomputer (24) through the five terminals (23).
I am trying to restore 1A0. Therefore, an EPRO with a large storage capacity can be used in a microcomputer with a small number of terminal pins.
Address data can be input in parallel even when M is incorporated.

[0015]

According to the present invention, the address data of the non-volatile memory is divided into units of at least 2 bits, an analog voltage corresponding to the divided address data is generated, and the analog voltage is passed through one terminal. The divided address data can be restored by importing it into the microcomputer. Therefore, even when a non-volatile memory having a large storage capacity is built in a microcomputer having a small number of terminal pins, address data can be input in parallel. Therefore, the peripheral circuit of the nonvolatile memory can be prevented from becoming complicated, the program data of the nonvolatile memory can be calibrated in a short time, and a general-purpose PROM writer can be used.

[Brief description of drawings]

FIG. 1 is a diagram showing a control circuit of a nonvolatile memory of the present invention.

FIG. 2 is a diagram showing an application circuit using a control circuit of the nonvolatile memory of the present invention.

[Explanation of symbols]

 (4) Analog voltage generator (5) (6) (7) (8) NAND gate (13) (14) (17) (18) (19) Resistor (16) (20) P-type comparator (23) Terminal (24) Microcomputer (28) EPROM

Claims (2)

[Claims] 1. A microcomputer having a built-in non-volatile memory capable of writing and reading program data, wherein the address data of the non-volatile memory is divided into at least 2 bit units, and a decoding means for decoding the divided address data. An analog voltage generating means for generating an analog voltage corresponding to the divided address data according to an output of the decoding means; a first reference voltage generating means for generating a first reference voltage; the analog voltage and the first reference voltage; And a second reference voltage generating means for generating a second reference voltage that changes according to the output of the first comparing means, the analog voltage, The second reference voltage is compared, and the lower bit immediately after the most significant bit of the divided address data is compared. And a second comparison means for outputting the output of the non-volatile memory. 2. At least the first and second comparing means are integrated in a microcomputer, and the output of the analog voltage generating means and the input of the first and second comparing means are connected via one terminal. The control circuit for a non-volatile memory according to claim 1, wherein: