KR100769799B1 - Flash memory device - Google Patents

Abstract

The present invention relates to a flash memory device for implementing a multi-level cell, wherein an input / output terminal for one address is connected to each of a plurality of page buffers for storing read data or program data of a plurality of memory cells for each cell. When the data of the cell is read, the data of the cell is divided and stored in the plurality of page buffers, and the data stored in the page buffers are output through the same input / output terminals according to different addresses, and the data to the cells. In the case of programming, a flash memory device capable of improving a read speed and a program speed by storing data in the plurality of page buffers using different input / output terminals according to an address and then programming the data in a corresponding cell is provided.

Flash memory device, multi-level cell, program, read

Description

Flash memory device             

1 is a state diagram of a single level cell.

2 is a state diagram of a multi-level cell.

3 is a schematic diagram of a NAND type flash memory device for implementing a conventional multi-level cell.

4 is a schematic diagram of a NAND type flash memory device for implementing a multi-level cell in accordance with the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device. In particular, an input / output terminal for one address is connected to each of a plurality of page buffers for storing read data or program data of a plurality of memory cells for each cell. The present invention relates to a flash memory device for implementing multi-level cells that can improve speed.

In NAND flash memory devices, the multi-level cell method is a breakthrough method that doubles the data storage capability of a chip by storing two bits of data information in one cell. That is, the 512M flash memory device has a data storage capacity of 1G. 1 illustrates a state of a single level cell, and FIG. 2 illustrates a state of a multi level cell. A single level cell requires eight cells to store one byte of information, while the multi-level cell of FIG. 2 requires four cells. As described above, in order to implement a multi-level cell, two bits of data must be stored in one cell, and for this purpose, the cell must have four threshold voltages.

3 is a schematic diagram of a NAND-type flash memory device for implementing a conventional multi-level cell. As illustrated, a plurality of memory cells M100 to M115 are connected to one bit line BL0 and BL1 and are driven according to the first selection signal DSL and the second selection signal SSL. The bit line is selected by two NMOS transistors N11 and N12. The bit lines BL0 and BL1 are connected to the first and second page buffers 11 and 12, and the first and second page buffers 11 and 12 are connected to the first and second input / output terminals IO0 and IO1. Each is connected.

In a conventional NAND flash memory device configured to implement a multi-level cell configured as described above, a process of processing data of one cell is simultaneously processed by different input / output terminals for the same address. For example, when reading the first cell M100 of the first bit line BL0, after sensing 2-bit information of the first cell M100, the information is stored in the first and second page buffers 11 and 12. Each). Information stored in the first page buffer 11 is output through the first input / output terminal I / O0, and information stored in the second page buffer 12 is output through the second input / output terminal I / O1. In this manner, the byte mode device can read one byte of data into four cells. That is, one byte of information can be output to only four cells using one address.

On the other hand, when writing data to the first cell (M100) may be performed in the opposite path to the read. First, information input to the input / output terminal is stored in the page buffer. Information input through the first input / output terminal I / O0 is stored in the first page buffer 11 and the second input / output terminal I / O1. Information input through the second page buffer 12 is stored. As such, the information input through the first to eighth input / output terminals I / O <0: 7> is stored in the first to seventh page buffers, respectively. The 2-bit information stored in the first and second page buffers 11 and 12 is programmed to have any one of four states corresponding to the first cell M100. As a result, all one byte is stored in four cells.

As described above, in the NAND-type flash memory device for implementing a multi-level cell, a data storage time is longer than that of a single-level cell because a process of processing data of one cell is simultaneously processed by different input / output terminals for the same address. It takes a lot of data, and the data reading speed is also slowed down. Although the device with the multi-level cell has many advantages in terms of cost, it is difficult to mass-produce due to the disadvantage of the longer program and read time.

An object of the present invention is to provide a flash memory device for implementing a multi-level cell that can improve the program speed and the read speed.

Another object of the present invention is to provide a flash memory device for implementing a multi-level cell that can improve program speed and read speed by dividing and processing two bits of information twice according to an address.

The flash memory device according to the present invention is configured such that an input / output terminal for one address is connected to each of a plurality of page buffers for storing read data or program data of a plurality of memory cells for each cell. When reading, data of the cell is divided and stored in the plurality of page buffers, and the data stored in the page buffer is output through the same input / output terminal according to a different address, and when inputting data to the cell, other input / output according to an address The data may be stored in the plurality of page buffers using a terminal and then programmed in a corresponding cell.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

4 is a schematic diagram of a NAND type flash memory device for implementing a multi-level cell according to the present invention. As illustrated, a plurality of memory cells M200 to M215 are connected to one bit line BL0 and BL1 and are driven according to the first selection signal DSL and the second selection signal SSL. The bit line is selected by two NMOS transistors N21 and N22. The bit lines BL0 and BL1 are connected to the first and second page buffers 21 and 22, and the first and second page buffers 21 and 22 are respectively connected to the first input / output terminals of the first and second addresses. Connected. In the present invention configured as described above, in the conventional method for implementing a multi-level cell, the processing speed of the program and the reading speed are improved by using eight cells with two addresses for processing one byte with four cells at the same address.

When the first cell M200 of the first bit line BL0 is read by the first address add0, 2-bit information of the first cell M200 may be stored in the first page buffer 21 and the second page buffer. Stored at 22. The first page buffer 21 is connected to the first input / output terminal (I / O0 of add0) of the first address, and the second page buffer 22 is the first input / output terminal (I / O0 of add1) of the second address. Is connected to. That is, the eight input / output terminals I / 0 <0: 7> of the first address add0 to be read are connected to eight page buffers, and the eight page buffers are connected to eight cells, thereby providing one byte of data. Outputs However, one byte of data of the second address, which is the next address, is output without the read sensing process of the upper bit data of each of the eight cells already read at the first address. This results in a 50% reduction in read time while processing the same amount of data with the same number of cells as the conventional multi-level cell method.

The process of programming data in the first cell M200 has a different program loop according to the address. First, the program order according to the address proceeds from the low address in 16 rows. That is, when the row address increases from the first cell M200 to the sixteenth cell M215, the program is executed in the order from the first cell M200 to the sixteenth cell M215. In contrast, when the sixteenth cell M215 has a low row address, the program is executed from the sixteenth cell M215 to the first cell M200. In the structure of programming the first cell M200 from the first cell M200 to the sixteenth cell M215, the first page buffer 21 of the first page buffer 21 is programmed. The first cell M200 is programmed with the program data. In the conventional multi-level cell method, the program time can be drastically reduced as compared to the structure in which the program is executed in three stages from the 00 state to the 11 state in the worst case. Next, if one byte is to be programmed by the second address add1, eight one-byte cells of the first address add0 are selected again, and verification of cells already programmed is performed first. Taking only the first input / output terminal I / O0 as an example, the first cell M200 is programmed according to the program data stored in the second page buffer 22 of the second address add1. If the data stored in the second page buffer 22 is program data and the first cell M200 at the first address add0 is verified, the cell is programmed up to 10 states. If the verification result is 01, the program is executed up to 11. By using such a multilevel cell method by dividing the address, it is possible to drastically reduce the time required for a significant program time such as verifying every intermediate step while the program is executed in three steps in the conventional multilevel cell method. After that, the reading and the program for the following addresses are repeated as above.

As described above, according to the present invention, the data read time and the program time can be drastically reduced by changing the method of simultaneously processing from the same address to different input / output terminals in the conventional multi-level cell method.

Claims (1)

A flash memory device for implementing a multi-level cell, An input / output terminal for one address is connected to each of a plurality of page buffers for storing read data or program data of a plurality of memory cells for each cell, and when reading data of the cell, data of the cell Is stored in the plurality of page buffers and the data stored in the page buffer is output through the same input / output terminal according to a different address, and when the data is programmed into the cell, the plurality of pages using different input / output terminals according to the address Flash memory device, characterized in that the data stored in the buffer and then programmed in the cell.

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