JPH07152905A - Image data processor - Google Patents

Abstract

PURPOSE:To provide the image data processor capable of easily performing various image processes as to an image data processor which processes normal input image data and performs image processing for the top-bottom and right- left inversion, enlargement, reduction, etc., of a screen based upon the input image data. CONSTITUTION:An address generation part 16 which determines the write addresses and read addresses of data to a memory part 12 consists of a write address generation part 17, a read address generation part 18, a write/read switching part 19, and an address control part 20; and the write address generation part 17 generates increasing and decreasing addresses by up counters 23 and 25 and down counters 24 and 25 and the address control part 20 selects the increasing or decreasing addresses. Then the write address order of data is controlled to control the write addresses of the data, thereby inverting and rotating the image.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data processing device, and more particularly, it processes ordinary input image data and performs image processing such as up / down, left / right inversion, enlargement / reduction of a screen based on the input image data. The present invention relates to an image data processing device.

With the spread of image display devices in recent years, there has been an increasing demand for display devices with larger capacity and higher definition.
In order to meet this demand, along with efforts to increase the number of display dots of a single display device, a plurality of medium-definition display devices (for example, 640 × 480 dots) which are relatively easy to manufacture are arranged vertically and horizontally to display one screen. A multi-display device that realizes a large capacity by configuring has been proposed. In particular, an attempt has been made to realize a multi-display device by enlarging the display screen of a direct type liquid crystal panel (for example, diagonal 10.4 inch size) as a display device beyond the frame portion (non-display portion) of the panel by using optical means. ing.

With respect to a multi-display device using such a liquid crystal panel, in order to minimize the image enlargement ratio of the image by the optical means and suppress the deterioration of the image quality due to the enlargement, the image layout required when the panel arrangement is devised. There is a demand for image data processing such as inversion processing and image data processing necessary for enlarging and displaying an input image on a multi-display device.

[0004]

2. Description of the Related Art Conventionally, as a method of constructing a multi-screen in which a large number of screens are arranged vertically and horizontally, a method of arranging a plurality of CRT screens as they are or arranging a plurality of rear projection display devices using CRTs or liquid crystal panels Is proposed.
However, it is difficult to make the joint thin by the method of arranging the CRT screen.

FIG. 25 shows a block diagram of a rear projection device. Four
One display device 201 constitutes one screen. The display device 201 has a liquid crystal panel 203 arranged in a pivot body 202,
A lamp 204 is arranged on the rear surface of the liquid crystal panel 203, and a magnifying lens 205 is arranged on the front surface. The image on the liquid crystal panel 203 is magnified by the magnifying lens 205 and projected on the display surface 206.

However, in the method using the rear projection device,
There is an inconvenience that the depth is thick. On the other hand, in recent years, a multi-display device has been devised which uses a direct-viewing type liquid crystal panel and an optical system with a short focus so that the depth is thin and the seams are not conspicuous.

FIG. 26 is a block diagram of a multi-display device using a direct-viewing type liquid crystal panel and a short focus optical system.

A plurality of liquid crystal panels 211 are connected to the liquid crystal panel 21.
A back light 212 is arranged on the back surface of No. 1 and an erecting imaging lens array 213, a magnifying lens 214 and a screen 215 are arranged on the front surface.

In the method using such a direct-viewing type liquid crystal display panel, the display screen is slightly enlarged beyond the frame portion of the panel by the short focus optical system to join the images, but the enlargement ratio at this time is as much as possible. The small size is advantageous in improving the image quality. Therefore, when a multi-screen is configured with four panels, two panels vertically and horizontally, as shown in FIG. 26B, the narrow side of the frame portion where the driver IC 216 of the liquid crystal panel 211 is not mounted is arranged close to each other. It is possible to do it. At this time, in the method using the rear projection device, the arrangement of the unit units is the same, the scanning directions are the same for each unit, for example, the first data is displayed from the upper left, and sequentially proceeds to the right on the same horizontal line. After scanning one line, proceed to the line one step below, and at the end, complete the data transfer display at the bottom right, and regarding image data transfer, distribute the data in the same scanning direction to each unit and supply it. However, in the method of arranging and using the direct-viewing type liquid crystal display panel as shown in the figure, the scanning direction of the image data differs depending on the panel. Therefore, the input image data corresponds to the panel arrangement. It is necessary to control the scanning direction.

[0010]

However, there is no conventional image data processing device for converting ordinary image data to be suitable for this type of multi-display device, and the input image data itself is generated in an order suitable for the multi-display device. Data processing on the data sending side becomes complicated, and
Since it can be connected only to a device capable of generating data suitable for a multi-display device, its application range is narrow and it is not practical.

The present invention has been made in view of the above points, and it is an object of the present invention to provide an image data processing apparatus which can easily perform image processing such as up / down / left / right inversion, enlargement / reduction.

[0012]

FIG. 1 shows the principle of the present invention. The memory unit 1 stores the input image data. The address generator 2 generates an address designating a storage device for the input image data in the memory 1, and supplies it to the memory 1.

The address control unit 3 controls the address generation unit 2 and controls the output order of the input image data by controlling the designation order of the addresses generated by the address generation unit 2.

[0014]

According to the present invention, since the address specifying unit can be controlled by controlling the address generating unit by the address control unit, the output order of the input image data can be controlled. Display conversion processing such as up / down / left / right inversion and enlargement / reduction of the obtained image can be performed.

[0015]

FIG. 2 is a block diagram of the first embodiment of the present invention. In the figure, T _IN1 is an input terminal to which input image data is serially supplied from the outside.

The input terminal T _IN1 is connected to the serial / parallel converter 11 and supplies the supplied serial input image data to the serial / parallel converter 11. The serial / parallel converter 11 converts the supplied serial image data into parallel data. The parallel input image data converted by the serial / parallel conversion unit 11 is supplied to the memory unit 12.

The memory unit 12 is composed of a semiconductor memory device such as a RAM, and stores a data unit 13 for storing data, a row address input unit 14 for specifying a row address of the data unit 13, and a column address of the data unit 13. The column address input unit 15 is provided. The parallel input image data supplied from the serial / parallel conversion unit 11 is stored in the address designated by the row address input unit 14 and the column address input unit 15 of the data unit 13 in the write cycle, and the row address input unit 14 in the read cycle. And are read out in the order of addresses designated by the column address input unit 15.

The data read from the data section 13 is supplied to the parallel / serial conversion section 16. parallel/
The serial conversion unit 16 converts the data read from the memory unit 12 into serial data. A control terminal T _C1 is connected to the parallel / serial conversion unit 16, and the shift direction can be switched according to the shift direction control signal supplied to the control terminal T _C1 .

In addition, the address generation unit 1 is included in the row address input unit 14 and the column address input unit 15 of the memory unit 12.
The address is supplied from 6. The address generation unit 16 includes a write address generation unit 17 that generates a write address, a read address generation unit 18 that generates a read address, a write / read switching unit 19 that switches the supply of the write address and the read address to the memory unit 12, and a write address. The write address control unit 20 controls the designated order of the.

The write address generator 17 is a write column address generator 21 for generating a write column address,
It comprises a write row address generation unit 22 for generating a write row address. The write column address generation unit 21 is an up counter 2 that generates column addresses that sequentially rise.
3 and a down counter 24 that generates a column address that sequentially decreases. The write row address generator 22 is composed of an up-down counter 25 that generates row addresses that sequentially rise and a down counter 26 that generates row addresses that sequentially descend.

The rising column address, the falling column address, the rising row address, and the falling row address generated by the write address generating unit 17 are supplied to the address control unit 20. The address controller 20 is a column address controller 27 that switches between a rising column address and a falling column address.
And a row address control unit 28 that switches between a rising row address and a falling row address.

The column address controller 27 has a rising column address and a down counter 2 from the up counter 23.
4, the falling column address is supplied, and the column address switching control signal is supplied from the control terminal T _C2 . The column address control unit 27 selectively outputs either the ascending column address or the descending column address according to the column address switching control signal supplied from the control terminal T _C2, and supplies it to the write / read switching unit 19.

Also, the row address control unit 28 is updated.
From the counter 25, ascending low address and down count
The falling row address is supplied from the controller 26 and the control end
Child T _C3Further, the row address switching control signal is supplied. B
-Address control unit 28 has control terminal T_C3Supplied by
ー Raising low address or falling according to the address switching signal
Select one of the row addresses to output and write / read
It is supplied to the output switching unit 19.

The writing / reading switching unit 19 includes a column address writing / reading switching unit 29 and a row address writing / reading unit.
The read switching unit 30 is included. The column address write / read switching unit 29 is supplied with the write column address selectively output by the column address control unit 27 and the read column address from the read address generation unit 18, and the write control signal from the control terminals T _C4 and T _C5. A read control signal is provided. The column address write / read switching unit 29 selectively outputs either the write column address or the read column address according to the write control signal and the read control signal supplied from the control terminals T _C4 and T _C5 , and the memory unit 12 of the memory unit 12 receives the selected column address. It is supplied to the column address input unit 15.

Further, the row address write / read switching section 30 is supplied with the write row address selectively output by the row address control section 28 and the read row address from the read address generation section 18, and at the same time the control terminals T _C4 , T _C5.
From which write and read control signals are provided. The row address write / read switching unit 30 selectively outputs either the write row address or the read row address according to the write control signal and the read control signal supplied from the control terminals T _C4 and T _C5 , and outputs the read address. It is supplied to the row address input unit 14.

The read address generator 18 which supplies the read column address and the read row address to the write / read switching unit 19 comprises a read column address generator 31 and a read row address generator 32. The read column address generator 31 is composed of an up counter,
Column addresses that sequentially rise are generated and supplied to the column address write / read switching unit 29. The read row address generator 32 is composed of an up-counter, generates row addresses which are sequentially increased, and performs row address write / write operations.
It is supplied to the read switching unit 30.

Further, the memory unit 12 is supplied with a write signal from the control terminal T _C6, memory unit 12 writes in response to a write signal supplied from the control terminal T _C6 is performed.

FIG. 3 shows an operation timing chart of the first embodiment of the present invention. In the figure, (A) is input image data supplied to the input terminal T _C1 , (B) is parallel input image data after serial / parallel conversion by the serial / parallel conversion unit 11, and (C) is address control. The write address supplied from the unit 20 to the write / read switching unit 19,
(D) is a read address supplied from the read address generation unit 18 to the write / read switching unit 19, (E) is a write control signal supplied to the control terminal T _C4 , and (F) is supplied to the control terminal T _C5. Read control signal, (G) is an input address to the memory section 12, (H) is a write signal supplied to the control terminal T _C6 , (I) is read data read from the data section 13, and (J) is parallel. / Serial conversion unit 1
6, the latch signal supplied to 6 and (K) indicate the output data of the parallel / serial conversion unit 16.

Which of the two write addresses, rising or falling, is selected is selected by inputting the address switching control signal supplied to the control terminals T _C2 and T _C3 to the address control unit 20.

A data input signal (FIG. 3A) serially input in time series is sent to the serial / parallel converter 1.
1 is transferred in parallel and written in the memory unit 12. On the contrary, the data read from the memory section 12 is supplied to the display device or the like by the parallel / serial conversion section 16 as the same serial data as at the time of input. The timing of writing and reading data to and from the memory is as shown in FIG.
As shown in (C) and (D), data is assigned in the period of serial / parallel conversion, and the written data is read out immediately after the writing, whereby the data is displayed in real time with respect to the moving image data.

FIG. 4 and FIG. 5 are diagrams for explaining the operation of the first embodiment of the present invention.

For example, as shown in FIG.
It is assumed that the number of display dots of is composed of 640 × 480 dots. Considering that the serial / parallel converter 11 converts a serial signal into eight parallel signals,
As shown in FIG. 4B, 8-bit data is stored in the memory unit 12 for each pixel corresponding to the address. As for the address designation of the display pixels 34, as shown by the numbers in each pixel 34, the lower two digits designate a column address and the upper three digits designate a row address and a five digit address is designated. In this embodiment, the column address is 00 to 79 and the row address is 000.
~ 479.

The address generator 17 has ascending counters 23 and 25 and descending counters 24 and 26 for each of the column and row, and these are countered to the original image as shown in FIG. In the case of inversion, the write row address is added from the rising counter 25 to the memory unit 12, and the write column address is added from the falling counter 24 to the memory unit 1.
In addition to 2, write image data. Further, the data shift direction of the parallel / serial conversion unit 16 is selected so as to be opposite to that at the time of reading at the time of reading.

In the case of vertically inverting as shown in FIG. 5B, writing is performed using the rising counter 23 for the column address and the falling counter 26 for the row address.
As shown in FIG. 5C, in the case of 180 ° rotation, both the column and row addresses are written using the down counters 24 and 26, and at the time of reading, the data shift direction of the parallel / serial conversion unit 16 is opposite to the input. .

As described above, by controlling the rising and falling directions of the write address, the image data is written, and the normal rising address is read at the time of reading.
Since the storage position of the data can be symmetrically moved to the left, right, top and bottom, the image based on the normal input image data can be easily rotated to the left, right, top and bottom or rotated.

FIG. 6 shows a block diagram of the second embodiment of the present invention. 2, those parts which are the same as those corresponding parts in FIG. 2 are designated by the same reference numerals, and a description thereof will be omitted.

In this embodiment, the input image data is written at the normal rising address at the time of writing, and the count direction of the address is controlled at the time of reading, so that the screen is reversed horizontally and vertically and rotated based on the input image data. Therefore, in the present embodiment, the write address generation unit 41 is composed of a write column address generation unit 42 and a write row address generation unit 43 consisting of only an up counter, and the generated address is supplied to the write / read switching unit 19 for reading. The address generator 44 includes an up counter 45 and a down counter 4.
6 and a read row address generator 50 including an up counter 48 and a down counter 49, and the write address of the read address generator 44 is written / read via the address controller 20. The configuration is such that it is supplied to the switching unit 19.

According to the present embodiment, the control of the address rise and fall of the read address generator 44 is performed in the same manner as the address control of the write address generator 17 of the first embodiment. You can perform left / right, upside down, and rotation as shown.

FIG. 7 shows a block diagram of the third embodiment of the present invention. This embodiment shows an image data processing device for displaying on a multi-display device.

The multi display device 51 comprises four liquid crystal display devices 52, 53, 54 and 55 having the same structure. Each of the liquid crystal display devices 52 to 55 has a wiring portion a and a screen portion b, and the wiring portion a cannot display an image.

For this reason, the liquid crystal display device 55 is rotated 180 ° with respect to the liquid crystal display device 52 and arranged diagonally, and the liquid crystal display device 53 is turned upside down with respect to the liquid crystal display device 52. Placed symmetrically on the left side of the device 52,
By arranging the liquid crystal display device 54 on the upper side of the liquid crystal display device 52 with the front and back opposite to the liquid crystal display device 52, the wiring portions a of the liquid crystal display devices 52 to 55 are positioned in the outer peripheral portion. Will be placed.

Therefore, when the liquid crystal display devices 53 to 55 are driven similarly to the liquid crystal display device 52, the liquid crystal display device 53 becomes an image in which the right and left are inverted with respect to the liquid crystal display device 52,
The liquid crystal display device 54 is an image which is vertically inverted with respect to the liquid crystal display device 52, and the liquid crystal display device 55 is the liquid crystal display device 5.
Since the image is rotated by 180 ° with respect to 2, when the liquid crystal display devices 53 to 55 are driven so as to be vertically and horizontally equivalent to the liquid crystal display device 52, the image on the liquid crystal display device 53 is horizontally reversed and the liquid crystal is reversed. The image on the display device 54 needs to be turned upside down and the image on the liquid crystal display device 55 needs to be rotated 180 ° for display.

Therefore, in this embodiment, the liquid crystal display devices 52-
Image data is supplied to 55 through the memory units 56 to 59 and is displayed.

[0044] The memory section 56 to 59 from the input image data input terminal T _IN11 is supplied, the write address generator 6
The writing and reading of the input image data are controlled according to the write address and the read address supplied from 0 and the read address generating unit 61. The write address generator 60 includes a write column address generator 62 for generating a write column address and a write row address generator 63 for generating a write row address.

The write column address generator 62 comprises an up counter 64 and a down counter 65. The up counter 64 generates a rising column address for 80 addresses, for example, 00 → 79, and the down counter 65.
Generates a descending column address for 80 addresses of 79 → 00, for example. In addition, the write row address generator 63
Is composed of an up counter 66 and a down counter 67, and the up counter 66 is, for example, 000 → 479.
, And the down counter generates falling row addresses corresponding to 480 addresses of 479 → 000, for example.

The ascending column address generated by the up counter 64 is supplied to the memory units 56 and 58 as the column address at the time of writing, and the descending column address generated by the down counter 65 is the column address at the time of writing to the memory units 57 and 59. Supplied as. In addition, the rising row address generated by the up counter 66 is stored in the memory unit 5.
6, 57 is supplied as a row address at the time of writing, and the descending row address generated by the down counter 67 is supplied to the memory units 58, 59 as a row address at the time of writing.

The read address generating unit 61 is composed of an up counter, and the ascending column address for 80 addresses, for example, 00 → 79 and 48 for 000 → 479, for example.
The rising row address for 0 address is generated, and the memory unit 5
Supply 6-59.

The image data supplied to the memory unit 56 as described above is written at the write address determined by the rising column address and the rising row address, read by the rising column address and the rising row address, and supplied to the liquid crystal display device 52. The image is displayed in the normal orientation.

The image data supplied to the memory section 57 is written by the descending column address and the ascending row address, and is written in the order reversed in the column direction (horizontal direction).
Since the image is read from the normal direction, the image on the liquid crystal display device 53 is an image that is horizontally inverted with respect to the image on the liquid crystal display device 52, and the same display as the image on the liquid crystal display device 52 can be performed.

The image data supplied to the memory section 58 is written at the write address determined by the rising column address and the falling row address, and is read by the rising column address and the rising row address. Therefore, the row direction (vertical direction). In the reverse order, and is read out from the normal direction. Therefore, when viewed from the same direction as the liquid crystal display device 52, the image on the liquid crystal display device 54 is an image which is vertically inverted with respect to the image on the liquid crystal display device 52. Therefore, the same display as the image on the liquid crystal display device 52 can be performed.

The image data supplied to the memory section 59 is written at a write address determined by the descending column address and the descending row address and read by the ascending column address and the ascending row address. Both directions (vertical direction) are written in the reverse order and read from the normal direction. Therefore, when the image of the liquid crystal display device 55 is viewed from the same direction as the liquid crystal display device 52, the image of the liquid crystal display device 52 is compared with the image of the liquid crystal display device 52. Since the image is rotated by 180 °, a normal image can be obtained when the image is arranged at a position rotated by 180 °.

In this embodiment, the write address is the column,
Since two types are prepared independently in the row direction (direction in which the address value rises and direction in which the address value falls), even in a multi-display device using liquid crystal panels, the data scanning direction of each liquid crystal panel may be arranged differently. By selecting the write address generation unit in accordance with the arrangement of the panels, it is possible to correct the vertical and horizontal inversion of the display and display the image in the normal direction.

Further, in the case of the multi-display device, any of the display devices 52 to 55 is always valid during the reading period, data is always read from the memory units 56 to 59, and the writing period is arbitrarily controlled by selectively controlling. You can perform operations such as stopping the display on the panel of and making it a movie.

Further, as shown in FIG. 8, it is possible to change the display image data for each frame and display different screens P1 to P4 for each of the display devices 52 to 55. When performing such an operation, as shown in FIG. 9, an enable signal (FIGS. 9C to 9F) that permits writing to the memory units 56 to 59 is supplied to the memory units 56 to 59 according to the frame signal. However, as shown in FIG. 9B, it can be realized by changing the image data supplied to the memory units 56 to 59 for each frame position.

FIG. 10 shows a block diagram of the fourth embodiment of the present invention. In this embodiment, the input image data for one frame is 2 × 2.
The structure which expands and displays on a screen of a frame is shown. 7 in the figure
Reference numeral 1 is a row address generation unit, and 72 is a column address generation unit. The row address generator 71 includes write row address counters 73 and 74 and read row address counter 7.
5, selectors 76 and 77, and generate a row address.

The write row address counter 73 has a terminal T.
_{twenty one}The horizontal synchronizing signal supplied to the
→ 2 → 4 → 6 → 8 → ... → 478 → 0 ... odd add
Is output and supplied to the selector 76. Writing lower
The dress counter 74 has a terminal T _{twenty one}Horizontal sync signal supplied to
The number of issues is counted and, for example, 1 → 3 → 5 → 7 → 9 → ... → 4
Outputs even addresses such as 79 → 1 ...
Supply to 6.

The read row address counter 75 has a terminal T.
_The horizontal synchronizing signal supplied to ₂₁ is counted and, for example, 0
Addresses that sequentially increase as → 1 → 2 → 3 → 4 → ... → 479 → 0 ... are output and supplied to the selector 77.

The selector 76 selectively outputs one of the output row addresses of the write row address counters 73 and 74 according to the select control signal C1 generated based on the vertical synchronizing signal, and supplies it to the selector 77. The selector 77 selectively outputs either the write row address from the selector 76 or the read row address of the read row address counter 75 according to the write / read control signal supplied to the terminal T ₂₅ .

The column address generator 72 is composed of write column address counters 78 and 79, read column address counter 80 and selectors 81 and 82, and generates a column address.

The write column address counter 78 counts a clock obtained by dividing the dot clock supplied to the terminal T ₂₂ by 8, and, for example, 0 → 2 → 4 → 6 → 8 → ... → 78.
→ Output an odd address as 0 and supply it to the selector 81. The write column address counter 79 has a terminal T _22.
A clock obtained by dividing the dot clock supplied to 8 by 8 is counted, and for example, 1 → 3 → 5 → 7 → 9 → ... → 79 → 1
The even address is output and supplied to the selector 81.

The read column address counter 80 counts a clock obtained by dividing the dot clock supplied to the terminal T ₂₂ by 8, and, for example, 0 → 1 → 2 → 3 → 4 → ... → 79.
→ Addresses that sequentially increase like 0 are output and supplied to the selector 82.

The selector 81 selectively outputs one of the output row addresses of the write column address counters 78 and 79 according to the select control signal C2 generated based on the vertical synchronizing signal, and supplies it to the selector 81. The selector 81 selectively outputs either the write column address from the selector 81 or the read column address of the read column address counter 80 according to the write / read control signal supplied to the terminal T ₂₅ .

The row address generated and selected by the row address generation unit 71 is supplied to the row address input units 87 to 90 of the memory units 83 to 86, and the column address generation unit 7 is supplied.
The column address generated and selected in 2 is stored in the memory unit 83.
To 86 column address input units 91 to 94.

The memory sections 83 to 86 are arranged in the data section 9 in accordance with the write or read address supplied to the row address input sections 87 to 90 and the column address input sections 91 to 94.
Data is written to or read from 5 to 98. Data is supplied to the memory units 83 to 86 from the serial / parallel conversion unit 99.

The serial / parallel converter 99 includes a shift register 100, selectors 101 to 104, and a latch 105.
It is composed of Serial input image data (8 bits) is supplied to the shift register 100 from the terminal T ₂₃ .
The data held in the shift register 100 is the selector 1
The data is supplied to the latch 105 via 01 to 104 and output from the latch 105 as parallel data.

If the input image data is 8 bits, the selector 101 is supplied with the data of the 4th bit and the data of the 8th bit, and either one of the data is supplied to the 7th and 8th bits of the latch 105. Selector 102 has 3 bits and 7
The bit data is supplied, and either one of the data is supplied to the fifth and sixth bits of the latch 105. Selector 1
The data of the second bit and the data of the sixth bit are supplied to 03, and either one of the data is supplied to the third and fourth bits of the latch 105. The selector 104 is supplied with the first bit data and the fifth bit data, and latches either one of the data.
It is supplied to the 1st and 2nd bits of 05. Selectors 101 to 1
Reference numeral 04 is a selection signal C generated based on the vertical synchronizing signal.
2 is supplied, and selective output is performed according to the selection signal.

The vertical synchronizing signal is supplied to the terminal T ₂₄ , and the frame counter 106 generates the above-mentioned selection signals C1 and C2. The frame counter 106 counts the vertical synchronization signal and sequentially outputs a count value for one synchronization of 00 → 01 → 10 → 11. The selection signal C1 is the count value 1
Corresponding to the bit position, 0 → 1 → 0 → according to the vertical sync signal
It changes to 1. The selection signal C2 corresponds to the second bit of the count value, and changes from 0 → 0 → 1 → 1 ... In accordance with the vertical synchronizing signal.

The read row address counter 75,
The output address of the read column address counter 80 is also supplied to the write enable generator 107. The write enable generator 107 generates enable signals E1 to E4 according to the supplied address, and the memory 83
~ 86.

Further, the write / read control signal supplied to the terminal T ₂₅ is also supplied to the memory units 83 to 86. The write / read timings of the memories 83 to 86 are controlled according to the enable signals E1 to E4 and the write / read control signals. .

Data portions 95-98 of the memory portions 83-86
Are converted into serial data by the parallel / serial conversion units 108 to 111, and then the display panels 112 to 115
Is supplied to the display device 116, and drives the display device 116.

FIG. 11 (FIGS. 12 and 13) shows the fourth embodiment of the present invention.
The operation | movement timing diagram of an Example is shown. FIG. 11 shows the timing of four cycles of the vertical synchronizing signal. FIG. 11A shows a terminal T
Vertical synchronizing signals supplied to _24, FIG. 11 (B), (C) is a selection signal C ₂ which is obtained by counting the frame counter 106 a vertical synchronization signal, C _1, 11
(D) shows the horizontal synchronizing signal supplied to the terminal T ₂₁ .

FIG. 12 shows the timing of one cycle of the vertical synchronizing signal supplied to the terminal T _24. FIG. 12A shows the vertical synchronizing signal, FIG. 12B shows the horizontal synchronizing signal, and FIG. Parallel input image data output from the serial / parallel conversion unit 99, FIG. 12D shows a timing signal T generated in the write enable generation unit 107 in response to an address from the read row address counter 75 and the read column address counter 80. Indicates ₁ .

FIG. 13 shows the timing of one horizontal synchronizing period. In FIG. 13, (A) is a horizontal synchronizing signal and (B) is a terminal T _22.
The dot clock supplied to the
(C) shows input image data converted into parallel data by the serial / parallel converter 99, and (D) shows a timing signal T ₂ generated inside the write enable generator 107.

The write enable generator 107 is shown in FIG.
(D) and timing signals T ₁ and T shown in FIG.
By decoding ₂ enable signals E _{1 to} E ₄
To generate.

FIG. 14 shows the output of the enable signals E _{1 to} E ₄ with respect to the timing signals T ₁ and T ₂ .

FIG. 15 shows an operation explanatory diagram of the fourth embodiment of the present invention.

The output of the shift register 100 is distributed to the latch 105 while being selected by the selectors 101 to 104 by the serial / parallel converter 99, as shown in FIG.
As shown in (A) and (B), the upper 4 bits and the lower 4 bits are each converted into 8-bit data, and expansion in the column direction is performed.

Further, the write row address is divided into an odd address and an even address by the write row address counters 73 and 74, and the write row address is divided into an odd address and an even address, as shown in FIGS.
As shown in (1), first, the input image data is written to the odd address, and then the same image data is written to the even address to perform the expansion in the row direction.

FIG. 16, FIG. 17 and FIG. 18 are diagrams for explaining the operation of the fourth embodiment of the present invention. In the figure, (A) is an original image. Here, the original image is 16 × 12 for the sake of simplicity.
It is composed of dots, and this original image is enlarged 2 × 2 times.

First, the operation as shown in FIGS. 15A and 15C is executed, and data is written to the odd row address of the memory units 83 to 86 as shown in FIG. 16B. . Here, the shaded portion indicates the portion where data is not written.

Next, the operations shown in FIGS. 15A and 15D are executed, and the memory unit 8 is returned as shown in FIG. 16C.
Data is written to even row addresses 3 to 86.

Next, the operation shown in FIGS. 15B and 15C is executed, and as shown in FIG.
Data is written to odd row addresses of ~ 86.

Next, the operation shown in FIGS. 15B and 15D is executed, and data is written in the even row address as shown in FIG. 17B.

By reading the data written by the above operation as usual, the data shown in FIGS.
As shown in (C), FIG. 17 (A), and FIG. 17 (B), it is possible to obtain data in which the written data are superposed,
This is an image that is 2 × 2 times the original image data shown in FIG.

According to the above configuration, for example, FIG.
The original image shown in FIG. 18 can be enlarged to a 2 × 2 enlarged image as shown in FIG.

In this embodiment, the enlargement is performed by controlling the write address, but the same control as that at the time of writing can be performed at the time of reading by controlling the read address.

FIG. 19 shows a modification of the serial / parallel converter 99. The serial / parallel conversion unit 99 described above is configured to be supplied with serially input digital image data and convert it into parallel data. However, in this modification, serially supplied analog image signals are output in parallel. It is to be converted into digital data. The serial / parallel conversion unit 120 of this modification includes comparators 121 to 124 for detecting the input signal level, shift registers 125 to 128 for generating parallel data from the data detected by the comparators 121 to 124,
A data multiplex circuit 129 for selecting data from the shift registers 125 to 128, and a latch circuit 13 for latching output data of the data multiplex circuit 129.
It consists of zero.

[0088] Comparator 121 to 124 have different thresholds Th ₁ ~Th _4, the analog input signal is compared to this threshold Th ₁ ~Th _4, it outputs a signal of high or low level. The threshold values Th _{1 to} Th ₄ are Th ₁ > T
It is set to h ₂ > Th ₃ > Th ₄ .

The detection data of 0 or 1 detected by the comparators 121 to 124 is the shift registers 125 to 128.
Are held in sequence. The data held in the shift registers 125 to 128 respectively correspond to the dots when enlarged.

FIG. 20 shows display dots at the time of enlargement. When one dot is enlarged 2 × 2 times, it can be composed of 2 × 2 dots. At this time, 1 dot corresponds to 2
The coordinates of each dot forming × 2 times the dot are (0,
When expressed as 0), (0, 1), (1, 0), (1, 1), the data held in the shift register 125 is a dot (0, 0), and the data held in the shift register 126 is a dot. (1,1), the data held in the shift register 127 corresponds to dot (0,1), and the data held in the shift register 128 corresponds to dot (1,0).

The data held in the shift registers 126 to 128 is supplied to the data multiplex circuit 129. The data multiplex circuit 129 is supplied with selection signals C1 and C2 from the frame counter 106. The multiplex circuit 129 selects data according to the selection signals C1 and C2 supplied from the frame counter 106,
Supply to the latch 130.

FIG. 21 shows an explanatory diagram of the selection operation. When the selection signal C1 is 0, an odd row address is written, and when the selection signal C1 is 1, an even row address is written. Therefore, when C1 = 0, data is written in the upper stage (0,0), (0,1) of the display dot. Data a, c to be written are selected, and when C1 = 1, data b, written in the lower row (1, 0) (1, 1) of the display dot,
d is selected. Also, the upper bit and the lower bit are divided by the selection signal C2.

After the data Q _{0 to} Q ₇ selected by the data multiplex circuit 129 are held in the latch 130,
It is supplied to the memory units 83 to 86.

By utilizing the fact that 4 dots are allocated by the enlargement as described above, it is possible to selectively illuminate any of the 4 dots in accordance with the input level to realize area gradation. In this case, four thresholds (Th _{1 to} Th ₄ ) are provided for the input analog signal, and the comparator compares the levels of the input signal to obtain 4
Obtain the analog / digital conversion signal of the book. By making this signal correspond to the dot after enlargement, the area gradation is realized by the number of lit dots.

FIG. 22 shows a block diagram of the fifth embodiment of the present invention. In this embodiment, the image is reduced.

Input image data is serially supplied to the terminal T ₃₁ . The terminal T ₃₁ is the serial / parallel converter 13
1 and the serial input image data is supplied to the serial / parallel conversion unit 131.

The serial / parallel converter 131 is composed of shift registers 132, 133 and a latch 134. The serial input image data is stored in the shift register 132,
It is sequentially held in 133.

The shift registers 132 and 133 each have 8 bits and hold 16-bit input image data. The shift registers 132 and 133 are connected to the latch 134 every other bit. The latch 134 is configured to hold 8-bit data, and the shift register 132, 1
The data held in 33 is thinned out, converted into parallel data, and supplied to the memory unit 135.

The memory section 135 has a data section 136, a row address input section 137, and a column address input section 138. The output conversion data of the serial / parallel conversion unit 131 is supplied to the data unit 136, and the row address input unit 1
37, writing and reading are performed according to the address supplied to the column address input unit 138.

The read data is supplied to the parallel / serial conversion unit 139, converted into serial data and supplied to the display unit.

The row address and the column address are supplied from the address generator 140 to the row address input unit 137 and the column address input unit 138 of the memory unit 135. The address generator 140 includes a row address generator 141 that generates a row address and a column address generator 142 that generates a column address.

The row address generator 141 outputs the write row address counter 143 for generating a write row address, the read row address counter 144 for generating a read row address, and the write row address counter 143 or the read row address counter 144. It is composed of a selector 145 for selection. The write row address counter 143 is supplied with the horizontal synchronizing signal from the terminal T ₃₂ , counts the horizontal synchronizing signal, and counts 0 → 0 → 1 → 1 → 2 → 2 → 3 → 3 → ... → 239 → 239 for each count.
Count up the address like. Further, the read row address counter 144 is supplied with a horizontal synchronizing signal from a terminal T ₃₂ , counts the horizontal synchronizing signal, and counts up the address as 0 → 1 → 2 → 3 → ... → 479 for each count.

Write / _select from the terminal T ₃₄ to the selector 145.
The read control signal is supplied, and either the write row address or the read row address is selectively output according to the write / read control signal and is supplied to the row address input unit 137 of the memory unit 135.

The column address generator 142 is a write column address counter 1 for generating a write column address.
46, a read column address counter 147 for generating a read column address, a write column address counter 146, and a selector 148 for selecting any address of the read column address counter 147. The write column address counter 146 has a terminal T.
_A clock that is a dot clock divided by 8 is supplied from ₃₃ , the clock is counted, and 0 → X → for each count.
The number of invalid addresses is incremented every cycle, such as 1 → X → 2 → X → 3 → X → ... → 39 → X.
A clock obtained by dividing the dot clock by 8 is supplied from the terminal T ₃₃ to the read column address counter 147, and this clock is counted and 0 → 1 → 2 → 3 → for each count.
The address is incremented like →→ 79.

Writing / writing from the terminal T ₃₄ to the selector 148
The read control signal is supplied, and either the write column address or the read column address is selectively output according to the write / read control signal and is supplied to the column address input unit 138 of the memory unit 135.

23 and 24 are operation timing charts of the fifth embodiment of the present invention. FIG. 23A shows a vertical synchronizing signal,
23B is a horizontal synchronizing signal supplied to the terminal T ₃₂ , FIG. 23C is input image data supplied to the terminal T ₃₁ , and FIG. 23D is a row address generated by the write row address counter 143. 23E is a write enable supplied to the terminal T ₃₅ , FIG. 23F is a read address generated by the read row address counter 144, and FIG.
(G) shows read data read from the data section 136 of the memory section 135.

The numbers in FIG. 23 (C) indicate lines, and FIG.
The numbers in 3 (D) and FIG. 23 (E) indicate count values and correspond to addresses. The data shown in FIG. 23G is the data of the previous frame, and the numbers indicate the lines in which the data was written. The data of FIG. 23G is supplied to the display device in the order of being read and is sequentially displayed from the first line. Therefore, the 0 line of the display device is a display corresponding to the 0 line data, the 1 line of the display device is a display corresponding to the 2 line, similarly, the data of 4, 6, 8, 10 ... Line is the display device. 2, 3, 4, 5 ... Displayed on the line.

Further, FIG. 24A shows a horizontal synchronizing signal supplied to the terminal T ₃₂ , FIG. 24B shows a dot clock for generating a clock supplied to the terminal T ₃₃ , and FIG.
(C) is input data supplied to the terminal T ₃₁ , FIG.
24D is a latch timing signal of the latch 134, FIG.
24E is the output parallel data of the latch 134, FIG.
24F is a write / read control signal supplied to the terminal T ₃₄ , FIG. 24G is a write address supplied to the memory unit 135, and FIG. 24H is a read address supplied to the memory unit 135. 24 (I) is a read latch timing signal of the memory unit 135, and FIG.
24, the conversion timing signal of the parallel / serial conversion unit 139 is shown in FIG.
(L) indicates output data of the parallel / serial conversion unit 139.

As described above, in this embodiment, the counter value of the write address counter is doubled every other number in the vertical direction, thinned out every other line, and set to 1 in the horizontal direction.
Data is thinned out at every dot, and is written in the RAM when 1 byte (8 bits) is prepared, and reading is performed by sequentially reading 1 byte of data from the memory unit 135 for each line.

[0110]

As described above, according to the present invention, it is possible to control the output order of image data by controlling the order of address designation to the memory unit in which the input image data is stored. It has features such that image processing such as left / right, upside down, enlargement / reduction of the obtained image can be easily realized.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a block diagram of the first embodiment of the present invention.

FIG. 3 is an operation timing explanatory diagram of the first embodiment of the present invention.

FIG. 4 is an operation explanatory diagram of the first embodiment of the present invention.

FIG. 5 is an operation explanatory diagram of the first embodiment of the present invention.

FIG. 6 is a block configuration diagram of a second embodiment of the present invention.

FIG. 7 is a block configuration diagram of a third embodiment of the present invention.

FIG. 8 is an operation explanatory diagram of the third embodiment of the present invention.

FIG. 9 is an operation explanatory diagram of the third embodiment of the present invention.

FIG. 10 is a block diagram of a fourth embodiment of the present invention.

FIG. 11 is an operation timing explanatory diagram of the fourth embodiment of the present invention.

FIG. 12 is an operation timing explanatory diagram of the fourth embodiment of the present invention.

FIG. 13 is an operation timing explanatory diagram of the fourth embodiment of the present invention.

FIG. 14 is an operation explanatory diagram of the fourth embodiment of the present invention.

FIG. 15 is an operation explanatory diagram of the fourth embodiment of the present invention.

FIG. 16 is an operation explanatory diagram of the fourth embodiment of the present invention.

FIG. 17 is an operation explanatory diagram of the fourth embodiment of the present invention.

FIG. 18 is an operation explanatory diagram of the fourth embodiment of the present invention.

FIG. 19 is a configuration diagram of a modified example of the serial / parallel conversion unit of the fourth exemplary embodiment of the present invention.

FIG. 20 is an explanatory diagram of display dots when enlarged.

FIG. 21 is an operation explanatory diagram of a modified example of the serial / parallel conversion unit of the fourth exemplary embodiment of the present invention.

FIG. 22 is a block diagram of the fifth embodiment of the present invention.

FIG. 23 is an operation timing explanatory diagram of the fifth embodiment of the present invention.

FIG. 24 is an operation timing explanatory diagram of the fifth embodiment of the present invention.

FIG. 25 is a configuration diagram of a rear projection display device.

FIG. 26 is a configuration diagram of a multi-display device using a direct-viewing type liquid crystal panel.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 memory unit 2 address generation unit 3 address control unit 11 serial / parallel conversion unit 12 memory unit 13 data unit 14 row address input unit 15 column address input unit 16 parallel / serial conversion unit 17 write address generation unit 18 read address generation unit 21 Write column address generator 22 Write row address generator 23,25 Up counter 24,26 Down counter 27 Column address controller 28 Row address controller

Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G09G 3/20 R 9378-5G 5/36 520 K 9471-5G H04N 1/387 9/74 Z 9191-5L G06F 15/68 310 J

Claims (7)

[Claims] 1. A memory unit (1) for storing input image data, and an address designating a storage position of the input image data in the memory unit (1) is generated and supplied to the memory unit (1). The output order of the input image data is controlled by controlling the address generation section (2) and the address generation section (2), and controlling the designation order of the addresses generated by the address generation section (2). An image data processing device comprising an address control unit (3), and performing display conversion processing of an image obtained according to the input image data. 2. The image data processing apparatus according to claim 1, wherein the address control unit (3) controls the output order of the image data by controlling a write address. 3. The image data processing apparatus according to claim 1, wherein the address control unit (3) controls the output order of the image data by controlling a read address. 4. The address controller (3) reverses and rotates an image according to the image data by controlling addresses of data in the scanning direction and the sub-scanning direction of the image data. The image data processing device according to any one of claims 1 to 3. 5. A data distribution means (99) for distributing the input image data to a plurality of adjacent addresses in one direction.
The address control unit (71, 72) controls the address of the input image data distributed by the data distribution unit so that the memory unit (83 to 86) stores the input image data in the data distribution unit (99). 5. The screen is expanded according to the input image data by writing or reading this data while accessing the same address a plurality of times in a direction orthogonal to the distribution direction. The image data processing device according to any one of claims. 6. A data synthesizing means (10) for synthesizing the input image data into one data from a plurality of data in one direction.
3), and the data synthesizing means (103) of the memory section (135) by the address control section (140) for the data synthesized by the data synthesizing means (103).
5. The screen is reduced according to the input image data by writing or reading data while accessing every other line to an address in a direction orthogonal to the composition direction of. The image data processing device according to any one of claims. 7. Data conversion means (121 to 121) for converting the input image data into data for controlling the brightness of a plurality of dots set in advance according to the gradation of the input image data.
30), and the data conversion means (121 to 130)
6. The image data processing device according to claim 1, wherein the data converted by the above is used as input data of the memory (3).