JPH07151820A - Testing apparatus for withstand voltage - Google Patents

Abstract

PURPOSE:To test the withstand voltage without degrading a sample. CONSTITUTION:A DC high voltage is applied to a sample from a high-voltage generation part 1, and a current which flows in the sample is detected by a current detection part 3. Then, on the basis of the detected current, an abnormality detection part 6 detects the abnormality such as the withstand-voltage defect, the insulation defect or the like of the sample. When the abnormality of the sample is detected by the abnormality detection part 6, a thyristor Q1 is turned on, and the high voltage which has been applied to the sample is dropped instantaneously. Instead of a high-voltage relay whose responsivity is slow, the thyristor Q1 whose responsivity is excellent is used. Thereby, when the sample is judged to be abnormal, the high voltage which has been applied to the sample is dropped instntaneously by the thyristor Q1, and withstand voltage can be tested without degrading the sample.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a breakdown voltage tester for non-destructively testing the breakdown voltage of a sample.

[0002]

2. Description of the Related Art A breakdown voltage tester is a device for applying a high voltage to a sample, which is an electronic component such as a semiconductor element, and testing whether the sample has a breakdown voltage defect or an insulation defect. Abnormalities such as insulation defects are detected from the current flowing through the sample when a high voltage is applied. Here, in the conventional withstand voltage test device of this type, when it is determined that the sample is defective, the high voltage applied to the sample is cut off by using a high voltage relay or the like.

[0003]

However, in the method of cutting off the high voltage applied to the sample by using the high voltage relay or the like as described above, the response of the high voltage relay is delayed,
It took a long time for a large current to flow through the sample, making it unsuitable for nondestructive testing. In this type of withstand voltage test apparatus, a high voltage relay or the like is turned on at the start of the test, and a high voltage of a predetermined voltage is often applied to the sample. However, when a high voltage is suddenly applied to the sample at the start of the test using the high voltage relay in this way, when the sample has a stray capacitance, a large inrush current flows as a charging current for charging the stray capacitance, and the charging current Therefore, there is a risk that a normal sample may be determined to be defective.

Therefore, as a countermeasure, it is conceivable to make the abnormality determination circuit for determining abnormality of the sample from the current flowing through the sample insensitive to the charging current for charging the stray capacitance. However, in this case, there is a problem in that the abnormality determination circuit cannot detect a minute discharge current, and the abnormality detection performance of the withstand voltage test apparatus deteriorates.

Further, at the end of the test, it is necessary to turn off the high voltage applied to the sample by a high voltage relay or the like, and then take out the sample from the withstand voltage test apparatus. However, in the case of the sample having the stray capacitance as described above, there is a risk of electric shock because the high-voltage electric charge is accumulated in the stray capacitance. The present invention has been made in view of the above points, and a first object is to prevent deterioration of a sample,
The second purpose is to make it possible to perform a withstand voltage test, and the second purpose is to prevent inrush current from flowing at the start of the test even for a sample having a stray capacitance. The purpose is to avoid the risk of electric shock even if the sample is touched after the test.

[0006]

In order to achieve the first object, the invention of claim 1 is a high voltage generating means for generating a high DC voltage applied to a sample, and a high voltage generating means. A voltage detecting means for detecting a high voltage value, a current detecting means for detecting a current flowing through the sample, a reference voltage generating means for generating a reference voltage for setting a high voltage value applied to the sample, and the reference voltage. Voltage control means for determining the difference between the reference voltage of the generating means and the voltage value detected by the voltage detecting means and controlling the voltage value of the high voltage generated by the high voltage generating means so as to eliminate the difference, and the current detecting means. An abnormality detecting means for detecting an abnormality of the sample from the current detected by the means, and a switching element which is turned on when the abnormality detecting means detects the abnormality of the sample and instantaneously steps down the high voltage applied to the sample. ing.

In order to achieve the above-mentioned second object, the invention of claim 2 gradually increases the value of the reference voltage from 0V from the start of the test as a reference voltage generating means, and applies it to the sample after an appropriate time. A high voltage value is used as a specified value for the withstand voltage test. The pressure resistance test device described. Claim 3
In order to achieve the above-mentioned third object, the invention of (1) makes it possible to turn on the switching element even at the end of the test.

[0008]

According to the invention of claim 1, it is judged that the sample is abnormal by using a switching element having excellent responsiveness, such as a thyristor, in place of the high-voltage relay having slow responsiveness as described above. At this time, the high voltage applied to the sample is instantaneously stepped down by the switching element. As a result, the breakdown voltage test can be performed without deteriorating the sample.

According to a second aspect of the present invention, as the reference voltage generating means, the value of the reference voltage is gradually increased from 0 V from the start of the test, and a high voltage value applied to the sample after an appropriate time is a prescribed value for performing the withstand voltage test. The high voltage applied to the sample is gradually increased by using the above, so that even if the sample has a stray capacitance, a large charging current does not flow in the stray capacitance. That is, the current value of the charging current for charging the stray capacitance is suppressed to be smaller than the current value determined to be abnormal by the abnormality detecting means so that the abnormality detecting function of the withstand voltage test apparatus is not affected.

According to the third aspect of the present invention, by turning on the switching element even after the test is completed, when the sample has a stray capacitance, the electric charge charged in the stray capacitance is switched at the end of the test. Discharge through
Do not get an electric shock even if you touch the sample after the test.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a pressure resistance test apparatus of the present invention. In addition,
The specific configuration is shown in FIG. The withstand voltage test apparatus of this embodiment basically has a high voltage generation unit 1 that generates a high DC voltage applied to a sample and a voltage detection unit 2 that detects a voltage value of the high voltage applied to the sample. A current detecting section 3 for detecting a current flowing through the sample, a reference voltage generating section 4 for generating a reference voltage for setting a high voltage value applied to the sample, a reference voltage of the reference voltage generating section 4 and the above voltage. The voltage control unit 5 for controlling the voltage value of the high voltage generated by the high voltage generation unit 1 so as to find the difference from the voltage value detected by the detection unit 2 and eliminating the difference, and the voltage control unit 5 detected by the current detection unit 3 Abnormality detecting section 6 for detecting an abnormality of the sample from the current, a time section 7 for applying a high voltage to the sample, that is, a withstand voltage test time, and an end of the withstand voltage test time set by this timer section 7. At the time, and when the abnormality of the sample is detected by the abnormality detection unit 6 High voltage removal unit 8 stepping down a high voltage applied to the sample instantly
And a control unit 9 which gives a processing signal to each unit at the start and end of the withstand voltage test.

The high voltage generator 1 supplies the AC (sine wave) voltage generated by the AC (sine wave) generation circuit 11 to the power amplifier 1
2 is amplified, the amplified output is further boosted by the step-up transformer T ₁ , and the boosted output is rectified and smoothed by the diode bridge DB ₁ and the smoothing capacitor C ₁ to obtain a high DC voltage. The smoothing capacitor C ₁ A high voltage generated at both ends of the sample is applied to the sample.

Here, in order to set the high voltage applied to the sample to a specified value, the voltage detection unit 2 for detecting the voltage value applied to the sample and the value of the high voltage applied to the sample, that is, the above specified value. Reference voltage generator 4 for generating a reference voltage for setting a value
Then, the difference between the reference voltage of the reference voltage generator 4 and the voltage value detected by the voltage detector 2 is obtained, and the voltage value of the high voltage generated from the high voltage generator 1 is controlled so as to eliminate the difference. And a voltage control unit 5.

[0014] Voltage detector 2 Yes constituted by voltage dividing resistors R _2, R ₃ and the differential amplifier 21, and the divided voltage of the voltage dividing resistors R _2, R _3, the dividing resistors R _2, R _The differential amplifier 21 amplifies the difference between the divided voltage between the series circuit of 3 and the current detection resistor R ₁ of the current detection circuit 3 to be described later to obtain a voltage output according to the high voltage applied to the sample. There is. The reference voltage generator 4 is composed of a ramp (RAMP) wave generation circuit 40, which will be described in detail later, and a variable resistor VR ₁ which generates a reference voltage V _REF based on the output voltage of the ramp wave generation circuit 40. is there.

The voltage control unit 5 is inserted between the error amplifier 51 that generates an error output between the detection voltage V _VD detected by the voltage detection unit 2 and the reference voltage V _REF , and the AC generation circuit 11 and the amplifier 12. And an attenuator 52 that appropriately attenuates the output of the AC generation circuit 11 based on the output of the error amplifier 51. In each of the units 2, 4 and 5, the attenuation amount in the attenuator 2 is adjusted by the output of the error amplifier 5 so that the detection voltage V _VD detected by the voltage detection unit 2 matches the reference voltage V _REF , and then applied to the sample. Feedback control is performed so that the _generated high voltage becomes a prescribed voltage value determined by the reference voltage V _REF .

As the current detecting section 3, a current detecting resistor R ₁ inserted in a path through which a high voltage is applied to the sample is used. Here, a limiter circuit 31 is connected to both ends of the current detection resistor R ₁ . The limiter circuit 31 is provided in order to prevent an excessive input signal from being applied to the inverting amplifier 61 of the abnormality detection unit 6 described below even if an abnormally large current flows through the current detection resistor R _1. There is.
In this embodiment, the resistance detects the current flowing through the sample, but a current transformer or the like may be used.

The abnormality detecting section 6 includes a current detecting resistor R₁Both ends of
Inverting amplifier 61 that amplifies the voltage generated in the
High-pass filter 62 that extracts high-frequency components from the output
And a low-pass filter that extracts low-frequency components from the amplified output.
Filter 63 and the high frequency extracted by the high pass filter 62.
A comparator that determines whether the wave component is above a specified value.
Ta CMP₁And the low frequency extracted by the low pass filter 63.
A comparator that determines whether the wave component is above a specified value.
Ta CMP₂And the control described later, which indicates that the pressure resistance test is in progress.
Output Q of control circuit 94 of control section 9_BAnd each comparator
CMP₁, CMP ₂Take the AND of the
Comparator CMP₁, CMP₂Output is high level
AND circuit whose output becomes high level when
AND₁, AND₂And each AND circuit AND₁, A
ND₂When any of the outputs of
NOR circuit NOR that generates high level output₁And Noah times
Road NOR₁Flip-flop 64 set by the output of
It consists of and. In addition, each comparator CMP₁, C
MP₂Reference voltage V_REF3, V_REF4Is the variable resistance VR₃, V
R_FourYou can change the setting with.

The timer unit 7 is composed of a timer 71 in which a test time is set and a fall detection circuit 72 for detecting the fall of the output Q _T of the timer 71. The timer 71 is
The output of the ramp wave generation circuit 40 * V _TRIG (* indicates that the signal or the input terminal is active low) starts the time counting operation, and a high level output is generated during the time counting operation. Further, the fall detection circuit 72 detects the fall of the test time by detecting the fall of the timer 71. Here, the fall detection circuit 72 is composed of, for example, a differentiating circuit that differentiates the output of the timer 71 and a one-shot multivibrator that is triggered by the differentiated output, and generates a negative pulse at the time of falling detection. Is done. The falling edge detection circuit and the rising edge detection circuit described below have the same configuration.

The control section 9 includes a delay circuit 91 for starting a timing operation by a start signal (START) consisting of a negative pulse indicating the start of a test, a rising detection circuit 92 for detecting the rising of the delay circuit 91, and a delay circuit. A fall detection circuit 93 for detecting the fall of the circuit 91, and a control circuit 94 including a flip-flop set by the output of the fall detection circuit 93.
An output composed of a fall detection circuit 95 for detecting the fall of the output of the output Q _B of the control circuit 94, and a flip-flop for producing a high level output when the output of the fall detection circuit 95 is obtained. And a circuit 96.

In the control circuit 94, when a reset signal (RESET) consisting of a negative pulse for forcibly ending the withstand voltage test is input, an abnormal output is obtained by the flip-flop 64 of the abnormality detecting section 6. At this time, when the test operation time set in the timer 71 elapses and the output of the fall detection unit 72 is input, each is reset.

The high-voltage cutoff unit 8 has a thyristor (SCR) Q ₁ connected in parallel across a smoothing capacitor C ₁ via a resistor R ₄ and a gate of the thyristor Q ₁ via a pulse transformer PT _1. And a gate trigger circuit 81 for applying a trigger. Further, as shown in FIG. 2, the gate trigger circuit 81 takes the NAND of the output of the rising edge detection circuit 92 of the control section 9, the output of the falling edge detection circuit 95, and the reset signal (RESET), and either It is composed of a NAND circuit NAND ₁ whose output becomes high level when the signal becomes low level, and a transistor Q ₃ which is on / off controlled by the output of the NAND circuit NAND ₁ .

Here, the present embodiment is characterized in that the thyristor Q ₁ is used as a means for cutting off the high voltage applied to the sample. In addition to the thyristor Q ₁ , a switching element having excellent responsiveness, for example, an SI thyristor may be used, and if a withstand voltage is satisfied, a transistor,
It may be a FET or the like. Also, as shown in FIG.
Two thyristors Q ₁₁ and Q ₁₂ connected in series may be used to increase the withstand voltage of the thyristor Q ₁ .

The ramp wave generator 40 of the reference voltage generator 4, which is another feature of the present invention, will be described below. As shown in FIG. 2, the ramp wave generation circuit 40 basically includes an integration circuit 41 that generates an output that gradually increases from 0 V to the voltage of the control power supply, and an output of the integration circuit 41 that is a reference voltage V _REF. A buffer B ₁ applied to a variable resistor VR ₁ for setting a comparator, and a comparator CMP ₃ for detecting a state immediately before the high voltage applied to the sample reaches a predetermined value because the output of the integrating circuit 84 has reached a predetermined voltage. It is composed of.

The output of the integrating circuit 41 is, for example, as shown in FIG.
As shown in (g), the voltage gradually increases from 0 V to the voltage of the control power supply. As a result, the reference voltage V _REF is also shown in FIG.
As shown in, the voltage gradually increases from 0V to a predetermined value. An input voltage is applied to the integrating circuit 41 via a variable resistor VR _2, and a charging current for charging the capacitor C _I via the resistor R _I of the integrating circuit 41 is adjusted by adjusting the input voltage. It is variable so that the rising speed of the output voltage V _C can be changed. That is, since the stray capacitance of the sample varies depending on the shape and the like, the input voltage can be adjusted by using the variable resistor VR ₂ in order to appropriately suppress the charging current to a small value according to the type of the sample.

A Zener diode ZD ₁ is connected to the output of the integrating circuit 41 to prevent the voltage applied to the variable resistor VR _{1 from} becoming higher than necessary. The reference voltage of the comparator CMP ₃ is slightly lower than the Zener voltage E _Z of the Zener diode ZD ₁ (E
_Z- ΔE), and the state immediately before the output of the integrating circuit 41 reaches the Zener voltage E _Z is determined as the state immediately before the high voltage applied to the sample reaches a predetermined value. The output of the comparator CMP _3, the rising edge detection unit 42 is provided, upon detecting a rising edge of the comparator CMP _3, it is as to generate a negative pulse. It should be noted that the output of the rising detection unit 42 is used to output the timer 7 of the clock unit 7.
1 starts timing operation. In other words, in the case of the present embodiment, it takes time for the reference voltage V _REF to reach the specified voltage. Therefore, the comparator CMP ₃ is provided and the test time is measured at the time when the specified high voltage is applied to the sample. The operation of the timer 71 is started.

The ramp wave generating circuit 40 has an analog switch SW _D which is turned on at the time of a test so that an input voltage can be applied to the integrating circuit 41 from the variable resistor VR ₂ .
It is connected to both ends of the capacitor C _I through the discharge resistor R _D and the analog switch SW _E that turns on during non-testing and drops the input of the integrating circuit 41 to the ground, and turns on during non-testing. , Capacitor C
An analog switch SW _F for discharging the charge of ₁ is provided. Any of these analog switches SW _{D to} S
W _F is basically also provided to keep the operation of the integrating circuit 41 completely stopped during non-testing and to put the integrating circuit 41 into the initial state for the next measurement.

In addition to these analog switches SW _{D to} SW _F , the present embodiment includes analog switches SW _{A to} SW _C. The analog switch SW _A is turned on at the time of non-test, the input terminal of the reference voltage V _REF of the error amplifier 5 is connected to the ground, and the variable resistor VR ₁ to the reference voltage V _REF.
It is to prevent _{REF from} being applied, and the analog switch SW _B is turned on during non-test, so that the control input of the attenuator 2 is dropped to the ground and the output of the error amplifier 5 is input to the attenuator 2. Is to prevent. These analog switches SW _A and SW _B are provided to prevent a malfunction of the withstand voltage test device by opening a feedback control loop during non-test.

The analog switches SW _A , SW _B and S
The ON / OFF control of W _{D to} SW _F is performed by the control circuit 94 of the control unit 9. That is, the control circuit 9
The output Q _B of 4 turns on the analog switch SW _D ,
The off control is performed and the analog switch S is output at output * Q _B.
ON / OFF control of W _A , SW _B , SW _E , and SW _F is performed.

The analog switch SW _C is a differential amplifier 4
It is provided at the output of a, and a capacitor C _H is connected to that output,
The output of the capacitor C _H is output to the voltmeter M via the buffer B _2.
Output to the analog switch S
A sample hold circuit is composed of W _C , capacitor C _H and buffer B ₂ . That is, while the output * Q _NG of the flip-flop 64 is at the high level, the analog switch SW _C is turned on, and the output of the differential amplifier 4a is added to the capacitor C _H during this period, and When an abnormality is detected, the flip-flop 64
When the output of becomes the low level, the analog switch S
W _C turns off and the differential amplifier 4 at the time of abnormality detection
The output voltage state of a is held by the capacitor C _H , the value is displayed by the voltmeter M, and the value of the high voltage applied to the sample at the time of abnormality detection can be confirmed.

The basic operation of this embodiment will be described below. First, a case of so-called no-load operation in which the sample is not mounted will be described. When starting the withstand voltage test, a negative pulse start signal is input according to the operation of the start switch or the like (FIG. 3A). This start signal is input to the delay circuit 91. In the delay circuit 91, as shown in FIG.
As shown in (b), it is triggered by the rising edge of the start signal and generates an output Q _D that is at a high level for a fixed time (delay time).

The output Q _D of the delay circuit 91 is input to the rising edge detecting section 92 and the falling edge detecting section 93. here,
The output circuit 96 is reset by the output * CLR ₂ of the rising edge detector 92 shown in FIG. As a result, the output state indicating the previous test result held in the output circuit 96 is cleared. Also, the output * CLR of this rising detection unit 92
₂ is also input to the high voltage cutoff unit 8. At this time, the output of the NAND circuit NAND ₁ becomes a high level by the output of the rising detection section 92, the transistor Q ₃ is turned on, and the gate of the thyristor Q ₁ is triggered to be turned on. As described above, by turning on the thyristor Q ₁ before starting the test, for example, the charge stored in the smoothing capacitor C ₁ is discharged, so that the test can be appropriately performed. In other words, the pre-processing at the start of the test is performed by the above operation. The delay circuit 91 is provided to set the time for this preprocessing.

When the output of the delay circuit 91 falls, FIG.
Output * B of rising edge detection unit 93 shown in (d)_SETIs output
Then, the control circuit 94 is set to the test state. This and
Output Q of the control circuit 94_BBecomes high level and output
* Q_BBecomes low level. Output Q of control circuit 94_BTo
More analog switch SW_DIs turned on and the integration circuit
An input voltage is applied to 41. As a result, the integration circuit 4
1 output voltage V_CIs 0V as shown in FIG.
Resistance R_IAnd capacitor C_IGradually according to the time constant of
To rise. Then, the output V of the integrating circuit 41_CTse
N-Diode ZD ₁Zener voltage E_ZAfter reaching
Is the output V_CIs the Zener voltage E_ZKept in. Zenadai
Aether ZD₁The voltage Va at both ends of is shown in FIG.

The voltage Va corresponds to the buffer B.₁Through high power
Variable resistance VR set to the specified value of pressure ₁Applied to. This
Here, the reference voltage V_REFIs buffer B₁Above the output voltage of
Buffer B gradually rises with rising₁Input voltage Va of
Zener voltage E_ZReaches the specified high voltage
It is in the state of being applied. The reference voltage V_REFIs the error
By inputting into the group 51, the
The attenuation is maximized by the attenuator 52 and gradually reduced.
It is controlled so that it can be extracted. Power amplifier 1 at this time
2 output V_PAIs shown in FIG. 3 (n), and the smoothing capacitor C₁
Voltage V across_C1Figure (p), high voltage applied to the sample
The HV is shown in FIG.

The voltage Va is also input to the comparator CMP ₃ . Here, the reference voltage of the comparator CMP ₃ is the Zener diode ZD as shown in FIG.
_The voltage (Ez-ΔE) slightly lower than the Zener voltage of ₁ is set, and it is detected by the comparator CMP ₃ that the time immediately before the state in which a predetermined high voltage is applied to the sample is reached. Note that the reference time of the comparator CMP ₃ can be set to be constant when the reference voltage is as close as possible to the Zener voltage, but the timer 71 may not start the time counting operation when the Zener voltage varies. Therefore, in order to prevent this, the reference voltage is set to a voltage (Ez-ΔE) slightly lower than the Zener voltage.

The output of the comparator CMP ₃ (see FIG.
The rising edge (shown in (i)) is detected by the rising edge detector 72. An output * V _TRIG composed of a negative pulse shown in FIG. 3 (j) is output from the rising edge detection section 72, whereby the timer 71 for measuring the test time starts the time counting operation. In other words, when the sample is non-defective, the sample 71 measures the time measured by the timer 71 (high-level period shown in FIG. 3K).
Only a high voltage is applied. Even in the unloaded state, a high voltage is applied during the test time set in the timer 71, as in the case where the sample is non-defective.

When the test time is over,
The fall detection unit 72 detects it. At this time, the falling edge detector 72 outputs the signal * CLR ₄ shown in FIG. 4 (l), and the control circuit 94 is reset. At this time, the output Q _B of the control circuit 94 becomes low level, and the negative pulse signal * E _SET shown in FIG. 3 (v) is output from the fall detection circuit 95. As a result, the output Q _E of the output circuit 96 becomes high level. This output Q _E is used to indicate that the test is complete.

The output * E _SET of the fall detection circuit 95 is also input to the high-voltage cutoff section 8 at the same time, and as a result, the gate of the thyristor Q ₁ as shown in FIG. Trigger on to turn it on. When the thyristor Q ₁ is turned on in this way, the charge stored in the smoothing capacitor C ₁ is discharged through the resistor R ₄ and the device is ready for the next test.

Further, when the output Q _B of the control circuit 94 becomes low level, the analog switch SW _D is turned off, and when the output * Q _B becomes high level, the analog switches SW _A , SW _B , SW. _E , SW _F
Are turned on to prevent the output of the integration circuit 51 from being generated, and the voltage control unit 5 is maintained in a state where it is not controlled.

Needless to say, no current flows through the current detection resistor R ₁ when there is no load, and the output Vi of the inverting amplifier 61 does not occur as shown in FIG. 3 (r). Therefore, the output * Q _NG of the flip-flop 64 of the abnormality detection unit 6 is maintained in the high level state. Therefore, the analog switch SW _C is always held in the ON state, and the voltmeter M displays the voltage corresponding to the output V _VD of the differential amplifier 21 shown in FIG. 3 (s).

Next, description will be made on the case where a withstand voltage test is performed on a non-defective sample. Also in this case, the operation is almost the same as the above-mentioned no load. Here, when the non-defective sample has a stray capacitance, a charging current flows when the stray capacitance is charged. However, in this embodiment, as described in the operation at no load, the reference voltage V _REF is gradually increased from 0V from the start of the test, and the high voltage applied to the sample is also gradually increased from 0V. Therefore, even if the sample has a stray capacitance, the current flowing through the stray capacitance can be suppressed to a small value as shown in FIG. 4 (j). Therefore, unlike the case where a high voltage of a specified value is applied simultaneously with the start of the test, no inrush current flows. Since the charging current is kept small in this way, the abnormality detection unit 6 does not detect any abnormality.

At the end of the test, thyristor Q ₁
By turning on, the electric charge accumulated in the stray capacitance of the sample is discharged through the resistors R ₅ and R ₁ . In this way, there is no risk of electric shock even if the sample is touched after the test. At the end of this test, as with no load,
The charging charge of the smoothing capacitor C ₁ is also discharged. When the sample has a poor withstand voltage, as shown in FIG.
A current flows through the current detection resistor R ₁ through the sample. The voltage generated across the current detection resistor R ₁ by this current is amplified by the inverting amplifier 61 and input to the low pass filter 62 and the high pass filter 63. Here, in this case, since the sample has a poor withstand voltage, a high-frequency current flows through the sample. The high frequency referred to here means a high frequency with respect to the frequency of the current component flowing at the time of insulation failure. In this way, when the breakdown voltage is poor, a high-frequency current flows, and the output of the inverting amplifier 61 corresponding to the current in this case is input to the comparator CMP ₂ through the high-pass filter 62. Here, the output of the inverting amplifier 61 is the reference voltage V set by the variable resistor VR _4.
When it exceeds _REF4, the output of the comparator CMP ₂ becomes high level. In this case, since the output Q _B of the control circuit 94 is at high level, the output of the AND circuit AND ₁ becomes high level and the output of the NOR circuit NOR ₁ becomes low level. In the flip-flop 64, the NOR circuit NOR
Upon receiving the output of ₁ , the output Q _NG becomes low level as shown in FIG. 6 (h). This low level output is input to the clear input * CLR ₃ of the control circuit 94. As a result, the output of the control circuit 94 becomes low level, a negative pulse signal * E _SET is generated at the output of the _fall detection section 95, and the output Q _E of the output circuit 96 becomes high level. The output of the output circuit 96 indicates that the test is completed. When the output * Q _NG of the flip-flop 64 becomes low level, the analog switch SW _C , which has been in the on state until then, is turned off, and when the abnormality is detected by the voltmeter M, it is applied to the sample. Displays the high voltage value. The tester confirms from the display on the voltmeter M that the sample is abnormal.

Next, the case where the sample has a defective insulation will be described. In this case as well, basically, an abnormality is detected in the same manner as in the case where the sample has a poor withstand voltage, and therefore only the different operation in the case of a poor insulation will be described. When a high voltage is applied to a sample having such an insulation defect, a low-frequency current flows. The output Vi of the current inverting amplifier 61 detected in the case of this insulation failure is input to the comparator CMP ₁ through the low-pass filter 63. When the output of the inverting amplifier 61 at this time is larger than the reference voltage V _REF3 set by the variable resistor VR ₃ as shown in FIG. 6 (g), the output of the comparator CMP ₃ becomes high level and the AND circuit AND ₁ Output becomes high level, and the output of NOR circuit NOR ₁ becomes low level.
4 output * Q _NG becomes low level as shown in FIG. 6 (h). As a result, the voltmeter M is connected to the analog switch SW _C.
The high voltage value when is turned off is displayed, and it is possible to determine the abnormality of the sample.

By the way, in this embodiment, the voltmeter M is used to display the abnormality of the sample. However, the AND circuit AND ₁ , A
It is also possible to use the output of ND ₂ as an abnormality detection output,
It is possible to distinguish between withstand voltage failure and insulation failure by a factor of two.

[0044]

As described above, the invention of claim 1 comprises high voltage generating means for generating a high DC voltage applied to a sample.
Voltage detecting means for detecting a high voltage value applied to the sample, current detecting means for detecting a current flowing through the sample, and reference voltage generating means for generating a reference voltage for setting a high voltage value applied to the sample And a voltage control means for controlling the voltage value of the high voltage generated by the high voltage generation means so as to find the difference between the reference voltage of the reference voltage generation means and the voltage value detected by the voltage detection means and eliminate the difference. And an abnormality detecting means for detecting an abnormality of the sample from the current detected by the current detecting means, and it is turned on when the abnormality of the sample is detected by the abnormality detecting means to instantly step down the high voltage applied to the sample. It is equipped with a switching element, and it is judged that the sample is abnormal by using a switching element with excellent response such as a thyristor instead of a high-voltage relay with slow response. When, it is possible to step down the high voltage applied to the sample by switching elements instantly Thus without deteriorating the sample, it is possible to perform the withstand voltage test.

According to a second aspect of the present invention, as the reference voltage generating means, the value of the reference voltage is gradually increased from 0 V from the start of the test, and a high voltage value applied to the sample after an appropriate time is a specified value for performing the withstand voltage test. It is possible to increase the high voltage applied to the sample gradually so that a large charging current does not flow to the stray capacitance even if the sample has stray capacitance. It is possible to suppress the current value of the charging current for charging the stray capacitance to be smaller than the current value determined to be abnormal by the abnormality detecting means so that the abnormality detecting function of the withstand voltage test device is not affected.

According to the third aspect of the present invention, since the switching element is turned on even at the end of the test, when the sample has a stray capacitance, the electric charge charged in the stray capacitance is measured at the end of the test. It is possible to discharge through the switching element, and there is no electric shock even if the sample is touched after the test.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is a specific circuit diagram of the above.

FIG. 3 is an operation explanatory diagram when there is no load.

FIG. 4 is an operation explanatory diagram when the sample is a non-defective product.

FIG. 5 is an operation explanatory diagram when the sample has a poor breakdown voltage.

FIG. 6 is an operation explanatory diagram in the case where the sample has an insulation failure.

[Explanation of symbols]

1 high voltage generator 2 voltage detecting unit 3 current detector 4 the reference voltage generating unit 5 voltage controller 6 abnormality detecting unit 40 ramp generator Q _1, Q ₂ thyristor

Claims (3)

[Claims] 1. A high voltage generation means for generating a high DC voltage applied to a sample, a voltage detection means for detecting a voltage value of the high voltage applied to the sample, and a current detection for detecting a current flowing through the sample. Means, a reference voltage generating means for generating a reference voltage for setting the value of the high voltage applied to the sample, and a difference between the reference voltage of the reference voltage generating means and the voltage value detected by the voltage detecting means is calculated. The voltage control means for controlling the voltage value of the high voltage generated by the high voltage generation means so as to eliminate the difference, the abnormality detection means for detecting the abnormality of the sample from the current detected by the current detection means, and the abnormality detection means A withstand voltage test apparatus comprising: a switching element that is turned on when an abnormality of the sample is detected and that instantaneously steps down the high voltage applied to the sample. 2. The reference voltage generating means, wherein the value of the reference voltage is gradually increased from 0V from the start of the test, and the value of the high voltage applied to the sample after an appropriate time is used as the specified value for the withstand voltage test. It uses, It is characterized by the above-mentioned.
The pressure resistance test device described. 3. The breakdown voltage test apparatus according to claim 1, wherein the switching element is turned on even at the end of the test.