JPH07146813A - Image memory with logical operation function - Google Patents

Abstract

PURPOSE:To speed up the image processing of image memory. CONSTITUTION:A logical operation part 2 and an arithmetic code register 3 are provided inside an image memory chip 1. The arithmetic code register 3 is constituted of four bits R0-R3. Image data S inputted from the I/O terminal 5 of the image memory chip 1 is inputted to the logical operation part 2 before it is written on a memory cell 6, and simultaneously, data D is outputted from the memory cell 6 on which write is desired to perform. and it is inputted to the logical operation part 2. The logical operation part 2 performs a logical operation among the arithmetic codes R0-R3, the input image data S, and the output data D from the memory cell 6, and a computed result is written on the memory cell 6.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to image memory chips.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional image processing circuit has a source data holding section 8 provided outside an image memory chip 7.
The operation code holding unit 9, the memory data holding unit 10, and the logical operation unit 11 were included. When performing arithmetic processing with the data in the image memory chip 7, the write data from the CPU 12 is held in the source data holding unit 8 in the T1 cycle shown in FIG. A cycle is generated and the data in the image memory chip 7 is once read into the memory data holding unit 10. Next, in the T2 cycle of FIG.
1, the operation code held in the operation code holding unit 9 is calculated between the data in the source data holding unit 8 and the data in the memory data holding unit 10, and finally T3 in FIG.
The calculation result is written back to the image memory chip 7 in a cycle.

[0003]

In this conventional image processing circuit, the delay of data is large due to the fact that the logical operation processing unit is realized by the external circuit, and the performance of the memory chip cannot be utilized to the maximum extent. There are drawbacks, and in image processing, there are many read-modify-write processings, so that the memory cycle is very slow as compared with the CPU cycle.

An object of the present invention is to provide an image memory with high speed logical operation processing.

[0005]

The image memory of the present invention comprises:
It includes an image memory cell, a logical operation unit for performing a logical operation between the data in the image memory cell and the data to be written in the write cycle, and an operation code register for setting the type of the logical operation to be executed.

[0006]

Even if a logical operation is required between the data existing in the image memory cell and the write data, it can be processed only in the write cycle. Also, by placing the logical operation unit inside the memory chip, the delay of the logical operation circuit is eliminated, and the processing speed is increased.

[0007]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of an image memory according to an embodiment of the present invention, and FIG. 2 is its time chart. The image memory chip 1 has a memory cell 6, a logical operation unit 2 and an operation code register 3 inside. The logical operation unit 2 is

[0009]

[Equation 1] It is composed of a logical operation circuit represented by the following equation. The operation code register 3 is composed of 4 bits of R0 to R3, corresponds to R0 to R3 of the logical operation expression, and sets data according to the operation to be executed by the logical operation unit 2. C
When a write cycle occurs from the PU 4 to the image memory chip 1, the image data is input from the I / O terminal 5 into the image memory chip 1 and is input to the logical operation unit 2 before being written to the memory cell 6 to perform logical operation. It becomes the data of the S part of the equation. At the same time, the memory cell 6 to be written
The data is output from and is input to the logical operation unit 2 and becomes the data of the D section of the logical operation expression. In the logical operation unit 2, the operation code R0 to R3, the image data S to be written, and the output data D from the memory cell 6 are operated, and the operation result is written in the memory cell 6. As described above, the series of processes is executed only in the T1 cycle shown in the time chart of FIG.

[0010]

As described above, the present invention has the operation code register and the logic operation unit in the image memory chip, so that the logic operation is required between the data existing in the image memory and the write data. However, the processing can be performed only in the write cycle, and by disposing the logical operation unit inside the memory chip, the delay of the logical operation circuit can be eliminated, and the processing speed can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of an image memory according to an embodiment of the present invention.

FIG. 2 is a time chart of the embodiment of FIG.

FIG. 3 is a block diagram of a conventional image processing circuit.

FIG. 4 is a time chart of the image processing circuit of FIG.

[Explanation of symbols]

 1 Image Memory Chip 2 Logical Operation Section 3 Operation Code Register 4 CPU 5 I / O Terminal 6 Memory Cell 7 Image Memory Chip 8 Source Data Holding Section 9 Operation Code Holding Section 10 Memory Data Holding Section 11 Logical Operation Section 12 CPU

Claims (2)

[Claims] 1. An image memory cell, a logical operation unit for performing a logical operation between data in the image memory cell and data to be written in a write cycle, and an operation code register for setting the type of the logical operation to be executed. Image memory with logical operation function. 2. The image memory with logical operation function according to claim 1, wherein the operation code register is composed of 4 bits of R0 to R3 and corresponds to R0 to R3 of the logical operation expression.