JPH07143424A - Phase control circuit for clock signal - Google Patents

Abstract

PURPOSE:To control a phase of a sampling clock signal of video signal data for a dot matrix display device properly by shifting a clock signal used for sampling the video signal data based on an additional signal superimposed for a horizontal blanking period. CONSTITUTION:A blanking (BL) period detection circuit 1 detects a back porch of a video signal S1 for a horizontal BL period and a signal generating circuit 2 generates an additional signal S3 so as to match the phase therewith. The signal S3 is superimposed on the signal S1 by a superimposing circuit 3. The superimposed signal is sampled by a clock signal S4 from a clock shift circuit 6, a data detection circuit 5 detects sampling data via an A/D converter circuit 4 and controls the shift circuit 6 so that the detected data are normal data to shift an original clock signal S2. The signal S2 becomes the clock signal S4 whose phase is shifted by a required amount through the control and normal sampling is conducted. The video signal sampled normally is fed to a signal processing circuit 7 and displayed on a liquid crystal display panel 11, then deterioration in the picture quality is prevented in the sampling stage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase control circuit for a clock signal, and more specifically, to a video signal data display in a dot matrix type display such as LCD (liquid crystal display) or PDP (plasma display panel). The present invention relates to a circuit that controls a clock signal used for sampling to have an appropriate phase.

[0002]

2. Description of the Related Art Conventionally, in a display shown in the block diagram of FIG. 3 using an LCD (liquid crystal display), an analog video signal S31 is a clock signal in an A / D conversion circuit 31.
It is sampled by S32 and converted into a digital signal, and after predetermined signal processing (signal processing circuit 32), it is converted back to an analog signal by the clock signal S32 (D / A circuit 3).
3), after being amplified to a predetermined level by the amplifier 35, a video signal is supplied to the liquid crystal panel 36 through the alternating circuit 35. However, when displaying video signals from various signal sources (for example, various personal computers), the sampling position is deviated from the normal position and the display quality (image quality) is deteriorated because the timing of the display position is different. There was a problem. For example, although the sampling clock signal should originally have the phase relationship shown in FIG. 2 (E) with respect to the video signal shown in FIG. 2 (A), the phase may shift as shown in FIG. 2 (F). In addition, since the video signal has an annotated waveform as shown by the dotted line in FIG. 9A due to the frequency band limitation of the circuit at the processing stage, the phase of the clock signal is inappropriate as shown in FIG. In some cases, the display quality is further deteriorated.

[0003]

Therefore, the sampling clock signal must have a phase relationship with which any video signal is sampled at the center of the video data. It is an object of the present invention to provide a circuit that controls the phase of a clock signal so that sampling is performed at the center of video data for any video signal.

[0004]

SUMMARY OF THE INVENTION According to the present invention, a horizontal blanking period detection circuit for detecting a horizontal blanking period of an analog video signal and an additional signal having a predetermined waveform used for detecting sampling data are detected. An additional signal generating circuit that is generated during the ranking period, a superimposing circuit that superimposes the additional signal during the horizontal blanking period of the analog video signal, and an analog signal from the superimposing circuit is digitally converted by a clock signal from a clock shift circuit. A / D conversion circuit, data detection circuit for detecting sampling data relating to the additional signal from the digital signal from the A / D conversion circuit, original clock signal, and sampling data of the additional signal detected by the data detection circuit The original clock signal so that the clock signal becomes predetermined data. There is provided a phase control circuit of the clock signal is constituted by a clock shift circuit for shifting the phase.

[0005]

The data detection additional signal having a predetermined waveform is superimposed in the horizontal blanking period of the analog video signal. The analog video signal on which the additional signal is superimposed is A / D converted by the clock signal from the clock shift circuit. Same A /
The sampling data of the superimposed additional signal is detected from the D-converted digital signal. The clock shift circuit shifts the phase of the original clock signal so that the detected data becomes predetermined data.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A clock signal phase control circuit according to the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an essential part showing an embodiment of a clock signal phase control circuit according to the present invention, and FIG. 2 is a time chart for explaining FIG. In FIG. 1, S1 is an analog video signal, 1 is a blanking detection circuit for detecting the horizontal blanking period of the analog video signal S1, and 2 is for detecting the sampling state of the controlled original clock signal S2 during the horizontal blanking period. An additional signal generating circuit for generating the additional signal S3, 3 is a superimposing circuit for superimposing the additional signal S3 in the horizontal blanking period of the analog video signal S1, and 4 is a clock signal S4 for digitalizing the analog video signal from the superimposing circuit 3. A / convert to signal
D conversion circuit, 5 is a data detection circuit for detecting the sampling data of the additional signal from the digital signal from the A / D conversion circuit 4, and 6 is a controlled original clock signal S2 based on the signal from the data detection circuit 5. It is a shift circuit that corrects the phase. It should be noted that the reference numeral 7 and thereafter are the same as those in FIG.
Reference numeral 7 is a signal processing circuit for performing a predetermined process, 8 is a D / A conversion circuit for returning a digital signal to an analog signal, 9 is an amplifier for setting a predetermined level, 10 is an alternating circuit, and 11 is a liquid crystal panel.

Next, the operation of the present invention will be described. The blanking period detection circuit 1 detects the back porch of the analog video signal S1 during the horizontal blanking period, and the additional signal generation circuit 2 generates the additional signal S3 so that the back porch of the detected horizontal blanking period is in phase. To do. The generated additional signal S3 is used by the superimposing circuit 3 to generate the analog video signal S1.
Superimpose on. A concrete waveform example of the additional signal S3 is shown in FIG.
And (C). The waveform shown is for facilitating the suitability of sampling data. The additional signal S3 of either (B) or (C) above is converted to the analog video signal S1.
(A in the same figure) It overlaps with the back porch portion in the horizontal blacking period. FIG. 7D shows a case where the additional signal shown in FIG. It should be noted that the video signal is a rectangular wave as shown in FIG. 9A, the symbol a in the figure indicates a horizontal synchronizing signal, and the symbol b indicates a color burst signal. Superimposing circuit 3 that superimposes the additional signal S3
The analog signal is sampled by the clock signal S4 from the clock shift circuit 6 and converted into a digital signal (A / D conversion circuit 4). The A / D conversion naturally includes the additional signal S3, and the data detection circuit 5 detects the sampling data of the additional signal S3. FIG. 2 (E) shows the clock signal S4, and when the phase relationship between the clock signal and the additional signal is as shown in the figure, that is, the rising timing (arrow) of the clock signal coincides with the center of the additional signal. At some point, the normal sampling state is assumed.

Normal sampling when the additional signal is as shown in FIG. 6B is half of the maximum output Vo at the output of the A / D conversion circuit 4, and the additional signal is as shown in FIG. When the maximum output Vo is reached. For example, when the A / D conversion output is an 8-bit signal (maximum value 256), the normal sampling state is where the detected data is 128 for the former and 256 for the latter. That is, the data detection circuit 5 detects the sampling data relating to the additional signal in the A / D conversion output, and shifts the shift circuit 6 so that the detected data has a normal value (128 or 256 in the above example).
To shift the original clock signal S2. By this control, the controlled original clock signal S2 becomes the clock signal S4 with the required phase shift, and normal sampling is performed. As a result, the normal sampling shown in FIGS. 9A and 9E is also performed during sampling during the video period. The video signal normally sampled in this way is sent to the signal processing circuit 7, and thereafter, is displayed on the liquid crystal panel 11 through the same process as the conventional one, so that the image quality deterioration at the sampling stage is prevented.

[0009]

As described above, according to the present invention, in a dot matrix type display such as an LCD (liquid crystal display) or a PDP (plasma display panel) which displays video signals from various video sources, the video signal Since the clock signal used for data sampling is controlled to have an appropriate phase based on the additional signal superimposed in the horizontal blanking period, appropriate sampling can be performed for any video signal. Therefore, it is possible to solve the conventional problem that the sampling position is deviated depending on the video signal and the display image quality is deteriorated.

[Brief description of drawings]

FIG. 1 is a principal block diagram showing an embodiment of a clock signal phase control circuit according to the present invention.

FIG. 2 is a time chart of an analog video signal S1, a reference signal S3, and a clock signal S4.

FIG. 3 is a principal block diagram showing an example of a conventional video circuit.

[Explanation of symbols]

 1 blanking period detection circuit 2 additional signal generation circuit 3 superposition circuit 4 A / D conversion circuit 5 data detection circuit 6 shift circuit S1 analog video signal S2 controlled original clock signal S3 additional signal S4 sampling clock signal

Claims (3)

[Claims] 1. A horizontal blanking period detection circuit for detecting a horizontal blanking period of an analog video signal, and an additional signal of a predetermined waveform used for detecting sampling data,
An additional signal generation circuit that is generated during the detected blanking period, a superimposing circuit that superimposes the additional signal during the horizontal blanking period of the analog video signal, and an analog signal from the superimposing circuit that is a clock signal from a clock shift circuit. A / D conversion circuit for performing digital conversion by means of, a data detection circuit for detecting sampling data related to the additional signal from the digital signal from the A / D conversion circuit, an original clock signal, and the addition detected by the data detection circuit. A clock signal phase control circuit configured to shift the phase of the original clock signal so that the sampling data of the signal becomes the clock signal that becomes predetermined data. 2. The clock signal phase control circuit according to claim 1, wherein the additional signal is a signal that continuously changes between a maximum value and zero. 3. The clock signal phase control circuit according to claim 1, wherein the additional signal is a signal which changes from zero to a maximum value and continuously changes to zero again.