JPS61157084A - Display device - Google Patents

Abstract

PURPOSE:To superimpose stably a video information signal from a memory device part by adding a periodic signal preparing by a omission detection or a removing action of a horizontal synchronous signal to a reproducing composite video signal as a horizontal synchronous signal and by outputting a periodical signal. CONSTITUTION:In case of omission of a horizontal synchronous signal E6, a horizontal synchronous signal omission detecting circuit 5 makes signal Ec into '1'. And a horizontal synchronous signal forcible interpolation control circuit 6 synchronous with a vertical synchronous signal Ed and makes a signal Ee into '1' for previously specified time (much noise occurred). In a compensating horizontal synchronous signal generating circuit 7, a synchronous signal generating circuit 9 outputs a signal of period 1H same as a horizontal synchronous signal E6 when a signal Ec or Ee is '1'. Adding to this output signal and horizontal synchronous signal Eb, an adder 10 outputs compensating horizontal synchronous signal El. Therefore, it is possible to read out video information signal from the memory device part even if it is temporary stoppage state. The reproducing composite video signal El added the horizontal synchronous signal of picture stoppage section is outputted to a display part 21.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention superimposes a video information signal read out from a memory unit onto a reproduced composite video signal from a video playback device such as a VTR (video tape recorder). and CRT
(Cathode ray tube) etc., more specifically, it corresponds to the detection of missing horizontal synchronizing signals included in the reproduced composite video signal and the predetermined time near the retrace time of vertical synchronizing signals. The present invention relates to a display device which removes a horizontal synchronizing signal and adds and outputs a periodic signal created based on each operation of detecting or removing a horizontal synchronizing signal as a horizontal synchronizing signal to a reproduced composite video signal.

(Prior Art) Conventionally, display devices have been used that convert video information such as characters and graphics stored in a memory unit into a predetermined signal and superimpose it on a composite video signal reproduced by a video player. Are known.

This type of display device includes, for example, means for individually separating horizontal and vertical synchronization signals contained in a reproduced composite video signal (analog signal) of a video reproduction device, and a memory device using the synchronization signals by the means. Some devices are equipped with means for reading out data while synchronizing the parts, converting the data into O/A, and adding (mixing) the data to the reproduced composite video signal of the video reproduction device and outputting it to the display part.

In the above configuration, the display device can superimpose the desired video information signal stored in the memory unit onto the reproduced composite video signal of the video reproduction device using the synchronization signal obtained from the reproduced composite video signal. can.

(Problem to be Solved by the Invention) However, conventional display devices have a configuration that relies only on the synchronization signal included in the composite video signal reproduced by the video playback device, so the video playback If the synchronization signal in the reproduced composite video signal of the device is missing, there is a problem that reading from the memory device section is not possible during that time, and the composite image on the display section is severely distorted. Particularly in the case of a VTR, when the reproduced image is paused and the video information signal from the memory unit is superimposed, the horizontal synchronization signal is lost for several H (H is the period of the horizontal synchronization signal), so cannot be used. In addition, there is a lot of noise in the vicinity of the retrace time of the vertical synchronization signal of the reproduced composite video signal of the video reproduction device, and it is difficult to separate the horizontal synchronization signal, so there is a problem that the composite image is unstable.

(Means for Solving the Problems) The present invention has been made in view of the above, and its purpose is to prevent the memory device from disabling the memory even when the reproduced composite video signal is in a pause state or near the retrace line of the vertical synchronization signal. An object of the present invention is to provide a display device capable of stably superimposing video information signals from a video source.

A display device of the present invention that achieves the above object detects the omission of a horizontal synchronizing signal included in a reproduced composite video signal, removes a horizontal synchronizing signal corresponding to a predetermined time near the retrace time of a vertical synchronizing signal, and , a periodic signal created based on each operation of detecting or removing a horizontal synchronization signal is added to the reproduced composite video signal as a horizontal synchronization signal and output.

(Example) Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a configuration diagram showing an embodiment of the present invention. A display device is divided into a signal processing section and a memory device section. The signal processing section receives the reproduced composite video signal Ea from the video reproduction device 1.
horizontal synchronization signal separation circuit 2 and vertical synchronization signal separation circuit 3
and the reproduced composite video signal correction circuit 4, respectively.

The horizontal synchronization signal separation circuit 2 constitutes means for creating a corrected horizontal synchronization signal together with the following circuits. That is, the means:
The horizontal synchronizing signal separation circuit 2 separates the horizontal synchronizing signal Eb from the reproduced composite video signal Ea, and when the 1H interval of the horizontal synchronizing signal Eb is detected and the 1H signal is not detected, 1111
At a predetermined time near the retrace time of the horizontal synchronization signal missing detection circuit 5 which outputs the signal EC of 1 and the vertical synchronization signal Ed from the vertical synchronization signal separation circuit 3 (particularly in the section where there is a lot of noise during pause), A horizontal synchronization signal forced interpolation control circuit 6 that outputs a signal Ee for forcibly removing a horizontal synchronization signal component from the reproduced composite video signal Ea, and a signal E. , Eo and E.

and a corrected horizontal synchronizing signal generation circuit 7 which inputs the corrected horizontal synchronizing signal Ef and outputs a corrected horizontal synchronizing signal Ef. The corrected horizontal synchronization signal generation circuit 7 generates signals E and E. OR gate 8 inputs
and a synchronous signal oscillation circuit 9 controlled by an OR gate 8,
It has an adder 10 that adds and outputs the output signal of the synchronization signal oscillation circuit 9 and the signal E. The reproduced composite video signal correction circuit 4 is controlled by the signal Ee, and the reproduced composite video signal E
Signal Eg from which horizontal open 11 signal components in a specific section of a are removed
A signal clear circuit 11 that outputs a signal Eg, a signal E,
, and a horizontal interpolation synchronization signal addition circuit 12 that outputs a corrected reproduced composite video signal Eh.

On the other hand, the memory device section receives the signal Ed, the phase synchronization circuit 13 (
The read clock generation circuit 14 and the frequency dividing circuit 15 generate signals @E1
It has a character/figure memory control circuit 17 that performs predetermined processing based on a signal E from a circuit that creates a signal E synchronized with Under the control of the memory control circuit 17, characters and
Desired data is read from the graphic memory 18, signal conversion is performed by the D/A converter 19, and a video information signal E to be superimposed is provided to the character/graphic signal adder 20. And a character/figure signal adder 20
adds the signal E to the signal Eh, and outputs the combined signal E1 to the display section 21.

Next, the operation of the display device will be explained with reference to FIGS. 2 and 3.

In accordance with the playback operation, the reproduced composite video signal Ea from the video reproduction device 1 is simultaneously given to the horizontal synchronization signal separation circuit 2, the vertical synchronization signal separation circuit 3, and the signal clear circuit 11, and the horizontal synchronization signal separation circuit 2 receives the horizontal synchronization signal Eb. (Fig. 2 (a)), and the vertical synchronization signal separation circuit 3 outputs the vertical synchronization signal Ed.
(FIG. 3(a)) and outputs them, and the signal clear circuit 11 receives the control signal E from the horizontal synchronization signal forced interpolation control circuit 6. Take action based on. At this time, the horizontal synchronizing signal loss detection circuit 5 checks whether the horizontal synchronizing signal Eb is missing or not, and if there is a loss, the signal E is detected. 1′
(Figure 2 (b)). Further, the horizontal synchronization signal forced interpolation control circuit 6 synchronizes with the vertical synchronization signal Ed and inputs the signal E for a predetermined certain period of time (a time with a lot of noise).

is set to 1" (Fig. 3 (b)). In the correction horizontal synchronization signal generation circuit 7 to which these signals are input, the synchronization signal oscillation circuit 9 generates a signal when the signal E is 1" or when the signal E is 1". ′
1'', a signal with the same period of 1H as the horizontal synchronization signal Eb is output, and the adder 10 adds the output signal of the synchronization signal oscillation circuit 9 and the horizontal synchronization signal E to generate a corrected horizontal synchronization signal Ef. (Fig. 2 (c) and Fig. 3 (c)).

That is, when the horizontal synchronizing signal Eb from the video reproduction device 1 is stable as the corrected horizontal synchronizing signal Ef, the horizontal synchronizing signal Eb itself is output, and the reproduced composite video signal Ea
When the horizontal synchronizing signal Eb is missing or the horizontal synchronizing signal Eb is unstable, the synchronizing signal oscillation circuit 9
The signal from is output. Therefore, the corrected horizontal synchronizing signal generation circuit 7 always outputs a stable corrected horizontal synchronizing signal Ef while the reproduced composite video signal Ea is being applied. This corrected horizontal synchronization signal E-1 is used as a reference for horizontal synchronization signals for signals output within and outside the apparatus.

In the reproduced composite video signal correction circuit 4, the signal clear circuit 11 outputs the signal E. Therefore, the reproduced composite video signal E
A certain section of the horizontal synchronizing signal Eb is forcibly removed from the horizontal synchronization signal Eb, that is, a reproduced composite video signal Eg with one forced interpolation section cleared is output (FIG. 3 (d)). Then, the horizontal interpolation synchronization signal addition circuit 12 adds a corrected horizontal synchronization signal E to this reproduced composite video signal Eg, and sends the composite signal (corrected reproduced composite video signal) Eh to the character/graphic signal adder 20. Output (Figure 3 (e)).

On the other hand, in the phase synchronization circuit 13, the readout clock generation circuit 14 inputs the corrected horizontal synchronization signal E1, activates the feedback loop of the frequency divider circuit 15, and reads out the multiplied correction horizontal synchronization signal E while maintaining phase synchronization. Outputs clock E. The character/graphic memory control circuit 17 receives the drawing signal Ej from the character/graphic writing device 16, and outputs the read clock E,
The desired video information data is read out in synchronization with the vertical synchronization signal Ed, and an address is generated for the character/graphic memory 18. One D/A converter converts the video information data in the character/figure memory 18 into an analog video information signal Ek.
and outputs it to the character/graphic signal adder 20 (second
Figure (e)). The character/graphic signal adder 20 combines (mixes) this video information signal E with the corrected reproduced composite video signal E from the reproduced composite video signal correction circuit 4, and outputs the composite signal (mixed signal). The composite video signal) El is output to the display section 21 (Fig. 2)).

In the above operation J5, the corrected horizontal synchronization signal Ef is output even when the image based on the reproduced composite video signal Ea is in a paused state, so even in the paused state, the video information signal can be read from the memory device section. can be done, and
A reproduced composite video signal E1 to which a horizontal synchronization signal of the image stop section is added can be output to the display unit 21. Furthermore, the horizontal synchronization signal E included in the reproduced composite video signal Ea corresponds to the noisy section near the retrace time of the vertical synchronization signal Ed.

Since the corrected horizontal synchronizing signal E generated by the corrected horizontal synchronizing signal generating circuit 7 is used instead, the horizontal synchronizing signal included in the reproduced composite video signal E1 in the section can be stabilized.

(Effects of the Invention) As described above, according to the display device of the present invention, missing horizontal synchronizing signals included in a reproduced composite video signal are detected, and horizontal In addition to removing the synchronization signal, a periodic signal created based on each operation of detecting or removing a horizontal synchronization signal is added to and output as a horizontal periodic signal to the reproduced composite video signal, so that the reproduction composite video signal is Even in a pause state or near the retrace time of the vertical synchronization signal, the video edge fW signal from the memory device section can be stably superimposed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are diagrams illustrating the operation of the present invention. DESCRIPTION OF SYMBOLS 1... Video reproduction device, 2... Horizontal synchronization signal separation circuit, 3... Vertical synchronization signal valve 1 circuit, 4... Playback composite video signal correction circuit, 5... Horizontal synchronization signal missing detection Circuit, 6...Horizontal synchronization signal forced interpolation control circuit, 7...Correction horizontal synchronization signal generation circuit, 9...Synchronization signal oscillation circuit,
12... Horizontal interpolation synchronization signal addition circuit, 13... Phase synchronization circuit, 14... Read clock generation circuit, 16...
・Character/figure writing device, 17...Character/figure memory control circuit, 18...Character/figure memory, 20...Character/figure signal adder 20°

Claims (1)

[Scope of Claim] A separation circuit that separately separates each horizontal and vertical synchronization signal from a reproduced composite video signal of a video playback device, and a memory device section that reads out synchronization signals obtained from the separation circuit in synchronization with the separation circuit. A display device comprising an adder circuit that superimposes a video information signal on the reproduced composite video signal and outputs it to a display section, comprising: a horizontal synchronization signal loss detection circuit that detects a loss of the horizontal synchronization signal from the separation circuit; and the separation circuit. a horizontal synchronization signal forced interpolation control circuit for removing the horizontal synchronization signal in the reproduced composite video signal at a predetermined time in the vicinity of the retrace time of the vertical synchronization signal from the horizontal synchronization signal, a separation circuit for the horizontal synchronization signal, and a horizontal synchronization signal loss detection circuit. and a corrected horizontal synchronization signal generation circuit that creates a reference signal for a horizontal synchronization signal based on each output signal of the horizontal synchronization signal forced interpolation control circuit, and the reproduced composite video signal processed by the horizontal synchronization signal forced interpolation control circuit. A display device comprising: a reproduced composite video signal correction circuit that corrects the reproduction composite video signal using the reference signal.