JPH07142611A - Manufacture of mask rom - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a mask ROM, which increases the memory capacity without increasing its dimensions as well as the read-out margin easily. CONSTITUTION:When ions are implanted two times so as to differ-set different threshold voltages for the first, second, third and fourth memory cell transistors a0, b0, c0, d0 after finishing the first time ion implantation, the interlayer insulating films 17 on the second and fourth memory cell transistors b0, d0 parts are made thinner by etching away step using the same mask. Next, the other new masks 20 for opening the third and fourth memory cell transistors c0, d0 parts are formed to start the second time ion implantation for differentiating the ion transmittivity due to the difference between the thickness of the interlayer insulating films 17 of both memory cell transistors c0, d0 so that ions 21 may be sufficiently implanted in the channel part 14 of the fourth memory cell transistor do thereby enabling the threshold value voltage to be distributed at equi- intervals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a mask ROM in which ion implantation for ROM data is performed in plural times.

[0002]

2. Description of the Related Art As is well known, for example, a mask ROM composed of NOR type memory cells stores data by changing the threshold voltage of memory cell transistors. The threshold voltage is set by controlling the ion implantation from above the gate electrode after forming the gate that also serves as the word line of the memory cell transistor, the source and the drain. The memory cell thus formed is "0",
Only two types of information "1" can be written, and the number of memory cell transistors is required for the storage capacity of the mask ROM.

Therefore, a multi-valued ROM (MULTIPULLE STA) in which the memory capacity of the mask ROM is increased by writing three or more kinds of information in one memory cell.
TEROM CELLS). Such multi-value ROM
Then, for example, if four types of information can be written in one memory cell, the storage capacity can be doubled without increasing the chip area.

Further, in such a multi-valued ROM, TAT
(TURN AROUND TIME), that is, as a method of shortening the period from the acquisition of data from the user to the predetermined writing to the shipment of the product, ionization is performed by using a plurality of masks having different patterns after forming the gate electrode. A manufacturing method is known in which the implantation is performed a plurality of times to change the threshold voltage of the memory cell transistor to three or more to write data.

A conventional example will be described below with reference to FIGS. 11 to 15. 11 is a schematic sectional view showing the first step, FIG. 12 is a schematic sectional view showing the second step, and FIG. 13 is a schematic sectional view showing the third step.
FIG. 14 is a characteristic diagram showing the drain current with respect to the gate voltage, and FIG. 15 is a diagram showing the relationship between the ion implantation amount and the threshold voltage of the memory cell transistor.

First, in the first step shown in FIG.
a, b, c and d are formed so that their threshold voltages are different from each other, and data is written in the multi-valued ROM.
The first, second, third, and fourth memory cell transistors constituting the above, and are prepared in advance as standard. In each of the transistors a, b, c, d, 1 is a first conductivity type silicon (Si) substrate, 2 is a second conductivity type source diffusion layer, and 3 is a second conductivity type drain diffusion layer. is there.

Reference numeral 4 is a gate insulating film made of a silicon oxide film and having a thickness of 0.015 μm. Reference numeral 5 is a gate electrode made of polycrystalline silicon doped with impurities such as phosphorus (P) and having a thickness of 0.4 μm. And 6 is a channel part. Then, in each of the transistors a, b, c, and d having such a form, four different data based on predetermined information are written correspondingly in the subsequent steps.

Next, in a second step shown in FIG. 12, a resist is deposited on the upper surface of each of the transistors a, b, c and d for the first ion implantation, and then the second and fourth resists are deposited.
Of the upper surface of the memory cell transistors b and d of
Each gate electrode 5 is removed by photolithography until it is exposed, and a mask 7 for the first ion implantation is formed. And
Using this mask 7, ions 8 are implanted into the channel portion 6 of the silicon substrate 1 of the second and fourth memory cell transistors b and d through the exposed gate electrode 5. For the ion implantation, for example, boron (B) ions are used as the ions, and the dose amount is 2 × 10 ¹³ cm at an acceleration voltage of 170 kV.
^It is performed so that it becomes ⁻² .

Subsequently, in a third step shown in FIG.
The resist on which the mask 7 has been formed for the first time is removed, and instead of this, a resist is deposited again for performing the second ion implantation on the upper surfaces of the respective transistors a, b, c, d, and then the third and fourth resists are deposited. The resist on the upper surface of the memory cell transistors c and d is removed by photolithography until each gate electrode 5 is exposed, and a mask 9 for the second ion implantation is formed.

Then, using this mask 9, ions 10
Is injected into the channel portion 6 of the silicon substrate 1 of the third and fourth memory cell transistors c and d through the exposed gate electrode 5. For the ion implantation, for example, boron ions are used as ions, and the dose amount is 4 at an acceleration voltage of 170 kV.
It is performed so as to be × 10 ¹³ cm ⁻² .

As a result, each of the transistors a, b, c,
Based on the ion implantation amount in the first transistor a, the total ion implantation amount in d is 0 in the first memory cell transistor a and 2 × 10 ^{13 in the} second memory cell transistor b. cm ^-2, the third in the memory cell transistor c 4 × 10 ¹³ cm ^-2, further fourth in the memory cell transistor d 6 × 10 ¹³ cm ^-2.

The drain current with respect to the gate voltage of each of the ion-implanted transistors a, b, c, d is shown by curves Ia, Ib, Ic, I shown in FIG.
d, four different data are written in the first, second, third, and fourth memory cell transistors a, b, c, and d by two times of ion implantation to form a multi-value ROM. .

However, in such writing, the ion implantation into the fourth memory cell transistor d is performed by the third independent ion implantation step similar to the second and third memory cell transistors b and c. Instead, it is performed by the sum of dose amounts by two times of ion implantation using the two masks 7 and 9.

The relationship between the threshold voltage of the memory cell transistor and the amount of ion implantation has a curve X shown in FIG. This curve X is given by the following equation when the threshold voltage is V _th and the substrate impurity concentration (the amount of ion implantation into the substrate) is N _{A. V th = V FB + 2Ф F} + 1 / C OX × (2K S · ε O · q · N A · 2Ф F) -2 Incidentally, V _FB: flat band voltage, .PHI _F: intrinsic level of the Fermi level of the substrate and Difference C _OX : capacitance per area of gate oxide film K _S : relative permittivity of silicon ε _O : relative permittivity of vacuum q: unit charge (charge of one electron) From this relationship, the first and second doses The threshold voltage of each of the transistors a, b, c, d cannot be made to have an equal interval by appropriately setting the amount. That is, the higher the threshold voltage, the closer the two threshold voltages are.

[0015] Then, in the memory cell, considering that the threshold voltage V _th of the memory cell transistors constituting this varies, To distinguish four states of the write formed by the transistors, respectively the threshold voltage V _th of
Would be desired to be as far apart as possible. For example, when it is attempted to read the written information with a gate voltage of 5V, it is more advantageous to set the threshold voltage equal to or less than the read voltage. However, as described above, in the conventional ion implantation, each transistor a,
The threshold voltages of b, c and d were not evenly spaced, and the read margin was small.

[0016]

As described above, in the conventional example, a multi-valued ROM capable of increasing the storage capacity without increasing the chip area can be formed by a small number of independent ion implantation steps. However, the threshold voltage of each of the plurality of memory cell transistors cannot be distributed at equal intervals below the read voltage, and the read margin is small. The present invention has been made in view of such a situation, and an object of the present invention is to increase the storage capacity without increasing the size and to easily make the threshold voltage of the memory cell transistor equal to or less than the read voltage at equal intervals. It is an object of the present invention to provide a method of manufacturing a mask ROM that can be distributed and can increase a read margin.

[0017]

According to the method of manufacturing a mask ROM of the present invention, ion implantation is divided into a plurality of times so that the threshold voltage varies depending on the memory cell transistor. In the method of manufacturing a mask ROM for storing predetermined data by performing the ion implantation at least twice in the channel portion of the memory cell transistor, the ion implantation was performed after the first ion implantation. It is characterized by including a step of changing the thickness by etching the ion permeation limiting member on the channel portion using a mask, and further, the ion permeation limiting member is provided on the gate electrode. It is characterized in that it is an insulating film, and further that the ion permeation limiting member is a gate electrode. It is an.

[0018]

In the method of manufacturing the mask ROM configured as described above, the first ion implantation is performed when the ion implantation is performed at least twice in the channel portion of the memory cell transistor so that the threshold voltage varies depending on the memory cell transistor. After that, there is a step of changing the thickness by etching the ion permeation limiting member on the channel portion using the mask used for this ion implantation, so that the impurity concentration in the channel portion of each memory cell transistor is set to a threshold value. The voltage can be appropriately set so as to be distributed at equal intervals, and different data can be surely written. When the written data is to be read, the threshold voltages of the transistors are equally spaced apart from each other. As a result, the storage capacity can be increased without increasing the size and the read margin can be easily increased.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

First, a first embodiment will be described with reference to FIGS. FIG. 1 is a schematic sectional view showing a first step,
2 is a schematic sectional view showing the second step, FIG. 3 is a schematic sectional view showing the third step, FIG. 4 is a schematic sectional view showing the fourth step, and FIG. FIG. 6 is a schematic cross-sectional view showing a fifth step, FIG. 6 is a diagram showing an impurity profile of a channel portion of a memory cell transistor, and FIG. 6A is an impurity profile of a first memory cell transistor. 6B is a diagram showing the impurity profile of the second memory cell transistor, and FIG. 6C is a diagram showing the impurity profile of the third memory cell transistor. FIG. 6D is a diagram showing the impurity profile of the fourth memory cell transistor, and FIG. 7 is a characteristic diagram showing the drain current with respect to the gate voltage.

In the first step shown in FIG. 1, a ₀ , b
₀ , c ₀ , and d ₀ are formed so that their threshold voltages are different from each other, and data is written in the multi-valued ROM.
The first, second, third, and fourth memory cell transistors constituting the memory cell, which are prepared as standard through known manufacturing processes in the same manner as described in the conventional example. In each of the transistors a ₀ , b ₀ , c ₀ , d ₀ ,
Reference numeral 11 denotes a first-conductivity-type silicon substrate, and a second-conductivity-type source diffusion layer 12 is provided on the silicon substrate 11.
Similarly, the second conductivity type drain diffusion layers 13 are formed so as to be spaced apart from each other so that the channel portion 14 is provided therebetween.

Reference numeral 15 is a gate insulating film made of a silicon oxide film and having a thickness of 0.015 μm.
2 and the drain diffusion layer 13 are provided on the upper surface of the silicon substrate 11 on the channel portion 14, and the gate insulating film 1
A gate electrode 16 made of polycrystalline silicon doped with impurities such as phosphorus and having a thickness of 0.4 μm is provided on the gate electrode 5. Then, by changing the threshold voltage of each of the transistors a ₀ , b ₀ , c ₀ , and d _{0 of} such a form, based on predetermined information in the subsequent process,
Different kinds of data are written correspondingly.

Next, in a second step shown in FIG. 2, a silicon oxide (SiO 2) having a thickness of 0.4 μm is formed on the upper surface of each transistor a ₀ , b ₀ , c ₀ , d _{0 by} a known method, for example, a CVD method. The interlayer insulating film 17 of ₂ ) is formed.

Next, in a third step shown in FIG. 3, a resist is deposited on the upper surface of each of the transistors a ₀ , b ₀ , c ₀ , d ₀ in order to perform the first ion implantation, and then the second and fourth resists are deposited. The resist on the upper surfaces of the memory cell transistors b ₀ and d ₀ is removed by photolithography until the interlayer insulating film 17 on each gate electrode 16 is exposed to form a mask 18 for the first ion implantation. Then, the silicon substrate 1 under the gate electrodes 16 of the second and fourth memory cell transistors b ₀ and d ₀ is implanted with the ions 19 through the interlayer insulating film 17 and the gate electrode 16 exposed by using the mask 18.
1 for the channel section 14. Ion implantation is performed, for example, using boron ions as ions so that the dose amount becomes 1.5 × 10 ¹³ cm ⁻² at an acceleration voltage of 270 kV.

Then, in the fourth step shown in FIG.
RIE (Rea
The thickness of the interlayer insulating film 17, which is the ion permeation limiting member of the second and fourth memory cell transistors b ₀ and d ₀ , is set to 0.1 by the active ion etching.
Etching is performed so that the thickness becomes μm.

Further, in the fifth step shown in FIG.
The resist on which the mask 18 for the second time is formed is removed, and instead of this, a resist is deposited on the upper surfaces of the transistors a ₀ , b ₀ , c ₀ , d _{0 for} the second ion implantation,
Then, the third and fourth memory cell transistors c ₀ and d ₀
The resist on the upper surface of is removed by photolithography until the interlayer insulating film 17 on each gate electrode 16 is exposed to form a mask 20 for the second ion implantation.

Then, ions 21 are formed through the interlayer insulating film 17 and the gate electrode 16 exposed by using the mask 20.
Is injected into the third and fourth memory cell transistors c ₀ and d.
The channel portion 14 of the silicon substrate 11 below the _zero gate electrode 16 is formed. In the ion implantation, for example, boron ions are used as ions, and the range peak (Rp) is the interlayer insulating film 17.
And a dose amount of 7.0 × 10 ¹³ cm ⁻² at an acceleration voltage of 230 kV so that the thickness is smaller than the laminated thickness of the gate electrode 16 and the gate insulating film 15.

As a result, in the fourth memory cell transistor d ₀ in which the thickness of the interlayer insulating film 17 is 0.1 μm by etching, the thickness of the interlayer insulating film 17 is 0.
Ions 21 are sufficiently implanted into the channel portion 14 of the silicon substrate 11 because the transmission of ions is not limited as compared with the third memory cell transistor c ₀ which is still 4 μm. As a result, the transistors a ₀ , b ₀ ,
Impurity profile P of the channel portion 14 of c ₀ and d ₀
The schematic states of a ₀ , Pb ₀ , Pc ₀ , and Pd ₀ are shown in FIG. 6A to FIG. 6A in which the horizontal axis represents the depth from the surface of the silicon substrate 11 and the vertical axis represents the impurity concentration on a log scale. d)
It will be the street. Incidentally, the impurity concentration of the first memory cell transistor a ₀ is 10 ¹⁶ cm ⁻³ to 10 ¹⁷ cm.
^{It is -3} .

In each of the transistors a ₀ , b ₀ , c ₀ and d ₀ thus formed, the first, second and third memory cell transistors a ₀ and b are formed at the time of ion implantation.
_The second ion implantation dose is determined so that the threshold voltages of ₀ and c ₀ are evenly spaced. Further, regarding the ion implantation of the fourth memory cell transistor d ₀ , the impurity concentration of boron in the channel portion 14 of the silicon substrate 11 is set to the second,
By setting the impurity concentrations of the third memory cell transistors b ₀ and c ₀ to be equal to or higher than the combined concentration,
The threshold voltages of both the fourth memory cell transistors c ₀ and d ₀ are not close to each other, and each of the transistors a ₀ ,
The threshold voltages of b ₀ , c ₀ and d ₀ are distributed at equal intervals at a voltage equal to or lower than the read voltage.

Each of these transistors a ₀ , b ₀ ,
The drain current with respect to the gate voltage of c ₀ and d ₀ is shown in FIG.
The curves Ia ₀ , Ib ₀ , Ic ₀ , and Id ₀ shown in FIG. 4 are obtained, and four different data are obtained by two times of ion implantation, and the first, second, third, and fourth memory cell transistors a ₀ , The data is written in b ₀ , c ₀ and d ₀ to form a multi-valued ROM.

Since this embodiment is constructed as described above, the first, second, third, and fourth memory cell transistors can be easily formed by performing the ion implantation process twice using the two masks 18 and 20. The threshold voltages of a ₀ , b ₀ , c ₀ , and d ₀ can be distributed at equal intervals to write four different data. When the written data is to be read, the transistors a ₀ , b ₀ , c ₀ ,
Since the threshold voltage of d ₀ is a voltage equal to or lower than the read voltage and is evenly spaced, and the threshold voltages are spaced apart from each other, the read margin becomes large.

Next, a second embodiment will be described with reference to FIGS. It should be noted that this embodiment is composed of steps substantially similar to those of the first embodiment, and steps different from those of the first embodiment will be described below. 8 is a schematic sectional view showing the fourth step, and FIG. 9 is a schematic sectional view showing the fifth step.
0 is a diagram showing the impurity profile of the channel portion of the memory cell transistor, FIG. 10 (a) is a diagram showing the impurity profile of the first memory cell transistor, and FIG. 10 (b) is a second diagram. FIG. 11C is a diagram showing an impurity profile of the memory cell transistor, and FIG.
Is a diagram showing the impurity profile of the third memory cell transistor, and FIG. 10D is a diagram showing the impurity profile of the fourth memory cell transistor.

First, in the fourth step (corresponding to the fourth step of the first embodiment) shown in FIG. 8, a ₁ , b ₁ , c ₁ ,
d ₁ is a first, a second, a third and a fourth memory cell transistor which are formed to have different threshold voltages and form a multi-valued ROM by writing data,
Each of the transistors a ₀ , b ₀ , c ₀ , d _{0 of} the first embodiment.
The channel portion of the silicon substrate 11 under the gate electrodes 16 of the second and fourth memory cell transistors b ₁ and d ₁ through the same first to third steps as in the first embodiment. 14, boron ions are used as ions, and the dose amount is 1.5 × 10 ¹³ at an acceleration voltage of 270 kV.
The first ion implantation is performed using the mask 18 so as to be cm ⁻² .

Then, the mask 18 for the first ion implantation is used.
The RIE is used to etch the interlayer insulating film 17 which is the ion permeation limiting member in the second and fourth memory cell transistors b ₁ and d ₁ so as to have a thickness of 0 to 0.05 μm. That is, etching is performed so that the upper surface of the gate electrode 16 is exposed or the thin interlayer insulating film 17 of 0.05 μm remains.

Subsequently, in a fifth step (corresponding to the fifth step of the first embodiment) shown in FIG. 9, the mask 18 for the first time is performed.
The resist that has formed is removed, and in place of this, a resist is deposited on the upper surface of each of the transistors a ₁ , b ₁ , c ₁ , and d ₁ for performing the second ion implantation, and then the third and fourth resists are deposited.
The resist on the upper surfaces of the memory cell transistors c ₁ and d ₁ is removed by photolithography until the interlayer insulating film 17 on each gate electrode 16 is exposed to form a mask 22 for the second ion implantation.

Then, ions 23 are implanted through the exposed interlayer insulating film 17 and the gate electrode 16 using the mask 22 or the exposed gate electrode 16 in the third and fourth steps.
Gate electrodes 16 of the memory cell transistors c ₁ and d ₁ of
This is performed on the channel portion 14 of the lower silicon substrate 11. Ion implantation is performed twice using, for example, boron ions as ions. The first time, an acceleration voltage of 180 kV and a dose of 7
× 10 ¹³ cm ⁻² , the second time is 270
dose at an acceleration voltage of kV is 4 × 10 ¹³ cm ^- performed so that ^2.

Thus, in the fourth memory cell transistor d ₁ in which the interlayer insulating film 17 is removed or the thickness thereof is thin, the thickness of the interlayer insulating film 17 is 0.
Ions 23 are sufficiently implanted into the channel portion 14 of the silicon substrate 11 rather than the third memory cell transistor c ₁ which is still 4 μm. As a result, the outline states of the impurity profiles Pa ₁ , Pb ₁ , Pc ₁ , Pd ₁ of the channel portion 14 of each of the transistors a ₁ , b ₁ , c ₁ , d ₁ are plotted along the horizontal axis from the surface of the silicon substrate 11. Take depth,
FIG. 10 showing the impurity concentration on the vertical axis by a log scale.
As shown in (a) to (d).

In each of the transistors a ₁ , b ₁ , c ₁ and d ₁ thus formed, the third and fourth memory cell transistors c ₁ and d ₁ are formed as in the first embodiment.
The threshold voltages of the two transistors do not become close to each other, and the threshold voltages of the respective transistors a ₁ , b ₁ , c ₁ , d ₁ are distributed at equal intervals below the read voltage to form a new mask. 4 different data are written in the first, second, third and fourth memory cell transistors a ₁ , b ₁ , c ₁ and d ₁ by ion implantation using two masks 18 and 22 without using the multi-value ROM. Is configured.

Since this embodiment is constructed as described above, the same operation and effect as those of the first embodiment can be obtained.

In each of the above embodiments, by changing the thickness of the interlayer insulating film 17 which is the ion permeation limiting member on the gate electrode 16, the ion transmissivity is changed and the ion implantation amount is changed to change the ion implantation amount of the channel portion 14. The impurity concentration is set to each of the transistors a ₀ , b ₀ , c ₀ and d ₀ of the first embodiment or each of the transistors a ₁ , b ₁ , c ₁ and d _{1 of} the second embodiment.
However, the impurity concentration of the channel portion 14 may be controlled by changing the thickness of the gate electrode 16 which also serves as the ion permeation limiting member by etching, and may be appropriately changed within a range not departing from the gist. Can be carried out.

[0041]

As is apparent from the above description, according to the present invention, the thickness of the ion permeation limiting member on the channel portion is changed when performing the ion implantation in plural times so that the threshold voltage is different depending on the memory cell transistor. By adopting the configuration including the step of controlling the ion transmittance, the ion implantation is performed after the first ion implantation when the ion implantation is performed at least twice in the channel portion of the memory cell transistor. By adopting a configuration that includes a step of changing the thickness by etching the ion permeation limiting member on the channel portion using the mask used for the above, it is possible to increase the storage capacity without increasing the size and to easily read data. The effect that the margin can be increased can be obtained.

[Brief description of drawings]

FIG. 1 is a schematic sectional view showing a first step of the first embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a second step of the first embodiment of the present invention.

FIG. 3 is a schematic sectional view showing a third step of the first embodiment of the present invention.

FIG. 4 is a schematic sectional view showing a fourth step of the first embodiment of the present invention.

FIG. 5 is a schematic sectional view showing a fifth step of the first embodiment of the present invention.

FIG. 6 is a diagram showing an impurity profile of a channel portion of the memory cell transistor according to the first embodiment of the present invention, and FIG. 6A is a diagram showing an impurity profile of the first memory cell transistor. 6B is a diagram showing the impurity profile of the second memory cell transistor, and FIG. 6C is a diagram showing the impurity profile of the third memory cell transistor.
(D) is a figure which shows the profile of the impurity of a 4th memory cell transistor.

FIG. 7 is a characteristic diagram showing a drain current with respect to a gate voltage in the first embodiment of the present invention.

FIG. 8 is a schematic sectional view showing a fourth step of the second embodiment of the present invention.

FIG. 9 is a schematic sectional view showing a fifth step of the second embodiment of the present invention.

FIG. 10 is a diagram showing an impurity profile of a channel portion of a memory cell transistor according to a second embodiment of the present invention, and FIG. 10A is a diagram showing an impurity profile of a first memory cell transistor. Yes, FIG.
10B is a diagram showing an impurity profile of the second memory cell transistor, FIG. 10C is a diagram showing an impurity profile of the third memory cell transistor, and FIG. 10D is a fourth diagram. FIG. 6 is a diagram showing an impurity profile of the memory cell transistor of FIG.

FIG. 11 is a schematic sectional view showing a first step of a conventional example.

FIG. 12 is a schematic cross-sectional view showing a second step of the conventional example.

FIG. 13 is a schematic sectional view showing a third step of the conventional example.

FIG. 14 is a characteristic diagram showing a drain current with respect to a gate voltage in a conventional example.

FIG. 15 is a diagram showing a relationship between an ion implantation amount and a threshold voltage of a memory cell transistor.

[Explanation of symbols]

14 ... Channel part 16 ... Gate electrode 17 ... Interlayer insulating film 18, 20 ... Mask 19, 21 ... Ion a ₀ ... 1st memory cell transistor b ₀ ... 2nd memory cell transistor c ₀ ... 3rd memory cell transistor d ₀ ... Fourth memory cell transistor

Claims (3)

[Claims] 1. A mask RO in which predetermined data is stored in a channel portion of a plurality of preformed memory cell transistors by performing ion implantation in plural times so that the threshold voltage varies depending on the memory cell transistor.
In the method of manufacturing M, when the ion implantation is performed at least twice in the channel portion of the memory cell transistor, the ions on the channel portion are formed using the mask used for the ion implantation after the first ion implantation. A method of manufacturing a mask ROM, comprising the step of etching the transmission limiting member to change its thickness. 2. The method of manufacturing a mask ROM according to claim 1, wherein the ion permeation limiting member is an interlayer insulating film provided on the gate electrode. 3. The method of manufacturing a mask ROM according to claim 1, wherein the ion permeation limiting member is a gate electrode.