JPH0714032B2 - Method of manufacturing thin film resistor - Google Patents

Method of manufacturing thin film resistor

Info

Publication number
JPH0714032B2
JPH0714032B2 JP59227311A JP22731184A JPH0714032B2 JP H0714032 B2 JPH0714032 B2 JP H0714032B2 JP 59227311 A JP59227311 A JP 59227311A JP 22731184 A JP22731184 A JP 22731184A JP H0714032 B2 JPH0714032 B2 JP H0714032B2
Authority
JP
Japan
Prior art keywords
thin film
oxide film
forming
window
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59227311A
Other languages
Japanese (ja)
Other versions
JPS61104653A (en
Inventor
光一郎 見崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59227311A priority Critical patent/JPH0714032B2/en
Publication of JPS61104653A publication Critical patent/JPS61104653A/en
Publication of JPH0714032B2 publication Critical patent/JPH0714032B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はモノリシツク集積回路装置に薄膜抵抗を形成す
る製造方法に関するものである。
The present invention relates to a manufacturing method for forming a thin film resistor in a monolithic integrated circuit device.

〔従来の技術〕[Conventional technology]

従来、モノリシツク集積回路装置に薄膜抵抗を形成する
場合、その材料として低い温度係数,長期安定性を有す
るNiCr,SiCr等が用いられてきた。
Heretofore, when forming a thin film resistor in a monolithic integrated circuit device, NiCr, SiCr or the like having a low temperature coefficient and long-term stability has been used as a material thereof.

この薄膜抵抗を形成する製造方法について、第2図を参
照しながら説明する。まずN型半導体基板201にP型ベ
ース領域202,N+型エミツタ領域203,N+型コレクタオーミ
ツク領域204を形成し、その表面には熱酸化膜205を成長
する(第1図(a))。
A manufacturing method for forming the thin film resistor will be described with reference to FIG. First, a P type base region 202, an N + type emitter region 203, and an N + type collector ohmic region 204 are formed on an N type semiconductor substrate 201, and a thermal oxide film 205 is grown on the surface thereof (FIG. 1 (a)). ).

次にNPNトランジスタ212の各領域上にコンタクト用窓20
6を空け、酸化により下地酸化膜207を形成した後、更に
気相成長により窒化膜208と酸化膜209とを形成する(第
2図(b))。
Next, a contact window 20 is formed on each region of the NPN transistor 212.
After leaving 6 and forming a base oxide film 207 by oxidation, a nitride film 208 and an oxide film 209 are further formed by vapor phase growth (FIG. 2 (b)).

次にコンタクト用窓206の内側の酸化膜209を除去し、残
された酸化膜209をマスクとして熱リン酸にて窒化膜208
を除去し、更に酸化膜209とコンタクト用窓206に位置す
る下地酸化膜207とを同時に除去して内側コンタクト用
窓214を空け、この状態で半導体基板全面にNiCr,SiCr等
の薄膜層210を被着する(第2図(c))。
Next, the oxide film 209 inside the contact window 206 is removed, and the remaining oxide film 209 is used as a mask to form a nitride film 208 with hot phosphoric acid.
Is removed, and further the oxide film 209 and the underlying oxide film 207 located in the contact window 206 are simultaneously removed to open the inner contact window 214, and in this state, a thin film layer 210 of NiCr, SiCr or the like is formed on the entire surface of the semiconductor substrate. It is attached (Fig. 2 (c)).

次に写真蝕刻法により薄膜抵抗体以外の薄膜層を除去し
薄膜抵抗体211を形成する。この後アルミニウム等の金
属を用いてNPNトランジスタ212と薄膜抵抗体211とに金
属配線213を施し、熱処理によりオーミツクコンタクト
を得る(第2図(d))。
Next, the thin film layers other than the thin film resistor are removed by photolithography to form a thin film resistor 211. After that, a metal wiring 213 is formed on the NPN transistor 212 and the thin film resistor 211 by using a metal such as aluminum, and an ohmic contact is obtained by heat treatment (FIG. 2 (d)).

ところで従来の製造方法によれば、第2図(c)に示す
ように、クロムを含有する金属層がシリコン面とコンタ
クト用窓214を通して接触しているのでクロム汚染が生
じる。このシリコン面のクロムは第2図(c)以降の工
程で除去されるが、完全には除去されず微量に残る。そ
してその後の熱処理や組立後の熱履歴により、トランジ
スト特性に悪影響を及ぼすことになる。
By the way, according to the conventional manufacturing method, as shown in FIG. 2 (c), since the metal layer containing chromium is in contact with the silicon surface through the contact window 214, chromium contamination occurs. Chromium on the silicon surface is removed in the steps after FIG. 2 (c), but is not completely removed and remains in a trace amount. The subsequent heat treatment and thermal history after assembly adversely affect the transistor characteristics.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

本発明は上記従来例の欠点に鑑み提案されたものであ
り、シリコン面にクロムが直接接触することのない薄膜
抵抗の製造方法の提供を目的とする。
The present invention has been proposed in view of the drawbacks of the above-mentioned conventional example, and an object thereof is to provide a method of manufacturing a thin film resistor in which chromium does not directly contact the silicon surface.

〔問題点を解決するための手段〕[Means for solving problems]

本発明に係る薄膜抵抗の製造方法は、半導体基板にP型
領域とN型領域とを形成し、かつ該半導体基板表面に第
1の熱酸化膜を形成する工程、前記P型領域とN型領域
上の前記第1の熱酸化膜に第1の窓を空ける工程、前記
第1の窓に第2の熱酸化膜を形成する工程、前記第1お
よび第2の熱酸化膜上に気相成長窒化膜を形成する工
程、前記気相成長窒化膜に前記第1の窓に包含されるべ
く第2の窓を空ける工程、前記第2の窓に位置する前記
第2の熱酸化膜を同時に除去する工程、前記第2の窓に
第3の熱酸化膜を形成する工程、前記半導体基板表面に
金属薄膜層を形成する工程、前記金属薄膜層を薄膜抵抗
体に形成する工程、前記第3の熱酸化膜を除去する工
程、前記薄膜抵抗体と前記第2の窓に金属配線を形成
し、熱処理を施す工程とからなることを特徴とする。
A method of manufacturing a thin film resistor according to the present invention comprises the steps of forming a P-type region and an N-type region on a semiconductor substrate and forming a first thermal oxide film on the surface of the semiconductor substrate, the P-type region and the N-type region. Forming a first window in the first thermal oxide film on the region, forming a second thermal oxide film in the first window, vapor phase on the first and second thermal oxide films A step of forming a grown nitride film, a step of forming a second window in the vapor phase grown nitride film so as to be included in the first window, and a step of simultaneously forming the second thermal oxide film located in the second window. Removing step, forming a third thermal oxide film on the second window, forming a metal thin film layer on the surface of the semiconductor substrate, forming the metal thin film layer on a thin film resistor, the third step Removing the thermal oxide film, forming a metal wiring in the thin film resistor and the second window, and performing a heat treatment. And wherein the Ranaru.

〔実施例〕〔Example〕

以下図面を参照して本発明の実施例を説明する。第1図
は本発明の実施例に係る薄膜抵抗の製造方法を説明する
ための図である。まずN型半導体基板101にP型ベース
領域102およびN+型エミツタ領域103,N+型コレクタオー
ミツク領域104を形成し、表面に熱酸化膜105を成長する
(第1図(a))。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram for explaining a method of manufacturing a thin film resistor according to an embodiment of the present invention. First, a P-type base region 102, an N + -type emitter region 103, and an N + -type collector ohmic region 104 are formed on an N-type semiconductor substrate 101, and a thermal oxide film 105 is grown on the surface (FIG. 1 (a)).

次にNPNトランジスタ112の各領域上にコンタクト用窓10
6を空け、窒化膜108と酸化膜109とを形成する(第1図
(b))。
Next, a contact window 10 is formed on each region of the NPN transistor 112.
6 is opened, and a nitride film 108 and an oxide film 109 are formed (FIG. 1 (b)).

次にコンタクト用窓106の内側の酸化膜109を除去して残
された部分をマスクとして熱リン酸にて窒化膜108を除
去し、更に酸化膜109とコンタクト用窓106に位置する下
地酸化膜107とを同時に除去して内側に第2のコンタク
ト用窓114を空ける。更にこの部分をもう一度酸化によ
つて下敷酸化膜120を形成する。この状態で半導体基板
全面にNiCr,SiCr等の薄膜層110を被着する(第3図
(c))。
Next, the oxide film 109 inside the contact window 106 is removed, and the remaining portion is used as a mask to remove the nitride film 108 with hot phosphoric acid. Further, the oxide film 109 and the underlying oxide film located on the contact window 106 are removed. 107 and 107 are removed at the same time to form a second contact window 114 inside. Further, this portion is again oxidized to form the underlying oxide film 120. In this state, a thin film layer 110 of NiCr, SiCr or the like is deposited on the entire surface of the semiconductor substrate (FIG. 3 (c)).

次に写真蝕刻法により薄膜層110をエツチングして薄膜
抵抗体111を形成する。なおこの時の薄膜層110のエツチ
ングの際、下敷酸化膜120が第2のコンタクト用窓114に
残るように下敷酸化膜の厚さを設定してある。その後コ
ンタクト用窓214上の下敷酸化膜を除去し、アルミニウ
ム等の金属を用いてNPNトランジスタ112と薄膜抵抗体11
1とに金属配線113を施し、熱処理によりオーミツクコン
タクトを得る(第3図(d))。
Next, the thin film layer 110 is etched by photolithography to form a thin film resistor 111. The thickness of the underlying oxide film is set so that the underlying oxide film 120 remains in the second contact window 114 during the etching of the thin film layer 110 at this time. After that, the underlying oxide film on the contact window 214 is removed, and NPN transistor 112 and thin film resistor 11 are formed by using a metal such as aluminum.
Metal wiring 113 is applied to 1 and an ohmic contact is obtained by heat treatment (FIG. 3 (d)).

〔発明の効果〕〔The invention's effect〕

以上説明したように、本発明によれば工程上金属薄膜層
が直接シリコン面に接触することがないので、シリコン
面が金属に含まれるクロム等の汚染を受けることがな
い。従つてその後の熱履歴によるトランジスタの特性の
劣化を防止できる。
As described above, according to the present invention, since the metal thin film layer does not directly contact the silicon surface in the process, the silicon surface is not contaminated with chromium or the like contained in the metal. Therefore, it is possible to prevent deterioration of transistor characteristics due to subsequent thermal history.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の実施例に係る薄膜抵抗の製造方法を説
明するための図であり、第2図は従来例に係る薄膜抵抗
の製造方法を説明するための図である。 101,201…N型半導体基板、102,202…P型ベース領域、
103,203…N+型エミツタ領域、104,204…N+型コレクタオ
ーミツクコンタクト領域、105,205…フイールド酸化
膜、106,206…コンタクト用窓、107,207…下地酸化膜、
108,208…気相成長窒化膜、109,209…気相成長酸化膜、
110,210…薄膜層、111,211…薄膜抵抗体、112,212…NPN
トランジスタ、113,213…金属配線、114,214…第2のコ
ンタクト用窓、120…下敷酸化膜。
FIG. 1 is a diagram for explaining a method of manufacturing a thin film resistor according to an embodiment of the present invention, and FIG. 2 is a diagram for explaining a method of manufacturing a thin film resistor according to a conventional example. 101,201 ... N-type semiconductor substrate, 102,202 ... P-type base region,
103,203 ... N + type emitter region, 104,204 ... N + type collector ohmic contact region, 105,205 ... Field oxide film, 106,206 ... Contact window, 107,207 ... Base oxide film,
108,208 ... Vapor grown nitride film, 109,209 ... Vapor grown oxide film,
110, 210 ... Thin film layer, 111, 211 ... Thin film resistor, 112, 212 ... NPN
Transistors, 113, 213 ... Metal wiring, 114, 214 ... Second contact window, 120 ... Underlay oxide film.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半導体基板に拡散領域を形成する工程、 前記半導体基板表面に第1の熱酸化膜を形成する工程、 前記拡散領域上の前記第1の熱酸化膜に前記拡散領域に
達する第1の窓を空ける工程、 前記第1の窓の前記拡散領域表面に第2の熱酸化膜を形
成する工程、 前記第1及び第2の熱酸化膜上に気相成長窒化膜を形成
する工程、 前記気相成長窒化膜上に酸化膜を形成してパターニング
し、この酸化膜をマスクとして前記気相成長窒化膜に前
記第1の窓に包含されるべく第2の窓を空け、前記酸化
膜を除去すると同時に前記第2の窓に位置する前記第2
の熱酸化膜を除去して前記拡散領域表面を露出する工
程、 前記第2の窓の前記拡散領域表面露出部分に第3の熱酸
化膜を形成する工程、 前記半導体基板表面に金属薄膜を形成する工程、 前記金属薄膜を薄膜抵抗に形成する工程、 前記第3の熱酸化膜を除去する工程、 前記薄膜抵抗体と前記第2の窓に金属配線を形成し、熱
処理を施す工程とからなることを特徴とする薄膜抵抗の
製造方法。
1. A step of forming a diffusion region in a semiconductor substrate, a step of forming a first thermal oxide film on the surface of the semiconductor substrate, a step of reaching the diffusion region in the first thermal oxide film on the diffusion region. Opening a first window, forming a second thermal oxide film on the surface of the diffusion region of the first window, forming a vapor phase growth nitride film on the first and second thermal oxide films An oxide film is formed on the vapor-grown nitride film and patterned, and a second window is formed in the vapor-grown nitride film using the oxide film as a mask so as to be included in the first window. The second film located on the second window at the same time as removing the film
Removing the thermal oxide film to expose the surface of the diffusion region, forming a third thermal oxide film on the exposed surface of the diffusion region of the second window, and forming a metal thin film on the surface of the semiconductor substrate. A step of forming the metal thin film into a thin film resistor, a step of removing the third thermal oxide film, a step of forming a metal wiring in the thin film resistor and the second window, and performing a heat treatment. A method of manufacturing a thin film resistor, comprising:
JP59227311A 1984-10-29 1984-10-29 Method of manufacturing thin film resistor Expired - Lifetime JPH0714032B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59227311A JPH0714032B2 (en) 1984-10-29 1984-10-29 Method of manufacturing thin film resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59227311A JPH0714032B2 (en) 1984-10-29 1984-10-29 Method of manufacturing thin film resistor

Publications (2)

Publication Number Publication Date
JPS61104653A JPS61104653A (en) 1986-05-22
JPH0714032B2 true JPH0714032B2 (en) 1995-02-15

Family

ID=16858811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59227311A Expired - Lifetime JPH0714032B2 (en) 1984-10-29 1984-10-29 Method of manufacturing thin film resistor

Country Status (1)

Country Link
JP (1) JPH0714032B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2762473B2 (en) * 1988-08-24 1998-06-04 株式会社デンソー Method for manufacturing semiconductor device
JP3255995B2 (en) * 1992-10-23 2002-02-12 株式会社日立製作所 Videophone equipment

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5916362A (en) * 1982-07-19 1984-01-27 Matsushita Electronics Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS61104653A (en) 1986-05-22

Similar Documents

Publication Publication Date Title
JPH0714032B2 (en) Method of manufacturing thin film resistor
JPH0511668B2 (en)
JPS6336140B2 (en)
JPH04112532A (en) Manufacture of semiconductor integrated circuit
JPS6356708B2 (en)
JPH0366815B2 (en)
JPS5933271B2 (en) Manufacturing method of semiconductor device
JPS58170012A (en) Manufacture of semiconductor device
JPS6214953B2 (en)
JPH0117256B2 (en)
JPS63211755A (en) Manufacture of semiconductor device
JPS60226160A (en) Manufacture for thin film resistance device
JPS5952550B2 (en) Manufacturing method of semiconductor device
RU795311C (en) Method of manufacturing transistor structures
JP2817184B2 (en) Method for manufacturing semiconductor device
JPS628939B2 (en)
JPS5889861A (en) Semiconductor device and its manufacture
JPS5923515A (en) Impurity diffusion method
JPS6327863B2 (en)
JPH02226758A (en) Semiconductor device
JPH047588B2 (en)
JPS6165447A (en) Manufacture of semiconductor device
JPH0576767B2 (en)
JPS588140B2 (en) Manufacturing method of semiconductor device
JPS6359259B2 (en)