JPH0713818B2 - Microprocessor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a microprocessor, and more particularly to a microprocessor having a small time base error of a signal output through an output port.

2. Description of the Related Art In recent years, Neumann microprocessors have been widely used in all fields, and their configurations include a program storage means for storing a program consisting of a series of instructions to be sequentially executed and a data storage for reading / writing digital data. Means, an arithmetic means for executing arithmetic operation of digital data, a data bus connecting the input / output terminal of the data storage means and the input / output terminal of the arithmetic means, and the above-mentioned means based on an instruction sent from the program storage means. Control means for controlling the operations of the data storage means and the arithmetic means, a timing generator for generating an instruction execution timing signal, and a specific instruction stored in the program storage means based on the output of the timing generator. Characterized by having instruction selection means To be In addition, the typical structure is Japanese Patent Publication Sho 58-33.
No. 584 (hereinafter referred to as Document 1).

SUMMARY OF THE INVENTION However, the Neumann method microprocessor as shown in the above-mentioned document 1 executes data processing in a predetermined order, and therefore asynchronously as the program becomes huge. The cycle of inputting external data and processing of the data based on it becomes long, and as a result, the variation in the time from the occurrence of the event to the output signal from the microprocessor,
That is, there is a problem that the time base error becomes considerably large. Conventionally, a means called an interrupt has been used to deal with such a problem. However, even if an interrupt request is made, it cannot move to the interrupt process unless the instruction being executed at that time is processed. Had a problem that a timebase error occurred in the time itself from when an interrupt was accepted until the interrupt service routine was actually started.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a microprocessor having an output port capable of outputting a series of signal patterns with a small time base error.

Means for Solving the Problems To achieve this object, a microprocessor of the present invention comprises a free-running counter that performs a cyclic count operation based on a specific clock signal, and comparison data that stores at least two types of digital data. Storage means, comparison data selection means for selecting any one of the data of the comparison data storage means according to a selection command signal, and the comparison data selected by the comparison data selection means of the count data of the free running counter. Based on the match signal output from the comparing unit that compares the data in the storing unit and outputs a match signal when the data match, a cyclic counting operation is usually performed from the data in the initial state, and , When data is set, the cyclic count operation from that data is performed, and A pointer that outputs count data as the selection command signal, a master latch unit that stores the same number of digital data as the comparison data storage unit, and one of the data of the master latch unit is selected according to the selection command signal. And a slave latch unit for taking in the data of the master latch unit based on the coincidence signal output from the comparing unit.

Operation The present invention can obtain a microprocessor having a small time base error of a signal output through the output port with the above configuration.

Embodiment One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of the microprocessor of the present invention.

In FIG. 1, TMGR100 is a timing generator that generates an instruction execution timing signal based on the clock signal supplied to the external clock input terminal 10, and its output signal is supplied to the PC200, ICR900 and FRC1000. P
The LA300 is a programmable logic array, and stores a program including a group of instructions that are sequentially executed.
PC200 is a program counter, and selects a specific instruction stored in PLA300 based on the output signal of TMGR100.
FRC1000 is a free-running counter, which performs a cyclic counting operation using the output signal of TMGR100 as a clock signal. The count data of FRC1000 is supplied to ICR900 and output port 1100 via local bus 1400. The ICR900 is an input capture register circuit, and when the edge of the input signal applied to the external signal input terminals 20 to 27 arrives, the count data of the FRC1000 at that time is ICR900.
Stored in a specific register in (When multiple input signal edges arrive at the same time, FRC100
The count data of 0 is stored. ), And has a function of setting an input signal acceptance flag (not shown). The command transmitted from the PLA 300 is ALU 400, address decoder 600 (shown as address decoder A in the figure), and address decoder 800 via the command bus 1300.
(Indicated as address decoder B in the figure), ICR
900 and output port 1100. The data bus 1200 is ALU400, ROM500, RAM700, ICR900 and output port 1
Connected to 100. ALU400 is an arithmetic unit that executes arithmetic and logical operations on digital data. The ROM 500 is a read-only memory that sends digital data stored in advance to the data bus 1200. The RAM 700 is a random access memory that reads and writes digital data via the data bus 1200. The output port 1100 outputs a series of signal patterns that can be changed by a program from the signal output terminals 30 to 37. Address decoder 600 is ROM500
Address of the RAM 700 is selected by the address decoder 800.

The operation of the microprocessor of the present embodiment configured as described above will be described below with reference to FIGS. 1 to 5.

The TMGR100 generates an instruction execution timing signal based on the clock signal supplied to the external clock input terminal 10, and supplies this signal to the PC200, ICR900 and FRC1000. PC200
Based on the output signal of TMGR100, a specific instruction is selected from the instruction group stored in PLA300, and PLA300 sends the instruction selected by PC200 to command bus 1300. ALU4
00 executes arithmetic and logical operations of the digital data sent via the data bus 1200 according to the command sent from the command bus 1300, and sends the result to the data bus 1200. The address decoder 600 selects a specific address based on an instruction sent via the command bus 1300, and the ROM 500 transfers the digital data stored in the storage means corresponding to the address selected by the address decoder 600 to the data bus 1200. Send to. The address decoder 800 selects a specific address based on an instruction sent via the command bus 1300, and the RAM 700 sends data from the data bus 1200 to the storage means corresponding to the address selected by the address decoder 800. It stores the incoming digital data or sends the already stored digital data to the data bus 1200.

Next, the output port 1100 will be described with reference to FIGS.

FIG. 2 is a block diagram showing the internal structure of the output port 1100 of FIG. 1, and FIGS. 3, 4, and 5 are timing charts of main parts.

In FIG. 2, comparison data registers 1111-1114 (shown as comparison data registers A, B, C, D in the drawing).
Is a register for storing digital data to be compared with the count data of the FRC1000 in FIG. 1. The comparison data selection circuit 1120 selects any one of the comparison data registers 1111-1114 and stores it in the selected register. The digital data being supplied is supplied to the comparison circuit 1130. The comparison circuit 1130 receives the FR of FIG. 1 via the digital data supplied from the comparison data selection circuit 1120 and the local bus 1400.
The count data supplied from C1000 is compared, and if they match, a match signal is supplied to the slave latch circuit 1160 and the pointer circuit 1170. Also, the address decoder 1110
(Indicated as an address decoder C in the figure) selects an address when storing digital data in the comparison data registers 1111-1114 via the data bus 1200 according to an instruction sent from the command bus 1300. To do.

Master latch 1141-1144 (master latch A,
It is shown as B, C, D. ) Is a latch for storing output data, and the master latch selection circuit 1150 selects one of the master latches 1141 to 1144, and transfers the digital data stored in the selected master latch to the slave latch circuit 1160. Supply. Also,
The address decoder 1140 (indicated as an address decoder D in the figure) follows the instruction sent from the command bus 1300, and when the digital data is stored in the master latches 1141 to 1144 via the data bus 1200, the address is stored. Select. The pointer circuit 1170 stores the digital data transmitted via the data bus 1200 according to the instruction transmitted from the command bus 1300. Further, the pointer circuit 1170 performs a cyclic count operation of the stored digital data based on the coincidence signal of the comparison circuit 1130, and supplies the count data to the comparison data selection circuit 1120 and the master latch selection circuit 1150.

The operation of the output port 1100 configured as above will be described.

Arbitrary digital data is written in the comparison data registers 1111-1114 by a program. For example, when the comparison data register 1111 is written by the program, the address decoder 1110 first selects the comparison data register 1111 according to the instruction sent via the command bus 1300, and the selected comparison data register 1111 is selected. The register 1111 stores digital data sent via the data bus 1200. Similarly, arbitrary digital data is written in the comparison data registers 1112 to 1114. Further, in the master latches 1141 to 1144, arbitrary digital data is similarly written by the program.

Comparison data selection circuit 1120 and master latch selection circuit 11
The reference numeral 50 selects the comparison data registers 1112-1114 and the master latches 1141-1144, respectively, according to the count data supplied from the pointer circuit 1170.

The pointer circuit 1170 cyclically counts from 0 to 3, and count data "0", "1",
The comparison data selection circuit 1120 selects comparison data registers 1111, 1112, 1113, 1114 with respect to '2', '3', and the master latch selection circuit 1150 selects master latches 1141, 1142, 11
Select 43 and 1144 respectively.

Next, the operation of outputting a series of output patterns will be described with reference to FIG.

In FIG. 3, a shows the time change of the count data of the FRC1000, b shows the output data of the pointer circuit 1170, and c shows the comparison data supplied from the comparison data selection circuit 1120 to the comparison circuit 1130. , D is output data supplied from the master latch selection circuit 1150 to the slave latch circuit 1160, and e is the slave latch circuit 1160.
From the comparison circuit 1130 (the signals a to f are the signals of the portions marked with the same symbols in FIG. 2;
Similarly, the signals a to f in FIG. 5 and FIG. 5 show the signals in the same part. ) FRC1000 is a down counter and comparison data register 1
111 to 1114 are comparative data NA, NB, NC, ND (NA>
(NB>NC> ND) is stored, and the master latch 114 is stored.
It is assumed that the output data DA, DB, DC, DD are stored in each of 1 to 1144. When the count data of the pointer circuit 1170 in the initial state is set to "0", the comparison data selection means 1120 selects the comparison data register 1111 and sends the digital data NA stored in this register to the comparison circuit 1130 to be the master. Latch selection circuit 1150 is a master latch 1141
Is selected and the digital data DA stored in this latch is sent to the slave latch circuit 1160.

The comparison circuit 1130 compares the digital data NA supplied from the comparison data selection circuit 1120 with the count data of the FRC1000 shown in FIG. 1 sent via the local bus 1400, and at time t1 in FIG. When the count data of FRC1000 becomes equal to NA, the coincidence signal shown in FIG. 3f is sent to the slave latch circuit 1160 and the pointer circuit 1170. The slave latch circuit 1160 latches the digital data DA stored in the master latch 1141 at the rising edge of the match signal sent from the comparison circuit 1130 as shown in FIG. 3e, and also shown in FIG. 3b. As described above, the pointer circuit 1170 counts up the count data from “0” to “1” by the coincidence signal. When the count data of the pointer becomes "1", the comparison data NB is supplied from the comparison data selection circuit 1120 to the comparison circuit 1130 and the master latch selection to the slave latch circuit 1160 as shown in FIGS. The output data DB is supplied from the circuit 1150.

After that, similarly, the FRC1000 count data and the comparison data selected by the comparison data selection circuit 1120 are compared, and at time t2, t3, and t4, the FRC1000 count data and the comparison data match, so the comparison circuit 1130 Sends a match signal. Then, each time the match signal is sent from the comparison circuit 1130, the slave latch circuit 1160 latches the digital data stored in the master latch selected by the master latch selection circuit, and the pointer circuit 1170 performs the counting operation.

Therefore, compare the count data of the FRC1000 at a certain time with the data after any count and compare data register 11
The slave latch circuit 1160 can output a signal having a series of output patterns by storing arbitrary data in the master latches 1141 to 1144 corresponding to the comparison data registers 1111 to 1114 by storing them in 11 to 1114.

Next, the operation of changing the signal pattern output from the slave latch circuit 1160 will be described with reference to FIG.

When changing a signal pattern during the output of a certain signal pattern, the pointer circuit 1170 is initialized after rewriting the data in the master latches 1141 to 1144 and the comparison data registers 1111-1114. In Figure 4, the pointer circuit
The operation when the signal pattern is changed when the count data of 1170 is "2" is shown.

During the period from time t6 to t7, the data in the master latches 1141 to 1144 are transferred to DA ', DB', DC ', DD' and the comparison data register 1111 to
The data of 1114 is NA ', NB', NC ', ND' (NA '>NB'>
NC '>ND') is completed and the data '0' sent via the data bus 1200 at time t8 is stored in the pointer circuit 1170.
70 initialization is performed. By the initialization of the pointer circuit 1170, the comparison data becomes NA ', as shown in FIGS.
The data supplied from the master latch selection circuit 1150 to the slave latch is changed to DA '. Thereafter, the slave latch circuit 1160 outputs a signal having a new series of output patterns based on the changed comparison data and output data.

By thus initializing the pointer circuit 1170 when changing the signal pattern, the pointer circuit 1170
It is possible to output new signal patterns in the correct order regardless of the count state of. The pointer circuit 1170
The pattern of the output signal can be similarly changed in any of the count states other than '2'.

Next, with reference to FIG. 5, an operation when a part of the data of the set signal pattern is not output will be described.

If you want to stop outputting part of the data of the signal pattern that has already been set, before the data whose output you want to stop is latched by the slave latch circuit 1160, output the count data that corresponds to the data next to the data whose output you want to stop. Set to the pointer. In FIG. 5, after outputting a series of patterns, the output of the data DA and DB corresponding to the count data "0" and "1" of the pointer is temporarily stopped, and the count data "2" and "3" are output. The operation when only the corresponding data DC and DD are output is shown.

The data '2' sent via the data bus 1200 at time t9 is stored in the pointer circuit 1170. Pointer circuit 11
By changing the data of 70 to '2', the comparison data is Nc and the master latch selection circuit as shown in Fig. 5c and d.
The data supplied from the 1150 to the slave latch is Dc. After that, since the count data of the FRC1000 and the comparison data match at times t10 and t11, a match signal is sent from the comparison circuit 1130 as shown in f of FIG. 5, and the master latch selection circuit 1150 is sent to the slave latch circuit 1160. The digital data selected by is latched.

By rewriting the data of the pointer circuit 1170 in this way, it is possible to temporarily stop the data output of a part of the set signal pattern.

In the example of FIG. 5, the output of the data corresponding to "0" and "1" of the count data of the pointer is stopped. However, by rewriting the data of the pointer circuit 1170, the output of the data is output for any data. It is possible to cancel.

In this way, the data transfer from the master latches 1141 to 1144 to the slave latch circuit 1160 is performed by the comparison data register.
It is configured to be automatically performed by the match detection signal of the comparison circuit 1300 that compares 1111 to 1114 with the count data of the FRC1000. When a signal having an arbitrary signal pattern is transmitted from the output port 1100 after a certain time, the time base error can be suppressed to the minimum.

As described above, the present invention provides a free running counter (FR) that performs a cyclic counting operation based on a specific clock signal.
C1000) and comparison data storage means (comparison data register 11 for storing at least two types of digital data)
11 to 1114), comparison data selection means (comparison data selection circuit 1120) for selecting one of the comparison data storage means in accordance with a selection command signal, count data of the free running counter, and the comparison data selection means. Comparing with the data in the comparison data storage means selected in step (1), a comparison means (comparison circuit 1130) for outputting a match signal when they match, and a match signal output from the comparison means is normally used to initialize. The pointer (pointer) that performs the cyclic count operation from the state data and, when the data is set, performs the cyclic count operation from the data and outputs the count data as the selection command signal in any case. Circuit 1170) and a master latch unit (master latches 1141 to 1141) for storing the same number of digital data as the comparison data storage means. 4), and a master latch selection means (master latch selection circuit) for selecting any one of the master latch units according to the selection command signal.
1150) and a slave latch unit (slave latch circuit 1160) for taking in the data of the master latch unit based on the coincidence signal output from the comparison means, the output port (output port 1100).

Therefore, the microprocessor shown in FIGS. 1 and 2 can easily obtain a series of signal pattern outputs with less time base error.

In the embodiment, the comparison data register and the master latch of the output port are each configured with four, but even if two or more are provided depending on the complexity of the pattern of the signal output from the output port, it is completely impossible. Similar effects are obtained.

As described above, according to the present invention, when the edge of the input signal applied to any of the external signal input terminals arrives, the input capture register immediately outputs the count data of the free running counter as timing information at that time. Since it is stored in a specific register in the input capture register, the exact arrival time of the input signal can be confirmed by software, and the output port having a series of signal patterns can output the output signal up to the target time. If the time difference data is sent to the data bus and stored in the comparison data register, and the data stored in the comparison data register that is to be output at each set time is stored in the master latch via the data bus, the time base is output from the output port. A series of signal patterns with few errors can be output. It is possible to obtain a microprocessor capable of achieving high efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram of a microprocessor in one embodiment of the present invention, FIG. 2 is a block diagram showing a concrete configuration example of an output port section in the embodiment, FIGS. 3, 4, and 5 3 is a timing chart of the main part of FIG. 100 ... Timing generator, 200 ... Program counter, 300 ... PLA, 400 ... ALU, 500 ... ROM, 700 ...
… RAM, 900 …… ICR, 1000 …… FRC, 1100 …… Output port, 1111-1114 …… Comparison data register, 1130 …… Comparison circuit, 1141-1144 …… Master latch, 1160 …… Slave latch, 1170… … Pointer circuit.

Claims (1)

[Claims] 1. A free running counter for performing a cyclic counting operation based on a specific clock signal, a comparison data storage means for storing at least two kinds of digital data, and data of the comparison data storage means according to a selection command signal. The comparison data selecting means for selecting any one of the above, and the count data of the free running counter and the data of the comparison data storing means selected by the comparison data selecting means are compared, and a coincidence signal is generated when they coincide. On the basis of the comparing means for outputting and the coincidence signal outputted from the comparing means, normally, the cyclic counting operation from the data in the initial state is performed, and when the data is set, the cyclic counting from the data is performed. Pointer that operates and outputs count data as the selection command signal in any case. A master latch unit that stores the same number of digital data as the comparison data storage unit; a master latch selection unit that selects any one of the data of the master latch unit according to the selection command signal; A microprocessor having an output port formed of a slave latch unit for taking in the data of the unit based on a coincidence signal output from the comparison unit.